JPS5929914B2 - Vending machine sales available - Google Patents

Description

[Detailed description of the invention] [Technical field of high quality paulownia] The present invention calculates and stores the total amount of input coins,
It relates to the sales available device of a vending machine that makes a decision that can be sold by comparing the total input price and the selling price.

[Prior art and its problems]

In conventional vending machines, the total amount of money inserted and the selling price are compared, and if the smallest unit of money has change, the selling price is less than the total amount of money inserted, and if the smallest unit of money has change, it is possible to sell at a selling price that is less than the total amount of money inserted In this case, only the selling price equal to the total input amount was allowed to be sold.

For this reason, if the smallest unit of money does not have change, there is a drawback that even if a large amount of money has change, this large amount of money cannot be used effectively.

[Purpose of the invention]

In view of the above-mentioned points, an object of the present invention is to provide a device for determining whether a vending machine can sell, which makes it possible to effectively use change for a large amount of money even when the smallest unit of money does not have change. shall be.

[Summary of the Invention] The present invention compares the total input amount and the selling price, and if a coin with a higher value than the minimum unit of money has change, the amount of change that can be paid out using the higher value coin is determined. By setting the selling price as a sales price, the purpose is to increase sales opportunities by making effective use of change in large denomination coins.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

In addition, in the example, the currency is ¥10゜¥50. ￥
Consider a case using 100 various coins.

FIG. 1 shows a block diagram of an embodiment according to the invention.

In the figure, 1 is an encoder, 2 is an adder/subtractor, 3 is a shift register for total payout, 4 is a ¥50 number register, 5 is a ¥100 number register, 6 is a change amount and ¥5
0 is compared with ≧50 comparator, 7 is a P1 + 90 addition circuit that adds the highest change amount of ¥90 to the product sales price P1, 8 is a P1 + 50 addition circuit that adds the large amount of money ¥50 to the product sales price P1, 9 is a P2+90 addition circuit that adds the highest change amount of ¥90 to the product sales price P2; 10 is a P2+5 addition circuit that adds the highest change amount of ¥50 to the product sales price P2
0 addition circuit, 11 is the total input amount X, Pl and P1+
Product sales price P1 comparing 50 and P1+90
comparator, 12 is the total input amount X, P2 and P
Product sales price P comparing 2+50 and P2+90
13 is a P1 price setting circuit for setting the product sales price P1, 14 is a B2 price setting circuit for setting the product sales price P2, 15 is the product sales price based on the output of the P1 comparator 11 16 is a bend control circuit for B2 that controls the sale of the product with the product selling price P2 based on the output of the B2 comparator 12; 17 is a coin payout control circuit; 18 is a coin payout control circuit; 19 is a refund latch circuit, 20 is an automatic refund circuit, 21 is a select latch circuit, 22 is a CREM control circuit, 23 is a two-phase lock pulse generation circuit, and 24 is a pit pulse generation circuit.

Also, A1 is a ¥10 change change signal, A2 is a ¥50 change change signal, B1 is a coin payout signal, B2 is a ¥50 coin payout signal, VENDl is a signal that the product of Pl can be sold, v
END2 is the sales enable signal for the product in B2, pos is the coin payout confirmation signal, PO is the manual refund input, S E Ll is the selection input for the product with the product sales price P1, 5EL2 is the selection input for the product with the product sales price P2, tl ~t7 is bit pulse, ESC/ACC and ESC-RTRN
indicates a ¥100 coin receipt signal and a refund signal in escrow.

Terminals 1 to 2 and the sales start signal T correspond to those in FIG.

In the example, the amount is 1''' in lO backward system is ¥1
It is expressed as a 6-bit pure binary number that represents 0.

The coin used here is ¥10¥50. If it is 100 yen, 10 yen is represented by the binary code '000001', 50 yen is represented by 000101', and 100 yen is represented by the binary code '001010'.

Therefore, the maximum selling price that can be set when using 6 bits is 630 yen, and this maximum selling price can be increased by increasing the number of bits.

The operation of the embodiment according to the present invention will be explained in detail based on the block diagram shown in FIG.

¥10. ¥50. Every time a coin of 100 yen is inserted, the inserted coin is converted by the encoder 1 into a binary code representing the amount as described above, applied to the adder/subtractor 2, and stored in the shift register 3 for total payout. The total amount of input is added to the total amount of input so far, and the total amount of input is stored in the shift register 3 for total payout.

The total payout shift register 3 is shifted by two-phase clock pulses.

At this time, the ¥100 coin is temporarily held in a space called escrow, and the ¥101¥50 coin is automatically stored in each change cylinder.

Also ¥50. Each time a coin of 100 yen is inserted, the input pulse is sent to the 50 yen coin number register 4 and the 100 yen coin number register 5, and the respective inserted numbers are stored.

If a coin is jammed when inserting a coin, the coin jam detection circuit 18 detects the coin jam;
Coin return electromagnet (Co i) that returns inserted coins as is.
nReturn El electromagnet
It has the function of sending the signal to the CREM control circuit (referred to as 0 or less CREM) and blocking the acceptance of coins.

In the conventional device, even if a coin is jammed, if the power is interrupted and then turned on again, it is possible to insert the first coin even in the coin jammed state, but in this embodiment If the coin jam condition persists even after the power is turned on again, coin acceptance is prevented immediately after the power is turned on again.

Here, a coin jam is a state in which coins are jammed and a coin input signal is continuously output.

The product sales price is expressed in a 6-bit pure binary binary code in which 1" in the decimal system represents ¥10.

In this embodiment, one electronic control circuit for a vending machine has two product selling prices P1. P1 price setting circuit 13 and B2 price setting circuit 14 for setting P2
By installing two or more electronic control circuits for vending machines, it is possible to sell products with two different prices using one electronic control circuit for vending machines. You can get vending machines.

In this case, the values of P, , P2 are Pl, B in the conventional device.
Some regulations state that either one of B2 must be larger, but in the example, Pl>B2
Any setting of p Pl =P2 t Pl <B2 is possible.

Among the 6-bit pure binary binary codes set in the P1 price setting circuit 13 and the B2 price setting circuit 14, the binary code of P1 is P1+501+50 addition P1+
The binary code of 901+90 addition and B2 is added to the P2+50 addition circuit 10 and the P2+90 addition circuit 9.

In addition to the P1+50 addition circuit 8 and the P2+50 addition circuit 10, the bit pulse generation circuit 24 generates a bit signal of t1+t3, that is, °'00 representing the amount of high-value money Y59.
0101” has been added, P1+50, P2+50
is added.

In addition to the P1+90 addition circuit 7 and the P2+90 addition circuit 9, the bit pulse of the bit pulse generation circuit 24, i1+t, that is, 'ooiooi' representing the maximum change amount of ¥90.
” is added, and P1+90 and P2+90 are added.

The bit pulse generation circuit 24 has a two-phase clock signal φ1.
．． It is composed of a shift register shifted by φ2, and generates bit pulses from tl to t7 in a clock pulse period, of which the bit pulses from tl to t6 are used to represent the amount of money.

The product sales price P1, P1+50, P1+90, the total input amount X stored in the shift register 3 for total payout is the product sales price P1 comparator 11
, product sales price P2. P2+50, P2+90, the total input amount X is the product selling price P2 comparator 1
2 respectively, and as a result of the comparison, the product selling price P1 is determined by the comparator 11, X=P1, X>Pl
, X>Pl +90, X=P, +50, from the product selling price P2 comparator 12, X=P2, X>P2,
An output of X>P2+90, X=P2+50 can be obtained.

The output from the comparator 11 for product selling price P1 is P1
The output from the product selling price P2 comparator 12 is applied to the P2 bend control circuit 16.

Pl. In addition, a ¥10 change change signal A1 and a ¥50 change signal A2 are added to the bend control circuits 15 and 16 for P2.

In the examples, Pl. P2 bend control circuit 15,1
6, the products P1 and P2 are determined to be available for sale, and the products P1 and P2 are determined to be available for sale.

VE'ND2 is issued under the following conditions.

I) If X= Pl or P2G, II)
P, <X≦P1+900r P2〈X≦P2+90 and if the minimum unit of money is ¥10 change, 1) X=,
If P1 + 50 or X = P2 + 50 and there is ¥50 change for a large amount of money.

The present invention is particularly characterized by the introduction of the condition ①.In the conventional device, even if there is change for ¥500 (high-value coin), if there is no change for ¥10 (the smallest unit of money), the change will be changed. Although we did not conduct sales that were necessary,
■) Introducing the condition of product selling price P1. P2 and ¥5
0 (high amount of money) and the value P1+50, P2+
By comparing 50 with the total input amount
Items that are available for sale are:

In other words, the smallest unit of money (¥10) is higher than the currency (¥5).
0) has change, the selling price is set to be the selling price that has the amount of change that can be paid out using this large amount of money.

When the customer selects either the product with the selling price P1 or P2, an operation input 5EL1 is sent to the select latch circuit 21;
Or 5EL2 is sent and select latch circuit 2
1, it is determined whether the product with the product sales price P1 or the product with the product sales price P2 is selected, and the sales start signal T from the outside is generated almost simultaneously with 5EL1 or 5EL2.
A signal ESC-AeC is sent to the escrow to collect the ¥100 coin temporarily held in the escrow.

Next, the output signal of the select latch circuit 21 is sent to the P1 price setting circuit 13 when 5EL1 is selected, and to the P2 price setting circuit 14 when 5EL2 is selected, depending on whether 5EL1 or 5EL2 is selected. Sent.

P1 price setting circuit 13 and P2 price setting circuit 14
When it receives the output signal of the select latch circuit 21, it sends a binary code representing the product selling price to the adder/subtractor 2.

In the adder/subtractor 2, the P1 price setting circuit 13 or the P2 price setting circuit 1 is calculated from the input total amount X stored in the total payout shift register 3 at this time.
The sales price sent from 4 is subtracted.

That is, subtraction of x-p or X-P2 is performed, and the subtraction result K is sent to the total payout shift register 3.
is stored as the change amount.

This stored content K indicates the amount of change.

That is, the total payout shift register 3 functions as a change register.

The contents stored in the total payout shift register 3 are sent to a comparator 6 to determine whether the change amount K is 150 or more.

K≧50 Comparator 6 receives ¥50 signal as t1+
The bit pulse of t3 is P1+50 addition circuit 8 and P2
It is added in the same way as the +50 adder circuit 10.

K≧50 The output signal of the comparator is sent to the coin payout control circuit 17.

The coin payout control circuit 17 also receives as inputs a signal A2 indicating no ¥50 change, the amount of change K stored in the shift register 3 for total payout, and an output representing the number of ¥50 coins inserted into the register 4. A signal and a coin payout confirmation signal PO8 are added.

Coin payout signal B in coin payout control circuit 17
1. The payout of change using the ¥50 coin payout signal B2 is performed as follows.

I) If K < ¥50...Pay out ¥10 x n pieces n<5) n) If K4 is ¥50 and there is ¥50 change...
Payout ¥50 x 1 piece, ¥10 x n pieces n<5)
I) If K≧¥50 and there is no ¥50 change...
Payout in ¥10Xn pieces (10>n>0) In the embodiment of the present invention, it is only possible to sell products for which the maximum change amount is ¥90 or less when a coin is inserted, so the change amount is always ¥ 90 or less.

This means that the output signal from the P1 comparator 11 and the P2 comparator 12 is X>P1+90. X>P2+
This can be done by controlling the VEND1 and VEND2 sales enable signals from the P1 bend control circuit 15 and the P2 bend control circuit 16 using the control circuit 90.

Each time a coin is paid out, the coin payout control circuit 17 receives a coin payout confirmation signal PO8 indicating the payout amount2.
The decimal code is sent to the adder 2, and the paid change is subtracted from the change amount K stored in the total payout shift register 3.

Then, when the amount of change stored in the total payout shift register 3 reaches 0'', the payout of change is stopped.

However, if the amount of change is 150 or more, ¥50 change will be paid out first and the remainder will be paid out according to the output signal of comparator 6.
I try to pay out at 10.

When performing a manual refund, if a manual refund manual PO is added to the refund latch circuit 19, the refund will be sold within a certain period of time.

If there is no optical start signal T, the amount will be refunded.

¥100 will be paid out from the escrow that was temporarily held,
Subtraction is performed from the total input amount X by the adder/subtractor 2 and the total payout shift register 3 until the contents of the ¥100 coin count register 5, which stores the number of ¥100 coins inserted, becomes 0''.

Similarly, the adder/subtractor 2 and the shift register 3 for total payout perform subtraction from the total input amount X until the number of input coins stored in the ¥50 coin count register 4 becomes 0''.

In this case, the output signals of the ¥50 number register 4 and the ¥100 number register 5 are converted into binary codes representing the respective amounts via the encoder 1 as shown in the block diagram of FIG. Subtraction is performed by unit 2.

¥50. After the ¥100 is refunded, the ¥10 is refunded until the remaining memory content of the total payout shift register 3 becomes 0''.

The refund ends when the memory content of the total payout shift register 3 reaches 0''.

In addition, if the total input amount X is larger than all sales set prices and all sale enable signals are not generated, the automatic refund control circuit 20 determines and automatically sends a signal to the refund latch circuit 19 to issue a full refund. Let them do it.

At this time, the refund latch circuit 19 sends out the ESC-RTRN signal, and the ¥50 sheet number register 4 and the ¥1
Sends a signal to the 00 sheet count register 5.

Further, if a coin is jammed, a sales start signal has been generated, or a refund has been made, the CREM control circuit 22 outputs a signal CREM to prevent the coin from being accepted.

The operation of the control circuit based on the block diagram of FIG. 1 as described above will be more clearly illustrated by the description of the embodiment of the block diagram of FIG. 1 shown in FIGS. 2 and 3.

FIGS. 2 and 3 are circuits showing an embodiment of the operation shown in the block diagram O shown in FIG.

The present invention will be explained in detail based on FIGS. 1, 2, and 3.

In FIGS. 2 and 3, the signals from ■ to ■ are signals within the electronic control circuit for a vending machine according to the present invention, and the other signals are from the electronic control circuit from devices of the vending machine other than this electronic control circuit. or sent from the electronic control circuit to other vending machine devices.

The circuit illustrating the embodiment of the encoder 1 in FIG.
In the figure, AND circuit 25~27.37°OR circuit 28
~31.38, NAND circuits 32 to 35, inverter circuits 36, 41, cycle timer 39, wired OR
It consists of circuit WO1.

Initially, the symbol [F] indicating that the electronic control circuit for a vending machine according to the present invention is in operation is "0", so AN
Since 'l' is added to D circuits 25 to 27 from the inverter circuit 41, coin input ¥10.¥50.¥10
If there is a 0, AND circuits 25 to 2 correspond to it.
7 produces an output 1'', and the output ``l'' is output from the OR circuit 28~
30 and the AND circuit 2 is added to the OR circuits 28 to 30.
The same output n 1 tl as the outputs 5 to 27 is produced.

In addition, the NAND circuit 32 has a bit pulse of tl, NAND
The D circuit 33 has a bit pulse of t2, and the NAND circuit 34
A bit pulse of t3 is applied to the NAND circuit 35, and a bit pulse of t4 is applied to the NAND circuit 35 from the shift register SR1.

The shift register SR, which is shown by the bit pulse generation circuit 24 in the block diagram of FIG. 1, is a two-phase dynamic shift register and receives two-phase clock pulses φ1. It is configured to be shifted by φ2 to generate bit pulses 11 to t7.

The outputs of the OR circuits 29-31 are applied to the NAND circuits 32-35 in addition to the bit pulses tl-t4.

By doing this, if there is a coin input of ¥10, this input will be converted to NA via the OR circuit 28.31.
Since it is applied to the ND circuit 32, the output of the NAND circuit 32 is synchronized with the bit pulse of tl, so it is expressed as 111110'' in a 6-bit binary number, and is inverted by the inverter circuit 36 via the wired OR circuit WO□. oo
By expressing '1' as ¥1O, a binary code representing ¥10 in pure binary system can be obtained.

In the same way, the coin input of ¥50 is NAND circuit 32,3
4, Rare, and 11.13 bit pulses, the output of the inverter circuit 36 appears as 000101'', that is, a binary code indicating ¥5,0.

Further, a coin input of 100 yen is applied to NAND circuits 33 and 35, and 001010'', that is, a binary code indicating 100 yen, appears at the output of the inverter circuit 36 in synchronization with the bit pulse of 12#14.

The output of the inverter circuit 36 is applied to an AND circuit 37, which also receives a signal from a cycle timer 39.

The outputs of the OR circuits 28 to 30 are output to the cycle timer 39.
It is applied via the R circuit 38.

In other words, the cycle timer 39 costs ¥10. ¥50. Output for a certain period of time when any coin of ¥100 is input.
1'' to the AND circuit 37.

The fixed time is generally one cycle time of bit pulses from t1 to t7.

Therefore, the output of the AND circuit 37 is only for one cycle time from tl to t7, that is, ¥10. ¥50. Since the pulse representing the coin input of 100 yen is output from the output terminal of the AND circuit 37 only once, double counting of coins does not occur.

The pulse representing the total input amount from the AND circuit 37 is sent to the adder/subtractor 2 as shown in the block diagram of FIG.
I will be sent to

The adder/subtractor 2 and total payout shift register 3 shown in the block diagram of FIG. 1 are made up of the parts shown in FIG. 2, including an OR circuit 44, an adder/subtractor ADD, a shift register SR2, and an OR circuit 46. .

The adder/subtracter ADD is a pure binary adder/subtracter that switches between addition and subtraction modes according to the output of the inverter 43 (the detailed internal circuit can be found in the Showa 4
Please refer to Figures 5 and 8, page 176 of "Calculator Technology Textbook - Basic Edition" published by Radio Gijutsusha, August 15, 2006.

), and for the output from shift register SR2,
This is a type of addition or subtraction of the binary code signals given through the OR circuit 44 and the result is stored in the shift register SR2, but this may also be of a type in which the complement is taken and subtraction is performed. , in any case, it is a well-known addition.

A subtractor can be used.

By doing this, in the adder/subtractor ADD, when there is a coin input, the inverter circuit 43
Since ON is added, the addition mode is set, and the pulse representing the input amount from the AND circuit 37 is sent to the adder/subtractor A.D.
D't is added and stored in shift register SR2.

Shift register SR2 is a two-phase dynamic shift register shifted by two-phase clock pulses.

The price setting circuits 13 and 14 for P1 and P2 in the block diagram 1 of FIG. 1 are PRICE1 in FIG.

Each terminal of PR engineering CE2 and NAND circuits 83-94.
98, 99, wired OR circuits WO2 to WO□2, and inverter circuits 96 and 97.

NAND among each terminal of PRICEl and PRICE2
The terminal connected to circuits 83 and 89 is NAND circuit 8
Since terminals 3 and 89 are connected so that the bit pulse of tl is applied, they have a weight of 1'', and the terminals connected to the NAND circuits 84 and 90 in the same manner are n2.
The terminals connected to the NAND circuits 85 and 91 have a weight of "4", and the terminals connected to the NAND circuits 85 and 91 have a weight of "4".
The terminal connected to 692 has a weight of 8'' and is connected to NAN
The terminals connected to the D circuits 87 and 93 have a weight of ``16'', and the terminals connected to the NAND circuits 88 and 94 have a weight of ``16''.
By applying a signal to any of the terminals of PRIC'E1, the outputs of NAND circuits 83 to 88 are connected to wired OR circuits W02 to WO6.
Since the inverter circuit 96 is connected to the inverter circuit 96 through the inverter circuit 96, the output of the inverter circuit 96 is an inversion of the outputs of the NAND circuits 83 to 88, and a 6-bit pure binary code representing the product selling price P1 is generated. Inverter circuit 96
can be obtained as the output of

Similarly, the product selling price P2 can also be set by applying a signal to any of the terminals of PRICE2.

Of the product selling price P1゜P2 obtained in this way, Pl is P1+50 as shown in the block diagram of Fig. 1.
Addition circuit 7, P1+90 addition circuit 8, and P2
The signals are sent to a +50 adder circuit 9 and a P2+90 adder circuit 10, respectively.

In FIG. 2, the portion consisting of the full adder FA1, the AND circuit 49, and the flip-flop circuit FF1 is the P1+90 adder circuit 7; The portion consisting of the AND circuit 50 and the flip-flop circuit FF2 is the P2+90 addition circuit 9, and the portion consisting of the full adder FA3, the AND circuit 51, and the flip-flop circuit FF3 is the P1+50 addition circuit 8, the full adder FA4, and the AND circuit. 52, a flip-flop circuit FF, and a P2+50 addition circuit 10.

Full adders FA1 and FA2 include a two-phase shift register S.
Of the bit pulses t1 to t7 generated by R1, t
The bit pulses of l and 14 are connected to be applied as the output of the OR circuit 81, so that the full adders FA1 and FA2 receive the binary number "00" representing the maximum change amount of ¥90.
1001'' is added, and an output of P1+90 or P2+90 can be obtained from the full adders FA and FA2.

In addition, the full adders FA3 and FA4 similarly receive a binary number "000101" representing the denomination amount of ¥50 as the output of the OR circuit 80 based on the bit pulses of tl and 13.
” and its output is P1+50 and P2+5
You can get 0.

The comparator 11 for P1 in the block diagram of FIG. 1 is the comparator COMP2 to COMP, t in FIG.
The comparator 12 for P2 is the comparator COMP6~
This is a part consisting of COMP9.

Comparator COMP2 shows 6 representing the total input amount X.
The 6-bit binary code and the output of the inverter circuit 96, that is, the product selling price P1, are expressed in pure binary notation.
A decimal code is applied, and as a result of the comparison, a signal ■ where x>pl is obtained.

A 6-bit binary code representing the total input amount X in pure binary notation and a 6-bit binary code representing P1+90 in pure binary notation from the aforementioned full adder FA1 are applied to comparator COMP3. As a result of the comparison, a signal (2) with X>P1+90 is obtained.

The same input as comparator COMP2 is applied to comparator COMP4, and the comparison result is X=P
1 signal ■ is obtained.

Comparator COMP. A 6-bit binary code representing the total input amount X in pure binary notation and a 6-bit binary code representing P1+50 in pure binary notation from the aforementioned full adder FA3 are applied to . , a signal [F] of X=P1+50 is obtained as a result of the comparison.

For the product sales price P2, the comparator COM
Signal ■ of X>P2 from P6, signal ■ of X>P2+90 from comparator COMP7, signal ■ of X>P2+90 from comparator COMP8
A signal (2) with X=P2 is obtained from the comparator COMP, and a signal (2) with X=P2+50 is obtained from the comparator COMP.

Output signals of comparators COMP2 to COMP shown in FIG. 2: ■X>Pl, ■X>P1+90, ■X=P1
, [F]X=P1+50, ■X>P2, ■X>P
2+90, ■X=P2, ■X=P2+50 are NAND circuits 100, 101, AND circuits 102, 106°108, OR circuits 105, 107,
P1 bend control circuit consisting of inverter circuits 109, 110, NOR circuit 118, flip-flop circuit and FF1□, or NAND circuits 111, 112, AND
Circuits 113, 116, 119, OR circuits 114, 117
, inverter circuits 115, 110, NOR circuit 118,
It is added to the P2 bend control circuit consisting of flip-flop circuit FF13.

Considering a product with a product sales price of P1, X=P1
At this time, the signal (2) with X=P1 is applied to the OR circuit 105, and the output of the OR circuit 105 becomes one input of the AND circuit 106.

The other input of the AND circuit 106 has the output of the OR circuit 82, that is, the signal ■ P −o, so when the product selling price P1 is not O, '1'' is added, so the signal ■ of X=P1 is applied. If it is, the OR circuit 107
One input terminal "1" of the two input terminals of the AND circuit 108 is added as the output of the AND circuit 108.

The other input terminal of the AND circuit 108 is the NOR circuit 118
is connected to the output terminal of

The two input terminals of the NOR circuit 118 are wired AN
Signals are sent from D circuit WA3 and flip-flop circuit FF1.

The flip-flop circuit FF1□ is used when the customer selects a product using a push button, etc., as described later.
Since it is in a reset state until EL2 and the SEL signal e indicating that the product has been sold, or the refund signal ■, which occurs a little later than that, the flip-flop circuits FF1. The input from is 0″.

The wired AND circuit WA3 has as inputs the output of the flip-flop circuit FF15 inverted by the inverter circuit 149, the output of the flip-flop circuit FF, 8 inverted by the inverter circuit 147, and the NAND circuit 1.
56 outputs are added.

When there is no manual refund manual PO, flip-flop circuit FF1. is not set, so the inverter circuit 14
The output of the inverter circuit 147 is "1", and since the flip-flop circuit FF18 is not set when there is no sales start signal T, the output of the inverter circuit 147 is "1".

The NAND circuit 156 has flip-flop circuits FF1. The output of 5ING and the signal 5ING are added.

5ING has two price setting circuits in the embodiment, so if only one price setting circuit is used, the price setting number selection signal 5ING is "0" when two price setting circuits are used. Add "l" etc.

5 Regardless of the state of the ING signal Iζ, the sales start signal TO
When not present, the output of the NAND circuit 156 is 1 t+.

Therefore, when there is no sales start signal T or manual refund manual PO, the output of the wide 'Unzed AND circuit WA3 is 1'', and this output is inverted by the inverter circuit 160 to indicate NO.
“0” is added as an input to the R circuit 118.

Therefore, if there is no sales start signal T or manual refund PO, the output of the NOR circuit 118 is H1? +, and when the output of the OR circuit 107 becomes 1'', the 79717171 circuit FF1□ is set to generate a sellable signal VEND1 indicating that the product with the selling price P1 can be selected.
To enable a customer to select a product with a selling price P1.

The product with the product sales price P2 is exactly the same as the product with the product sales price P1, and the OR circuit 95
=O, and a sales ready signal vEND2 can be obtained from the flip-flop circuit FF13.

Based on this sellable signal VEND1 or ■END2, a display is displayed on the vending machine indicating that the customer can select the product with the product sales price P1 or P2, and when the customer selects either of the products, a signal of 5EL1 or 5EL2 is displayed. is sent along with the sales start signal T to the electronic control circuit device for vending machines according to the present invention.

That is, the sales start signal T is a signal that the product has been sold.

In addition, if a coin is inserted that causes the signal ■ of X>Pl, the signal ■ of X>Pl will be generated by the AND circuit 10.
2 and as the other input of the AND circuit 102
The signal ■ of 90 is inverted by the NOT circuit 109, the ¥50 no change signal A2 of large amount of money is inverted by the NOT circuit 110, and the signal ■ of X=P1+50 are added to the NAND circuit 100. The output is the minimum unit of money, ¥10, and the no change signal A1 is sent to the NAND circuit 10.
1 and the output of the NAND circuit 101 obtained, X>P,' and.

If X≦P1+90 and there is change in the minimum unit of ¥10, an output f'1 jl is generated in the AND circuit 102,
By applying the output to the OR circuit 105, the sales enable signal of VENDl is obtained in the same manner as in the case of X=P1 described above.

Also, when X = P1 + 50, if there is no change for the smallest unit of ¥10, but there is change for the highest amount of ¥50, then
Since °°1" and n11+ are added to the NAND circuit 100, its output is 0", and its output? +071
NAND circuit 1 with 1'' indicating ¥10 no change
01, so the output of the NAND circuit 101 is "
1”, and X=P1+50 is X>Pl and X≦P1
+90, the inputs of the AND circuit 102 are all 1'', and therefore the sales enable signal of VENDl can be obtained in the same way as when X>Pl described above.

Regarding the product sales price P2, X>P2, X−P2+5
In the case of 0, the output of the sellable signal vEND2 can be obtained by thinking in exactly the same way as in the case of the product selling price P1.

When the sales start signal T is generated, the following occurs in this embodiment O device.

The sales start signal T is applied as an input to an OR circuit 154, and the output of the OR circuit 154 is applied to an AND circuit 155.

The AND circuit 155 also has the output of a NOR circuit 159 which receives the outputs of the flip-flop circuits FF16 and FF1□ as inputs.

The output of the flip-flop circuit FF16 is NON when the sales start signal T is generated, and the output of the flip-flop circuit FF, □ is NOR because the output of the flip-flop circuit FF18 remains nO#+. The output of circuit 159 is '1'', therefore OR circuit 15
4, the flip-flop circuit FF1□ is set.

This output is delayed by 100 ms by delay circuit Delay4 and is applied to AND circuit 158 as the output of OR circuit 157.

Since "1" is added to the AND circuit 158 from the aforementioned NOR circuit 159 as another input, the OR circuit 157
The flip-flop circuit FF18 is set by the generation of I n as the output of .

Receipt signal ESC- of the ¥100 coin held in the escrow by the output of the flip-flop circuit FF18
Generates an Ace.

Also, the output "1" of the flip-flop circuit FF18 is AN
to the D circuit 131 together with the signal of 5EL1, or
It is applied to the D circuit 132 together with the signal of 5EL2.

Since the signals 5EL1 and 5EL2 are generated almost simultaneously with the sales start signal T, the flip-flop circuit FF
When the output "'1" of 18 is generated, either 5EL1 or 5EL2 has already been applied to the AND circuit 131 or 132.

Therefore, at the same time that the output "1" of the flip-flop circuit FF18 is generated, the output II from the AND circuit 131 or 132 is generated.
In occurs, the output of the AND circuit 131 is directly connected to one of the two input terminals of the AND circuit 141, and the other terminal is connected to the inverter circuit 161 and the wired OR circuit WO.
14-WO15 is applied via the inverter circuit 143 and the cycle timer 163.

By applying it to the AND circuit 141 via the cycle timer 163, the output of the AND circuit 141 becomes the bit pulse t.
It will occur only once every 1 to 17 intervals.

Similarly, the output of the AND circuit 132 is output from the AND circuit 142.
The NOT circuit 162, the wired OR circuit WO13, and the NO circuit are directly connected to one of the two input terminals of the
Since the bit pulses are applied via the T circuit 143 and the cycle timer 163, the output of the AND circuit 142 is the bit pulse t1 to t.
Occurs only once every 7.

Assuming that the output of the AND circuit 141 is the 5EL1 signal ■, and the output of the AND circuit 142 is the 5EL2 signal ■, the 5EL1 signal ■ is applied to the NAND circuit 98 in FIG.

The NAND circuit 98 also has a binary code representing the product selling price P1 from the inverter circuit 96 as an input, so by adding the 5EL1 signal ■, the binary code representing the product selling price P1 is converted to a wired OR circuit. It is applied to the adder/subtractor ADD via WO□2, the inverter circuit 79, and the OR circuit 44.

That is, since the 5EL1 signal (2) is generated only once in the interval from t1 to t7, the output of the OR circuit 44 is a binary code representing the product selling price P1.

The adder/subtracter ADD has an inverter circuit 43 as another input.
When there is no coin input signal ■, l'' is added, so the subtraction mode is entered, and the adder/subtractor ADD subtracts the product selling price P1 from the total input amount X.
The change amount K is stored in the shift register SR2.

The same is true for the product sales price P2, and 5E
The L2 signal ■ is applied to the NAND circuit 99, and the rest is carried out in the same way as for the product selling price P1.

These change amounts are calculated using the cycle timer 16 in FIG.
When the output of 3'' disappears, the output power of the inverter 140 becomes 1''.

Since the AND circuit 133 is supplied with the output of the inverter 140, the SEL signal θ which is already 1 jl, and the signal ■ which becomes 1'' when the contents of the shift register SR2 are not 0, the cycle timer 163 When the output disappears, the contents of shift register SR2 (i.e. change amount) become 0.
If not, the AND circuit 133 outputs an output, and the OR circuit 133 outputs an output.
A coin payout signal B1 is issued via the circuit 134 to start the change payout operation.

Next, the operation of paying out change will be explained.

The stored contents of the shift register SR2 representing the change amount K obtained by subtracting the product selling price P1 or P2 from the total input amount X are sent to the comparator COMP1 where ≧50 comparator 6 is shown in FIG. 1 and compared with ¥50. .

The output of the comparator COMP1 is applied to an AND circuit 77, which also has a ¥50 no change signal A2 as another input, which is the SEL signal signal output signal of the inverter circuit FF18.

Therefore, if there is a change coin of 50 yen and a product with a change amount of 150 yen or more is sold, the output of the AND circuit 77 will be 1.
'' occurs, and the ¥50 change payout signal B2 is generated as the output of the OR circuit 76, and this and the above-mentioned coin payout signal B1 are generated.
A change of ¥50 is paid out using the .

The output of the OR circuit 76 is added to the AND circuit 74,
The D circuit 74 receives a change payout confirmation signal PO as another input.
8 is added, and when ¥50 change is paid out, an output "1" is generated in the AND circuit 74, and this output is ORed.
It is added to circuit 29 and ¥ is added in the same way as when inserting a coin.
It is converted into a binary code representing 50 and added to the adder/subtracter ADD, but at this time, the output of the inverter circuit 43, which is the other input of the adder/subtracter ADD, is input to the AND circuits 25 to 2.
Since the output of 7 is 0'', it is ``1'', and therefore the adder/subtractor ADD is in the subtraction mode, so that 50 yen is subtracted from the change amount.

When the change amount K becomes less than 50 yen, the output of the AND circuit 77 becomes 0'', so that ``1'' is added to the AND circuit 73 via the OR circuit 76 and the inverter circuit 75.

The same change payout confirmation signal PO8 as the AND circuit 74 is added to the AND circuit 73;
Like the D circuit 74, every time change is dispensed, the output signal "1 u" is sent to the OR circuit 28 to subtract 10 yen from the change amount K.

To pay out change of ¥10, if the change amount K stored in shift register SR2 still remains after subtracting change of ¥50, OR circuit 46 sends change to shift register S.
Since the signal (2) indicating that the memory contents remain in R2 continues to be generated, the AND circuit 133 and the OR circuit 134 continue to output the coin payout signal B19.
This is done based on this and the condition that the ¥50 coin payout signal B2 has disappeared.

These are known techniques, and generally the signal B1 is applied to the change dispensing motor, and the signal B2 is applied to the ¥50.00 change dispensing motor. ¥10 is given to the switching solenoid.

Because paying out ¥50 change has priority over paying out ¥10 change,
It becomes possible to pay out the minimum number of change.

Next, consider the case of refund.

First, we will discuss the case of manual refund.

The coin input signal ■ generated from the OR circuit 40 is the OR circuit 1
20 and the output of the OR circuit 120 is added to the AND circuit 12.
Added to 1.

The output of the NOR circuit 122 is added to the AND circuit 121 as an input.

Since the sales start signal T and the SEL signal e are added to the NOR circuit 122 and the output of the inverter circuit 150 obtained through the NOR circuit 148 and the inverter circuit 150, when the sales start signal T is not present, the NOR circuit 122 Since the output of FF1. is set.

The output of flip-flop circuit FF14 is manual refund P.
It is added to the AND circuit 123 along with O.

Therefore, when manual refund manual PO occurs, AND circuit 12
3, an output f+ 191 is generated and applied to the AND circuit 125 via the NOR circuit 124.

Since the AND circuit 125 has, as another input, the input of a NOR circuit 126 to which the same input as the aforementioned NOR circuit 122 is added, the output II 1 ? of the OR circuit 124?
+, the output of the AND circuit 125 becomes 1″
As a result, flip-flop circuit FF15 is set.

Flip-flop circuit FF1. The output of is the delay circuit Del
AND circuit 146 via ay2 pOR circuit 145
added to.

Since the output of the above-mentioned NOR circuit 148 is added to the AND circuit 146 as an input, when the SEL signal e is not generated, "1" is generated, so the AND circuit 1
An output "l91" is produced at 46, and the flip-flop circuit F
R16 is set and the refund signal ■ can be obtained.

By doing this, if the sales start signal T is generated before the manual refund PO is applied, the flip-flop circuit FF1. ■ is a refund signal because it is reset.

In addition, even after the manual refund PO is applied, if the sales start signal T or SEL signal e is generated during the delay time of the delay circuit Delay2, the flip-flop circuit F
Reset F15 and send sales start signal T, SEL signal e
Prioritize.

In addition, an automatic refund signal ATPO, which will be described later, is added to the terminal of the manual refund manual PO.

Automatic refunds will be made in the following cases:

That is, the output of the aforementioned flip-flop circuit F:F12 is passed through the inverter circuit 127 to the T-wired AND circuit WA.
1, the output of the aforementioned flip-flop circuit FF13 is added to the wired AND circuit WA1 via the inverter circuit 128, and the output of the wired AND circuit WA1 is connected to the wired AND circuit WA1.
It is added to the ND circuit 129.

Also, the signal ■ of X>Pl and the signal ■ of x=p1 are added to the OR circuit 103, the signal ■ of X>R2 and the signal ■ of X=P2 are added to the OR circuit 104, and the OR circuit 103 and the OR circuit 1
04 output to the wired AND circuit WA2,
The output of wired AND circuit WA2 is connected to AND circuit 129.
Add to.

By doing this, wired AND circuit WA2
If you input an amount that is greater than or equal to all sales prices, an output of "1" will occur, and the wired AND circuit W
The output of A1 is a flip-flop circuit FF12. FF1
"1"' is generated when the output of 3 is not generated, and
Circuit 129 provides an automatic refund signal ATPO.

That is, in this embodiment, even if coins are inserted to the maximum limit, if neither of the sellable signals VEND1 and VEND2 occurs, the money is automatically refunded.

This automatic refund signal ATPO is added to the manual refund manual PO described above, and the refund signal (2) can be obtained in the same manner.

Refunds are made in the following manner based on the refund signal (2) obtained in this manner.

In the embodiment, as shown in the block diagram of FIG.
0. For the insertion of 100 yen coins, a 50 yen coin count register 4 and a 100 yen coin count register 5 are provided to count the number of coins inserted.

In other words, in Figure 2, the ¥50 number register is R1, ¥
The 100 sheet count register is indicated by R2.

Registers R1 and R2 sequentially set the flip-flop circuit each time an input is applied.
Register R2 can count up to 15 ¥50 coins (up to 750 yen), and register R2 can count up to 8 coins (800 yen).

The ¥50 sheet number register R1 receives ¥5 from the AND circuit 26.
0 coin input trace has been sent, and in addition, ¥50 coin input trace has been sent along with the output of cycle timer 39.
The output of the AND circuit 53 is applied to the OR circuit 54.

Cycle timer 3 every time there is a coin input signal of ¥50
The number of ¥50 coins inserted is stored in the ¥50 coin count register R1 based on the output pulse signal of the OR circuit 54, which applies a signal to the AND circuit 53 only during the nine bit pulse periods from t1 to t7.

Similarly, the ¥100 coin input signal from the AND circuit 27 is added to the ¥100 coin number register R2.

Furthermore, is the ¥100 coin input signal a cycle tie? '3
9 is applied to the AND circuit 64, and the output of the AND circuit 64 is applied to the OR circuit 67, so the OR
The ¥100 coin input signal becomes ¥1 due to the output pulse of the circuit.
00 sheets number register R2.

At the same time as the refund signal ■ is generated, a refund signal ESC/RTRN for the ¥100 coin held in the escrow is issued, and the ¥100 coin held in the escrow is refunded.

¥50 The number register R1 includes an OR circuit 58, an AND circuit 59, an inverter circuit 60, and a flip-flop circuit FF.
A circuit consisting of 6 is attached.When the ¥50 coin input is added to the ¥50 coin count register, the flip-flop circuit FF6 is set at the same time, and when the memory content of the ¥50 coin count register becomes 0'', the flip-flop circuit FF6 is set. circuit FF
6 is reset, so that the stored contents of the 150 sheet number register R1 can be judged from the output of the flip-flop circuit FF6.

Similarly, the OR circuit 69 and A are connected to the ¥100 number register R2.
A circuit consisting of an ND circuit 70, an inverter circuit 72, and a flip-flop circuit FF7 is attached, and the contents of the ¥100 number register can be determined based on the output of the flip-flop circuit FF7.

When the refund signal ■ is generated, the refund signal ■ is applied to the AND circuit 66, and by adding the clock pulse φ3 as another input to the AND circuit 66, the AND circuit 66 can obtain an output synchronized with the clock pulse φ3.

Since the output of the AND circuit 66 and the output of the OR circuit 71 whose inputs are the ¥1.00 number register R2 and the flip-flop circuit FF7 are added to the AND circuit 65, when the output of the flip-flop circuit FF7 is "1", In other words, while the number of ¥100 coins inserted is stored in the ¥100 register R2, the output "171" is output to the AND circuit 65.
A pulse is given to the 100 sheet number register R2 as the output of the OR circuit 67, and the memory in the ¥100 sheet number register R2 is sequentially moved toward the output end.

When a signal is output from the output end of the ¥100 sheet count register R2, that signal is added to the AND circuit 68 along with the output of the AND circuit 65, and a signal is output from the output end of the ¥100 sheet count register R2, and the number of ¥100 sheets is stored. Every time the subtraction is performed, the output ""1 jl generated from the AND circuit 68 is added to the OR circuit 30 and the above-mentioned ¥50. In the same way as when paying out change of 100 yen, 100 yen is subtracted from the total input amount X stored in the shift register SR2.

In this way, by sequentially subtracting the number of sheets stored in the ¥100 sheet number register R2, the stored contents of the \100 sheet number register R2 are emptied.

Since the memory contents of the ¥100 number register R2 become empty, the output of the OR circuit 71 becomes 0'', and the NOR circuit 61
0" is added to one input of the inverter circuit 56, and "1" is added to the AND circuit 63 as the output of the inverter circuit 56.

The AND circuit 63 also receives as inputs a signal from the output end of the ¥50 number register, a refund signal (2), and a signal (2) from the OR circuit 46.

If ¥50 is inserted, the flip-flop circuit FF6 is set, so the output of the NOR circuit 61,
Therefore, the output ◎ of the AND circuit 62 does not occur immediately, but the stored contents of the 150 sheet number register R1 and the 100 sheet number register R2 are simultaneously moved toward the output terminal via the AND circuit 57 and the OR circuit 54. Therefore, the 150-sheet count register R1 produces an output after a short period of time, depending on the stored contents.

This output, on the one hand, resets the flip-flop FF6 via the inverter 60 to prevent further movement of the memory contents via the AND circuit 57, and also
The R circuit 61 produces an output, and the Q signal is generated only through the AND circuit 62.

The output of the 150 sheets number register R1 is given to the AND circuit 63 on the other hand, and as a result, the output N1 to the AND circuit 63 is given to the AND circuit 63.
u is generated, its output is added to the OR circuit 76, and the ¥50 payout signal B is generated as in the case of paying out ¥50 change previously.
2 and the output ◎ of the above-mentioned AND circuit 62 are ORed together in Fig. 3.
The coin payout signal B1 obtained through the circuit 134 pays out a coin of ¥50, and the change payout confirmation signal PO8 causes the total payout shift register S to be paid out.
Subtract ¥50 from the memory contents of R2.

The change payout confirmation signal PO8 is applied to the AND circuit 55, and the AND circuit 55 also receives as input the signal from the output terminal of the 150-piece number register R1 and the output of the inverter circuit 56, and the signal from the ¥100-piece number register R2. If the memory content is empty and there is memory content in the 150 coins register R1, an output of "1" is generated in the AND circuit 55 by receiving the change payout confirmation signal PO8, and this output is O.
It is sent to the 150 sheet count register R1 via the R circuit 54,
150 The stored contents of the number register R1 are moved by one toward the output end.

This process is repeated until the contents of the 150-sheet count register R1 become empty.

When the stored contents of the 150-coin number register R1 become empty, the output "1" of the AND circuit 63 disappears, and the payout of 50 coins ends.

When the stored contents of the ¥50 sheet count register and the ¥100 sheet count register become empty, if the stored contents remain in the shift register SR2 and the OR circuit 46 generates the output ■, the AND circuit 62 still generates the output ◎. O
The coin payout signal B1 continues to be output via the R circuit 134, and based on this and the disappearance of the ¥50 coin payout signal B2, the ¥50 coin payout signal B1 is issued in the same way as when paying out change.
Make O coins payout.

Then, in the same way as the change payout at T10 described above, the change payout confirmation signal PO8 is used to subtract from the total payout shift register SR2 until the output of the OR circuit 46 becomes 0'', that is, the shift register SR
The coins of T10 are paid out until the memory contents of No. 2 become empty.

In this way, by providing the ¥50 number register R1 and the ¥100 number register R2, in the case of refund, the same amount,
You can get a refund for the founder matching coins.

In the embodiment, in order to deal with coin jams,
When there is a coin input signal ■, by applying that signal to the two input terminals of the AND circuit 1510, one directly and the other through the delay circuit Delay3, if the coin input signal ■ is still occurring even after the delay time has passed. is AND circuit 1
51 produces an output "1", and by applying this output to the OR circuit 153, the output "1" of the OR circuit 153 can prevent subsequent coin insertion.

However, the delay time of the delay circuit Delay3 is sufficiently long compared to the coin input signal time, and here it is 300 m.
A value of 5ec is used.

According to this method, it is possible to prevent coin insertion after a delay time in the case of a coin jam in which a coin input signal is generated even when the power is interrupted and then turned on again.

In the embodiment, the CREM off state (coin acceptance inhibited state) may occur in the following other cases.

That is, the output "1" is output to the wired AND circuit WA2 mentioned above.
If this occurs.

In other words, when the total amount of coins inserted exceeds the selling price of all the products, there is no need to insert any more coins, so the system prevents further coins from being accepted.

Further, when the sales start signal T is sent, the manual refund manual PO, and the automatic refund signal ATPO are sent, coin acceptance is blocked.

This means that the output of the wired AND circuit WA2, the sales start signal T1, the flip-flop circuit FF1. This can be implemented by adding the outputs of FF and □ to the OR circuit 152 and adding the outputs of the obtained OR circuits as inputs to the OR circuit 1530, so that the CREM control is performed by the output of the OR circuit 153. .

When operations such as selling, dispensing change, and refunding are completed, an operation (hereinafter referred to as "clearing") for transitioning the electronic control circuit for the vending machine to a state in preparation for the next sale is performed as follows. .

That is, the coin payout signal B1 is applied to the NAND circuit 137 via the inverter circuit 136.

The NAND circuit 137 also receives the refund signal ■ and SE as inputs.
It consists of three people: the L signal e is applied to the OR circuit 135, and the output of the OR circuit obtained is applied directly and via the delay circuit Delay 1.

Therefore, if there is no coin payout signal B1 and a refund signal ■ or SEL signal e occurs, the delay circuit Delay1
After a delay time of , the output of the NAND circuit 137 becomes "0".

The delay time of the delay circuit Delay1 is sufficiently long compared to other operating times of the embodiment device, and a value of 2 seconds is used here.

The output of the NAND circuit 137 is wired OR circuit WO1
Added to 3.

The wired OR circuit WO03 is supplied with a signal "Mateclina signal" which is not cleared from the outside and the output of the NAND circuit 130 as inputs.

The clear signal is internally used when attempting to obtain the automatic clear signal ACL, and is normally n 1 ty.

The NAND circuit 130 has a wired OR with the SEL signal e.
The outputs of circuits WO□4 and WO15 are added,
Since the wired-OR circuit changes the output power to 0'' when any input force becomes 0'', EXT
, either the NAND circuit 130 or 137 outputs
'0'', the change in the output of the wired OR circuit WO13 is applied to the inverter circuit 138, and the output of the inverter circuit 138 causes the flip-flop circuit FF to change.
The output of 1□ is inverted and the flip-flop circuit FF1□
When the output of 1'' is 1'', an automatic clear signal ACL(i) is obtained as an output to the inverter circuit 139.

ACL signal ■ is comparator COMP-COMP9
is added to reset the comparators COMP1 to COMP.

In this way, the operation of the electronic control circuit for vending machines shown in the block diagram in FIG. 1 can be achieved as shown in FIGS. 2 and 3; By further increasing the number of price setting circuits and matching other circuits, it is possible to sell products with two or more different prices using one electronic control circuit for automatic sales customers.

The above operations of the present invention are not limited to coins, for example,
Of course, the present invention can also be applied to those using 000 yen and 500 yen banknotes and 100 yen coins.

〔Effect of the invention〕

According to the present invention as described above, when a coin with a higher value than the minimum unit of money has change, the selling price is set such that the amount of change can be paid out using the higher value coin. Therefore, change in large denominations can be used effectively and sales opportunities can be increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention. FIG. 3 shows a circuit diagram of the embodiment of FIG. 1...Encoder, 2...Adder/subtractor,
3...Shift register for total payout, 4...¥50 number register, 5...
¥100 number register, 6...K≧50''1 amparator, 7...Pl +90 adder, 8...
...P1+50 adder, 9...P2+90
Adder, 10...P2+50 adder, 11...
...Comparator for P1, 12...Comparator for P2, 13...Price setting circuit for P1,
14... Price setting circuit for P2, 15...
・Bend control circuit for P1, 16...Bend control circuit for P2, 17...Coin payout control circuit,
18... Coin jam detection circuit, 19...
... Refund lunch circuit, 20 ... Automatic refund circuit, 21 ... Select latch circuit, 22 ...
...CREM control circuit, 23...Two-phase lock pulse generation circuit, 24...Bit pulse generation circuit, 25~27.37.49~53,55,57゜59
．． 62～66.68,70,73,74゜77.102
,106,108,113,116°119.121,
123,125,129°131-133,141,1
42,146゜151.155,158...A
ND circuit, 28-31.38, 40, 44, 46, 54
,58°67.69,71,76.80~82,95°103~105,107,114,117°120.1
24,134,135,145°152~154,15
7...OR circuit, 32-35.83-94.9
8～101,111゜112.130,137,156
・・・・・・NANDAND circuit, 61, 118, 12
2,126°148.159...NOR circuit,
36,41°43.56,60,72,75,78,7
9゜96.97,109,110,115,127゜1
28.136,138~140,143°147.14
9,150,160-162... Inverter circuit, 39,163... Cycle timer, Del
ayl~Delay4=delay circuit, FF1~FF4.
FF1□~FF18...Flip-flop circuit, COMP1~COMP,...Comparator,
WOl ~ WO1, ... wired OR circuit,
WA1~WA3...Wired OR circuit, SR
1. SR2...2-phase dynamic shift register,
R1, R2...Register, FA1~FA,...
...Full adder, PRICEl, 2...Product sales price setting terminal, PO8...Coin payout confirmation signal, AT PO...Automatic refund signal, PO
...Manual refund input, A1...¥10 no change signal, A2...¥50 no change signal, B
１・・・・・・Coin payout signal, B2・・・・・・￥
50 coin payout signal, T...Sale start signal,
vENDl, 2...Sellable signal, ESC・
RTRN...Coin refund signal in escrow, E
SC/ACC・・・Escrow coin collection signal,
EXT. CL...External clear signal, 5ING...
・Price setting number selection signal, ■... Coin input signal, ■... Refund signal, ■... Shift register SR2 memory content existence number, ■...・X>P1
Signal, ■...x>p1190 signal, ■...
...-X=P1 signal, ■...Auto clear signal A
CL, ■...X>P2 signal, ■...X
〉P2+90 signal, ■...X=P2 signal, ■・
...P1=0 signal, ■...P2=O signal, θ...Select signal SEL, ■...
Select signal 5EL1. ■・・・Select signal 5EL2, ■・・・・・・
Electronic control circuit operation signal for vending machines, ■・・・・・・￥
10 coin payout signal, [F]...X=P1
+50 signal, ■...X=P2+50 signal, 5E
L1.5EL2...Select input signal, CRE
M...Coin acceptance prevention signal, tl to t7...
...Bit pulse, φ1. φ2. φ3・・・・・・
clock pulse.

Claims (1)

[Claims] 1. means for calculating and storing the total amount of input money; price setting means for setting the selling price of the product to be sold; means for detecting the presence or absence of change in change coins of multiple denominations;
The total input amount is compared with the sales price, and if there is change in a higher amount of money than the minimum unit of money based on the detection output of the change presence/absence detection means, change is paid out using the higher amount of money. 1. A vending machine vending machine sales permissibility determination device, characterized in that the vending machine is vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending machine vending that vending machine vending machine vending machine vending machine vending machine vending that vending machine vending machine vending machine vending machine vending machine vending that vending machine vending machine vending machine vending machine vending machine vending that vending machine vending that vending machine vending that sours that it doesn't.