JPS5911158B2 - Control circuit for vending machines - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is an automatic vending machine in which a mechanism for calculating the input amount, change, etc., accepting money, returning money, or sending out a sales signal is configured with an electronic circuit. Related to electronic control circuits for vending machines.

With the diversification of products and sales prices sold in vending machines, it is desired to be able to set multiple prices with one vending machine, but it is possible to set the maximum number of sales prices that can be imagined. If the control circuit for standardization is manufactured as a standard product using LSI or the like, it will end up having excessive functions for a model with a single product price, which will lead to an increase in the product price on average.

Therefore, a control circuit unit that enables the setting of a number of sales prices smaller than the maximum number of sales prices that can be assumed is manufactured as a standard product using LSI etc., and this control circuit unit is manufactured in multiple numbers according to the number of desired set prices. The idea is to combine them.

This type of control circuit unit sends a sellable signal (bend signal) to an output terminal corresponding to the set price when the input amount exceeds any set price set in the unit.

When a product with the set price is selected by a push button on the vending machine main unit side, a selection signal is sent to the corresponding control circuit unit and a sales signal indicating that the vending machine main unit has entered the product selling operation. Signals are sent to all control circuit units.

In this case, the selected control circuit unit must be kept in an operating state to perform change calculation and payout control, but the unselected control circuit units must be reset in some way to stop them from sending the sellable signal. It needs to be stopped.

Some conventional devices have provided one of these control circuit units with the function of resetting non-selected control circuit units, but it is not possible to provide a specific function to a specific unit in this way. , which is contrary to unit standardization.

Therefore, an object of the present invention is to provide each control circuit unit itself with an automatic reset function when the unit is not selected, and to enable each control circuit unit to function independently of each other. be.

According to the present invention, the above object is to provide a control circuit for a vending machine that is equipped with a plurality of control circuit units that can individually set a plurality of prices.
For a control circuit unit in which a product selection signal does not arrive even though the signal has arrived, this can be achieved by providing means within the unit to generate an automatic clear signal only for the unit.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram illustrating the operation of a control circuit unit according to the invention.

In the figure, 1 is the encoder, 2 is the adder/subtractor, 3 is the shift register for total payout, 4 is the Y50 number register, 5 is the ¥100 number register, 6 is the change amount K and Y5
K≧50 comparator that compares with 0, 7 is a P1+90 addition circuit that adds Y90 to the product setting price P1, 8 is a P1+50 addition circuit that adds Y50 to the product setting price P1, 9
is a P2+90 addition circuit that adds product setting price P2t (T90, 10 is P2+ that adds Y50 to product setting price P2
50 addition circuit, 11 is input amount, P1 and P, +50
12 is a comparator for the product setting price P, which compares the input amount with P2, P2+50, and P2+90. Comparator 13 is P1 for setting the product setting price P1
A price setting circuit 14 is a P2 price setting circuit for setting the product set price P2, and 15 is a P2 price setting circuit for controlling the sale of the product at the product set price P1 based on the output of the comparator 11 for P1.
1 is the bend control circuit for P2, and 16 is the comparator 1 for P2.
A bend control circuit for P2 controls the sale of the product with the set price P2 by the output of 2, 17 is a coin payout control circuit, 18 is a coin jam detection circuit, 19 is a refund latch circuit, 20 is an automatic refund circuit, and 21 is a selector. latch circuit,
22 is a CREM control circuit (described later), 23 is a two-phase clock pulse generation circuit, and 24 is a bit pulse generation circuit.

Also, A1 is a YIO no change signal, A2 is a ¥50 change change signal, B1 is a coin payout signal, B2 is a Y50 coin payout signal, VEND1 is a P1 product sales ready signal, ■EN
D2 is the P2 product sales availability signal, POS is the coin payout confirmation signal, 0 is manual refund, SEL1 is product set price P
Select input of product 1, SEL2 is product setting price P2
Product selection input, t0 to t7 are bit pulses, E
SC-ACC and ESC-RTRN indicate the ¥100 coin collection signal and refund signal in the escrow.

Terminals 1 to 2 and T correspond to those in FIG.

In the example, “1” in the decimal system is YI for the amount.
It is expressed as a 6-bit pure binary number representing O.

If the coins used here are ¥10, Y50, YIOO, then ¥10 is “O O O O O O 1”, Y
5 0 ha”O O O 1 0 1”, ¥100 is “O
Each is represented by a binary code of "O 1 0 1 0".

Therefore, the maximum selling price when using 6 bits is 63
The maximum selling price can be increased by increasing the number of bits.

The operation of the electronic control circuit unit for coin knocking in a vending machine according to the present invention will be explained in detail based on the block diagram shown in FIG.

Each time a coin of ¥10, ¥50, or YIOO is inserted, the inserted coin is converted into a binary code representing the amount by the encoder 1 as described above and applied to the adder/subtractor 2, and then the total payout shift register 3 The total amount of input is added to the amount of input so far stored in , and the total amount of input is stored in the shift register 3 for total payout.

The total payout shift register 3 is shifted by two-phase clock pulses.

At this time, the ¥100 coin is temporarily held in a space called escrow, and the ¥10 and ¥50 coins are automatically stored in their respective change cylinders.

Moreover, each time a coin is inserted for Y50 and YIOO coins, the person's capulse is sent to the ¥50 number register 4 and the ¥100 number register 5, and the respective inserted numbers are stored.

If a coin is jammed when inserting a coin, the coin jam detection circuit 18 detects the coin jam;
Coin return electromagnet (Coi) that returns inserted coins as is.
n Return Electromagnet C
It has the function of sending the signal to the CREM control circuit (referred to as REMa) and preventing coin insertion.

Here, a coin jam is a state in which coins are jammed and a coin input signal is continuously output.

The product price is expressed in a 6-bit pure binary binary code in which n1st in decimal notation represents YIO.

In the embodiment of the present invention, by providing a P1 price setting circuit 13 and a P2 price setting circuit 14 for setting two product prices P1 and P2 in one control circuit unit, two prices can be set in one control circuit unit. This control circuit unit can be used to sell different products.
By installing a plurality of vending machines in one vending machine, a vending machine with multiple prices can be obtained.

In this case, the values of P1 and P2 are P, ,
Some regulations state that one of P2 must be larger, but in the present invention, P1>P2
, P1-P2, P1<P2.

Among the 6-bit pure binary binary codes set in the P1 price setting circuit 13 and P2 price setting circuit 14, the binary code of P1 is P1+50 addition circuit 8 and P1+90.
In addition circuit 7, the binary code of P2 is applied to P2+50 addition circuit 1'0 and P2+90 addition circuit 9.

The P1+50 adder circuit 8 and the P2+50 adder circuit 10 also receive a bit pulse from the bit pulse generator 24 representing t1+t3, that is, Y50.
1' is added, and P1+50 and P2+50 are added.

In addition, an 11+14 bit pulse, ie, "001001" representing Y90, is applied from the bit pulse generating circuit 24 to the P1+90 adder circuit 7 and the P2+90 adder circuit 9, and the addition of P1+90 and P2+90 is performed.

The bit pulse generation circuit 24 generates a two-phase clock pulse φ1.
, φ2, and generates bit pulses from t1 to t7 in a clock pulse period, of which the bit pulses from t1 to t6 are used to represent the amount of money.

Product setting price P1, P1+5.0, P1+9 0
, the total input amount X stored in the shift register 3 for total payout is stored in the comparator 11 for product setting price P1 as product setting price P2, P2+50, P2+90.
, the total input amount X is determined by the product setting price P2 comparator 12 (respectively), and as a result of the comparison, the product setting price P1 comparator 11 determines that X=P1, .
X>P,, X>P1+9 0, X1P1+50, from comparator 12 for product setting price P2, X=P2, X>P
2. An output of X>P2+90, X-P2+50 can be obtained.

The output from the comparator 11 for product setting price P1 is P1
The output from the product setting price P2 comparator 12 is applied to the P2 bend control circuit 16.

Is there change in the bend control circuits 15 and 16 for P1 and P2? A no-IO signal A1 and a no-change Y50 signal A2 are added.

In the embodiment, the bend control circuit 15 for P1 + P2
．． P1P2 product sales enable signal VEND1, VE from 16
ND2 is issued under the following conditions.

f) If X=Pt or P2, +*)p1<x≦P1+90orP2x≦P2+90
If YIO has change, ! ! ! ) If X = P1 + 5 0 or
If there was no IO change, sales that required change were not performed, but in the device of the embodiment, the number P1 + 5 0, which is the sum of the product setting prices P and P2 and Y50.
By comparing .

When the customer selects either the product with the P1 price or the P2 price, an operation input SEL is sent to the select latch circuit 21.
Or SEL2 is sent and select latch circuit 2
1 to determine whether to select the product with the product setting price P1 or the product with the product setting price P2, and select SEL1 or SEL1.
A signal ESC-ACC for collecting the ¥100 coin temporarily stored in the escrow is sent to the escrow in response to an external sales signal T generated almost simultaneously with EL2.

Next, the output signal of the select latch circuit 21 is sent to the P1 price setting circuit 13 when SEL1 is selected, and to the P2 price setting circuit 14 when SEL2 is selected, depending on whether SEL1 or SEL2 is selected. .

P, price setting circuit 13 and P2 price setting circuit 14
When the output signal from the select latch circuit 21 is received, a binary code representing the product setting price is sent to the adder/subtracter 2.

In the adder/subtractor 2, the set price sent from the P1 price setting circuit 13 or the P2 price setting circuit 14 is subtracted from the input total amount X stored in the total payout shift register 3 at this time.

That is, subtraction of X-P or X-P2 is performed, and the subtraction result K is stored in the total payout shift register 3 as the change amount.

This stored content K indicates the amount of change.

That is, the total/repayout shift register 3 functions as a change register.

The contents K stored in the total payout shift register 3 are inputted to a K≧50 comparator 6 to compare whether the change amount K is larger than 50 yen.

K≧50 Comparator 6 receives t1+ as a signal of ¥50
The bit pulse of t3 is P1+50 addition circuit 8 and P2
It is added in the same way as the +50 adder circuit 10.

K≧50 The output signal of the comparator is sent to the coin payout control circuit 17.

The coin payout control circuit 17 also receives as inputs a Y50 no change signal A2, an output signal representing the amount of change K% Y50 stored in the total payout shift register 3 and the number of coins inserted into the Y50 coin count register 4, and a coin payout confirmation signal. POS has been added.

Coin payout signal B in coin payout control circuit 17
1, Y50 Change is paid out using the coin payout signal B2 as follows.

1) In the case of K〈¥50...Payout in ¥10 x n pieces (n<5) ii) In the case of K>Y50 and Y50 change is available...
Payout with Y50 x 1 piece, Y10 x n pieces (n<
5) III) If K > ¥50 and there is no ¥50 change...
...Payout in YIO x n pieces (1 0>n>O) In the example, when a coin is inserted, the change is Y9
Since only products with a value of 0 or less can be sold, the amount of change must be Y90 or less.

This means that the output signal from the P1 comparator 11': J6 and the P2 comparator 12 is X>P1+9 0 ,
VEND1, VEND2 from the bend control circuit 15 for P1 and the bend circuit 16 for P2 due to X>P2+90
This can be done by controlling the signals of

Each time a coin is paid out, the coin payout control circuit 17 receives a coin payout confirmation signal POS and sends a signal 2 representing the payout amount.
The decimal code is sent to the adder/subtractor 2, and the paid change is subtracted from the change amount K stored in the total payout shift register 3.

Then, when the change amount stored in the total payout shift register 3 reaches 0'', the payout of change is stopped.

However, if the amount of change is less than Y50, the output signal of the K>50 comparator 6 causes the ¥50 change to be paid out first and the remainder to be paid out in the amount of ¥10.

When performing a manual refund, a manual refund manual PO is added to the refund latch circuit 19, and if there is no selection signal within a certain period of time, a full refund will be made.

¥100 will be paid out from the escrow that was temporarily held,
Subtraction is performed from the total input amount X by the adder/subtractor 2 and the total payout shift register 3 until the contents of the ¥100 coins register 5, which stores the number of ¥100 coins inserted, reach 0''.

Similarly, the adder/subtractor 2 and the total payout shift register 3 subtract from the input amount X until the number of inserted coins stored in the ¥50 coin register 4 becomes "0".

In this case, the output signals of the ¥50 number register 4 and the ¥100 number register 5 are converted into binary codes representing the respective amounts via the encoder 1 as shown in the block diagram of Fig. 1, and are further added and subtracted. Subtraction is performed by unit 2.

After Y50 and YIOO are refunded, ¥10 is refunded until the remaining memory contents of the total payout shift register 3 reach 11011.

The refund ends when the stored content of the total payout shift register 3 becomes "0".

In addition, if the input amount
0 and automatically sends a signal to the refund latch circuit 19 to issue a full refund.

At this time, the refund latch circuit 19 sends out the ESC/RTRN signal, and the Y50 sheet number register 4 and the ¥1
Sends a signal to the 00 sheet count register 5.

Further, if a coin is jammed, a sale signal is issued, or a refund is being made, the CREM control circuit 22 outputs a signal CREM to prevent coin insertion.

The operation of the control circuit unit of the present invention based on the block diagram of FIG. 1 as described above will be more clearly illustrated by the explanation of the embodiment of the block diagram of FIG. 1 shown in FIGS. 2 and 3. It will be done.

FIGS. 2 and 3 are circuits showing an embodiment of the invention which performs the operation shown in FIG. 1.

The present invention will be explained in detail based on FIGS. 1, 2, and 3.

In FIGS. 2 and 3, the signals from ■ to ■ are signals within the control circuit unit according to the present invention, and the other signals may be sent from devices in the vending machine other than this control circuit unit. Or it may be sent to another device.

The circuit illustrating the embodiment of the encoder 1 in FIG.
In the figure, AND circuits 25 to 27, 37, OR circuit 28
~3L38, NAND circuits 32 to 35, inverter circuits 36 and 41, cycle timer 39, and wired OR circuit W01.

Initially, the symbol ■ indicating that the electronic control circuit for the coin knock in the vending machine according to the present invention is in operation is "0", so "1" is added to the AND circuits 25 to 27 from the invert circuit 41. Coin input ￥10, Y5
0, ¥100, output nln is generated in AND circuits 25 to 27 correspondingly, and the output ゛゜1'' is added to OR circuits 28 to 30. It produces an output "1'' which is identical to the output of 27.

In addition, the NAND circuit 32 has a bit pulse of t1, NA
The ND circuit 33 has a bit pulse of t2, and the NAND circuit 3
4 is the bit pulse of t3, and the NAND circuit 35 is the bit pulse of t4.
A bit pulse of is applied from the silator resistor SR1-.

The shift register SR1 is shown as the bit pulse generation circuit 24 in the block diagram of FIG. 1, and is a two-phase dynamic shift register, and is shifted by two-phase clock pulses φ1 and φ2 to generate bit pulses from t1 to t7. Configure it to occur.

The outputs of the OR circuits 29-31 are applied to the NAND circuits 32-35 in addition to the bit pulses t1-t4.

By doing this, if there is a coin input of ¥10, this input will be converted to NAN via the OR circuit 28.31.
Since it is applied to the D circuit 32, the output of the NAND circuit 32 is synchronized with the bit pulse of t1, so it is expressed as "1 1 1 1 1 0" in a 6-bit binary number, and is sent to the Ishibark circuit 36 via the wired OR circuit WO1. By inverting the value to "o o o o o i'" and expressing ゜゛1 as ¥10, a binary code representing ¥10 in pure binary system can be obtained.

In the same way, the coin input of ¥50 is NAND circuit 32,3
4, and in synchronization with the bit pulses of t and jt3, the output of the inverter circuit 36 appears as ゜'000101'', that is, a binary code indicating Y50.

In addition, the ¥100 coin input is added to the NAND circuit 33.35, and the output of the invert circuit 36 is ``0 0 1 0 1 0'' in synchronization with the bit pulses at t2 and t4.
“In other words, a binary code indicating ¥100 appears.

The output of the inverter circuit 36 is applied to an AND circuit 37, to which a signal from a cycle timer 39 is also applied.

The outputs of the OR circuits 28 to 30 are output to the cycle timer 39.
It is applied via the R circuit 38.

That is, the cycle collector 39 functions to send an output "1" to the AND circuit 37 for a certain period of time when any coin of ¥10, ¥50, or YIOO is input.

The fixed time is generally one cycle time of bit pulses from t1 to t7.

Therefore, the output of the AND circuit 37 is only during one cycle time from t1 to t7, that is, the pulse representing the coin input of ¥10, ¥50, and YIOO is output from the output terminal of the AND circuit 37 only once. Two types of coin calculations do not occur.

A pulse representing the input amount from the AND circuit 37 is sent to the adder/subtractor 2 as shown in the block diagram of FIG.

The adder/subtracter 2 and the total payout shift register 3 shown in the block diagram of FIG. 1 are composed of the parts shown in FIG. ing.

The adder/subtractor ADD is a pure binary adder/subtractor (
Regarding the internal detailed circuit, if necessary, for example,
August 15B, ■ Radio Gijutsusha Publishing “Calculator Technology Textbook・
Please refer to Figures 5 and 8 on page 176 of "Basic Edition."

), and for the output from shift register SR2,
This is a type of addition or subtraction of the binary code signals given through the OR circuit 44 and the result is stored in the shift register SR2, but this may also be of a type in which the complement is taken and subtraction is performed. However, a well-known adder/subtractor can be used.

By doing this, when there is a coin input in the adder/subtractor ADD, the inverter circuit 43
''' is added, the mode becomes addition mode, and the pulse representing the input amount from the ADD circuit 37 is sent to the adder/subtracter ADD.
1, and stored in shift register SR2.

The shift register SR2 is a two-phase dynamic shift register that is shifted by two-phase clock pulses.

P1 and P2 price setting in the block diagram of Figure 1? Road 1
3.14 is PRICE1, PRICE2 in Figure 2
terminals and NAND circuits 83 to 94, 98, 99,
This is implemented by wired OR circuits WO2 to W012 and inverter circuits 96 and 97.

NAND of each terminal of PRICE1 and PRICE2
The terminal connected to circuit 8389 is NAND circuit 83
．． 89 is connected so that the bit pulse of t1 is applied, so it has a weight of "1", and the terminals that are connected to the NAND circuits 84 and 90 have a weight of "2", and the NAND circuits 85 and 89 have a weight of "2". The terminal connected to .91 has a weight of ``4'', and the NAND circuit 86.9
The terminal connected to 2 has a weight of "8", the terminal connected to NAND circuit 87.93 has a weight of elf 699, and the terminal connected to NAND circuit 88.94 has a weight of "8".
It has a weight of '32'', and by giving a signal to any of the terminals of PRICE1, the NAND circuit 83
Since the outputs of ~88 are connected to the inverter circuit 96 via the wired OR circuits WO~WO6, the output of the inverter circuit 96 is NAND.
The outputs of the circuits 83 and 88 are inverted, and a 6-bit pure binary code representing the product setting price P1 can be obtained as the output of the invert circuit 96.

Similarly, the product setting price P2 can also be set by applying a signal to any of the terminals of PRICE2.

Of the product setting prices P1 and P2 obtained in this way, P1 is sent to P,+50 addition circuit 7, P1+90 addition circuit 8, and P2 is sent to P2+, as shown in the block diagram of FIG.
The signals are sent to a P2+90 adder circuit 9 and a P2+90 adder circuit 10, respectively.

In FIG. 2, the portion consisting of the full adder FA1, the AND circuit 49, and the flip-flop circuit FF is the P1+90 addition circuit 7, and the portion consisting of the full adder FA2, the AND circuit 50, and the flip-flop circuit FF2 is the P2+90 addition circuit 9. The part consisting of the full adder FA3, the AND circuit 51, and the flip-flop circuit FF3 is the P1+50 addition circuit 8, and the part consisting of the full adder FA4 is the P2+
50 addition circuit 10.

Full adders FA1 and FA2 have two-phase soft registers S.
Of the bit pulses t1 to t7 generated by R1, t
1 and t4 are connected so that they are applied as the output of the OR circuit 81, thereby causing the full adder FA1'j
6 and FA2 are binary numbers representing 90 “0 0 1 0
0 1'' is added, and an output of P1+90 or P2+90 can be obtained from the full adders FA1 and FA2.

Similarly, Y
By applying the binary number "0 0 0 1 0 1" representing 50, we can obtain P1+50 and P2+50 as its output.

- Comparator 11 for P1 in the block diagram of FIG.
are comparators COMP2 to COMP5 in FIG.
, and the comparator 12 for P2 is the comparator COMP
This is a part consisting of 6 to COMP.

A 6-bit binary code representing the total amount of inserted coins X>P
1 signal ■ is obtained.

The comparator COMP3 contains a 6-bit binary code that represents the total amount of coins inserted, are applied, and as a result of the comparison, a signal (2) with X>P1+90 is obtained.

The same input as comparator COMP2 is applied to comparator COMP4, and the comparison result is X=P
1 signal ■ is obtained.

The comparator COMP5 receives a 6-bit binary code representing the total amount of input coins As a result of the comparison, a signal [F] of X=P1+50 is obtained.

For the product setting price P2, in the same way as for the product setting price P1, the signal ■ of X>P2 is sent from the comparator COMP6, and the signal ■ of X>1, +90 is sent from the comparator COMP7.
, a signal (2) of X-P2 is obtained from the comparator COMP8, and a signal (2) of X-P2+50 is obtained from the comparator COMP8.

In this way, in this embodiment, sales and change payments are controlled using the comparison results obtained by comparing the input amount with several amounts based on the product's set price, as described later. It is.

Output signals of the comparators COMP2 to COMP9 shown in FIG. 2: ■X>P, . ■X>P1+9 0, ■X1P11■X=P1+5 0, ■X>P2, ■X>P2
+90, ■X-P2, ■X-P2+50 are shown in Figure 3?
Like NAND circuit 1oo, ioi, AND circuit 102
, 106, 108, P1 bend control circuit consisting of OR circuits 105, 107, inverter circuits 109, 110, NOR circuit 118, flip-flop circuit FF1, or NAND circuits 111, 112, AND circuit 113,
116, 119, OR circuits 114, 117, inverter circuits 115, 110, NOR circuit 118, and flip-flop circuit FF13 are added to the P2 bend control circuit.

Considering a product with a set price of P1, X1P1
At this time, the signal (2) of X-P1 is applied to the OR circuit 105, and the output of the OR circuit 105 becomes one input of the AND circuit 106.

The other input of the AND circuit 106 is the output of the OR circuit 82, that is, the signal ``P1-0'' is added, so when the product setting price P1 is not 0, lt1jl is added, so when the signal ``X=P1'' is received. Then, "1" is added to one of the two input terminals of the AND circuit 108 as the output of the OR circuit 107.

The other input terminal of the AND circuit 108 is the NOR circuit 118
is connected to the output terminal of

The two input terminals of the NOR circuit 118 (wired A
Signals from ND circuit WA3 and flip-flop circuit FF1 are sent.

As described later, the flip-flop circuit FF1 allows the customer to select a product using a push button, etc., and selects SEL1 or SEL.
2 and the SEL signal G indicating that the product has been sold or the refund signal ■, which occurs a little later than that, is in a reset state, so the input from the flip-flop circuit FF11 to the NOR circuit 118 is It(1!+). It is.

The wired AND circuit WA30 has as inputs the output of the flip-flop circuit FF15 inverted by the inverter circuit 149, the output of the flip-flop circuit FF18 inverted by the inverter circuit 147, and the output of the NAND circuit 156. .

When there is no refund manual PO, flip-flop circuit F
Since F and 5 are not set, the inverter circuit 149
The output of the inverter circuit 147 is "1", and since the flip-flop circuit FF18 is not set when there is no sales signal T, the output of the inverter circuit 147 is "1".

The output of the flip-flop circuit FF1 and a signal SING are applied to the NAND circuit 156 as inputs.

SING has two product price setting circuits in the embodiment, so if only one product price setting circuit is used, the price setting number selection signal SING is set to ゛゜0.
″, or ″1″ when using two product pricing circuits.
Add it like this.

Regardless of the state of the SING signal, when there is no sales signal T, the output of the NAND circuit 156 is "'1".

Therefore, when there is no manual power PO to refund the sales signal T1, the output of the wired AND circuit WA3 is tlltl, this output is inverted by the invert circuit 160, and "O" is added as an input to the -i10R circuit 118.

Therefore, if there is no sales signal T1 refund manual PO, NO
The output of the R circuit 118 is "1", and when the output of the OR circuit 107 becomes "1", the flip-flop circuit FF1
2 to generate the signal VEND1 that the item with the P1 price can be selected, allowing the customer to select the item with the P0 price.

The product with the product setting price P2 is exactly the same as the product with the product setting price P1, and the OR circuit 95
This is performed based on the signal 2=0, and a signal VEND2 can be obtained from the flip-flop circuit FF13.

Based on this VEND1 and ■END2, a display is displayed on the vending machine indicating that the customer can select the product with the product set price P1 or P2, and when the customer selects either, a signal SEL1 or SEL,2 is generated. It is sent together with the sales signal T to the electronic control circuit device for the vending machine coin knock.

That is, the sales signal T is a signal indicating that the product has been sold.

Furthermore, if a coin is inserted that causes the signal ■ of X>P1, the signal ■ of X>P1 will be generated by the AND circuit 10.
2 and as the other input of the AND circuit 102
The P1+90 signal ■ is inverted by the NOT circuit 109, and the Y50 no change signal A2 is sent to the NOT circuit 110.
The inverted signal and the signal of X-P1+10 are converted to NAN
D: NA obtained by adding the output of the circuit 100 to the NAND circuit 101 together with the YIO no change signal A1
By adding the output of the ND circuit 101,
>P1 and X≦P1+90 and if there is YIO change, an output T+ is generated in the AND circuit 102, and the output is
By adding it to the R circuit 105, the VEND1 signal can be obtained in the same manner as in the case of X-R1 described above.

Also, when X = P1 + 50, there was no change for YIO and it was ¥50.
What if you have change? AND circuit 100 has ``1''
Since and ``1'' are added, the output is ``゛゜0'',
Since the output +1011 is added to the NAND circuit 101 along with "1" indicating that YIO has no change, the output of the NAND circuit 101 becomes "1", and X=R1+50 becomes X>P
1 and X≦P1+90, all the inputs of the AND circuit 102 are "1", so the above-mentioned X>P
Similarly to 1, the signal END1 can be obtained.

Regarding the product setting price P2, X>P2, X-P2+50
In the case of , the output of vEND2 can be obtained by thinking in exactly the same way as in the case of the product setting price P1.

The generation of the sales signal T causes the following to take place in the device of the actual case.

The sales signal T is added as an input to an OR circuit 154, and O
The output of R circuit 154 is applied to AND circuit 155.

The output of a NOR circuit 159 which receives the outputs of flip-flop circuits FF16 and FF11 as inputs is also added to the AND circuit 155.

The output of the flip-flop circuit FF16 is @10++ when the sell signal T is generated, and the output of the flip-flop circuit FF1 is @10++.
, 8 remains at ゜゛0'' when the output power of be done.

This output is delayed by 100 ms by delay circuit Delay4 and is applied to AND circuit 158 as the output of OR circuit 157.

Since nlu is added to the AND circuit 158 from the aforementioned NOR circuit 159 as another input, the OR circuit 157
When "1" is generated as the output of the flip-flop circuit FF18, the flip-flop circuit FF18 is set.

The receipt signal ESC- of the ¥100 coin held in the escrow is generated by the output of the flip-flop circuit FF,8.
Generate ACC.

Also, the output e+191 of the flip-flop circuit FF18
is applied to the ANI) circuit 131 together with the SEL1 signal or to the AND circuit 132 together with the SEL2 signal.

Since the SEL1 and SEL2 signals are generated almost simultaneously with the sales signal T, the flip-flop circuit FF18
When the output ++ 1 II occurs, it is already SEL1
or SEL2 is AND circuit 131 or 132
has been added to.

Therefore, at the same time as the output ""1" of the flip-flop circuit FF-18 is generated, the output "1" is generated from the AND circuit 131 or 132, and the output of the AND circuit 131 is output from the AND circuit 1.
The inverter circuit 161, wired OR circuit W0,
4, W01. , the inverter circuit 143 and the cycle timer 163.

By applying it to the AND circuit 141 via the cycle timer 163, the output of the AND circuit 141 becomes the bit pulse t.
This will occur only once in the interval 1 to t7.

Similarly, the output of the AND circuit 132 is output from the AND circuit 142.
Directly connect one of the two input terminals to the terminal, and the other terminal connect the NOT circuit 162 and the wire FOR circuit WO1, NO.
Since the bit pulses are applied via the T circuit 143 and the cycle timer 163, the output of the AND circuit 142 is the bit pulse t1 to t.
Occurs only once every 7.

If the output of the AND circuit 141 is SEL, the signal ■, and the output of the AND circuit 142 is the SEL2 signal ■, then the SEL1 signal ■
is applied to NAND circuit 98 in FIG.

The NAND circuit 98 also has an inverter circuit 9 as an input.
Since the binary code representing the product setting price P is added from . and is added to the adder/subtractor ADD'.

That is, since the SEL1 signal ■ is generated only once in the interval from t1 to t7, the output of the OR circuit 44 is a binary code representing the product setting price P1.

The adder/subtractor ADD has an inverter circuit 43 as another input.
When there is no recoil input signal ■, since ``'1'' has been added, the subtraction mode is entered, and the adder/subtractor ADD subtracts the product setting price P1 from the total input amount X, and the change amount K is transferred to the shift register SR2. be remembered.

The same is true for the product setting price P2, and SE
The L2 signal ■ is applied to the NAND circuit 99, and the rest is carried out in the same way as for the product setting price P1.

These change amounts are calculated using the cycle timer 16 in FIG.
3, and when the output of the cycle timer 163 disappears, the output of the inverter 140 becomes 91 1 91
becomes.

The AND circuit 133 receives the output of the inverter 140, the SEL signal e which is already ゜゜1'', and the signal ■ which becomes ``1111'' when the contents of the shift register SR2 are not O.
Therefore, when the output of the cycle timer 163 disappears and the contents of the shift register SR2 (that is, the amount of change) is not 0, the AND circuit 133 outputs an output and issues the coin payout signal B1 via the OR circuit 134. Start the change payout operation.

Next, the mechanism for dispensing change will be explained.

The stored contents of the shift register SR2 representing the change amount K obtained by subtracting the product setting price P1 or P2 from the input amount X are sent to the comparator COMP1, which indicates K≧50 comparator 6 in FIG. 1, and is compared with Y50.

The output of the comparator COMP1 is applied to an AND circuit 77, but the AND circuit 77 also receives as other inputs the Y50 no change signal A2 inverted by an inverter circuit 78, and the SEL signal C which is the output signal of the flip-flop circuit FF18. has been added.

Therefore, if there is a change coin of Y50 and a product with a change amount of Y50 or more is sold, the output of the AND circuit 77 will be ``
1'' is generated, and the Y50 change payout signal B2 is generated as the output of the OR circuit 76, and this and the above-mentioned coin payout signal B1 are generated.
Y50 change is paid out using .

The output of the OR circuit 76 is added to the AND circuit 74,
The D circuit 74 receives a change payout confirmation signal PO as another input.
S is added, and when Y50 change is paid out, an output "1'" is generated in the AND circuit 74, and this output is O.
It is added to the R circuit 29 and converted into a binary code representing Y50 in the same way as when a coin is inserted, and then sent to the adder/subtractor ADD.
However, at this time, the output of the inverter circuit 43, which is the other input of the adder/subtractor ADD, is added to the AND circuits 25 to 25.
Since the output of 27 is ゛゜0'', it is ゛゜1', so the adder/subtractor ADD is in subtraction mode, so the change amount K
and Y50 are subtracted.

When the change amount K becomes smaller than Y50, the output of the AND circuit 77 becomes "0", so "1" is added to the AND circuit 73 via the OR circuit 76 and the inverter circuit 75.

The same change payout confirmation signal POS as the AND circuit 74 is added to the AND circuit 73;
Like the D circuit 74, every time change is dispensed, the output signal I+1 14 is sent to the OR circuit 28 to subtract YIO from the change amount K.

To pay out the change of YIO, if the change amount K stored in the shift register SR2 still remains after subtracting the change of Y50, the change is sent to the shift register S by the OR circuit 46.
Since the signal ■ indicating that the memory contents remain in R2 continues to be generated, the AND circuit 133 and the OR circuit 134 continue to output the coin payout signal B1, and this and the ¥50 coin payout signal B2 have disappeared. This is done depending on the conditions.

These are known techniques, and generally the signal B1 is given to the change dispensing motor, and the signal B2 is given to the ¥50, YIO switching solenoid.

Since Y50 change payout has priority over YIO change payout,
It becomes possible to pay out the minimum number of change.

Next, consider the case of refund.

First, we will discuss the case of manual refund.

The coin input signal ■ generated from the OR circuit 40 is the OR circuit 1
20 and the output of the OR circuit 120 is added to the AND circuit 12.
Added to 1.

The AND circuit 121 has a NOR circuit 122 as another input.
The output of is added.

The sales signal T and SEL signal ○ are connected to the NOR circuit 122.
Since the R circuit 148 and the output of the inverter circuit 150 obtained via the inverter circuit 150 are added, when there is no sales signal T, the output of the NOR circuit 122 is ``1''.
”, so if there is a coin input signal, AND
゛1'' is generated at the output of the circuit 121, and the flip-flop circuit FF14 is set.

The output of flip-flop circuit FF14 is manual refund P.
It is added to the AND circuit 123 along with O.

Therefore, when a refund manual PO occurs, an output ゛゜1'' is generated in the AND circuit 123, and an AND output is generated via the NOR circuit 124.
added to circuit 125.

Since the AND circuit 125 has the input of the NOR circuit 126 added with the same input as the aforementioned NOR circuit 122 as another input, the output 11 1 t of the OR circuit 124
By adding +, the output of the AND circuit 125 becomes "1", and the flip-flop circuit FF15 is set.

The output of flip-flop circuit FF1 is a delay circuit ・D
elay2, AND circuit 146 via OR circuit 145
added to.

Since the output of the above-mentioned NOR circuit 148 is also added to the AND circuit 146 as an input, when the SEL signal 6 is not generated, "1" is generated, so the AND circuit 1
An output "1" is generated at 46, and the flip-flop circuit FF1
6 is set and a refund signal (■) can be obtained.

By doing this, if the sales signal ■ occurs before adding the refund manual PO, the flip-flop circuit FF
14 is reset, so no refund signal is obtained, and even after the refund manual PO is applied, if the sales signal ■ or the SEL signal e occurs during the delay time of the delay circuit Delay2, the flip-flop circuit FF15 is reset. The sales signal T and SEL signal e are given priority.

In addition, an automatic refund signal ATPO, which will be described later, is added to the terminal of the manual refund manual PO.

Automatic refunds will be made in the following cases:

That is, the output of the flip-flop circuit FF,2 described above is passed through the inverter circuit 127 to the wired AND circuit WA1.
In addition, the output of the flip-flop circuit FF13 mentioned above is connected to the wired AND circuit W via the inverter circuit 128.
In addition to A1, the output of wired AND circuit WA1 is
Add to D circuit 129.

In addition, the signal ■ of X>P1 and the signal ■ of X-P1 are added to the OR circuit 103, and the signal ■ of X>P2 and the signal ■ of X-P2 are wired and In addition to circuit WA2, wired AND circuit W
The output of A2 is added to the AND circuit 129.

By doing this, wired AND circuit WA2
If you input an amount greater than or equal to the maximum fixed price of the product, an output n 1 ty will be generated, and the wired AN
The output of the D circuit WA1 is a flip-flop circuit FF12.
, "1" is generated when the outputs of the FFs 13 are not generated, and the AND circuit 129 obtains the automatic refund signal ATPO.

That is, in this embodiment, if the sales outputs VEND, .

This automatic refund signal ATPO is the manual refund signal P described above.
It is added at O, and the refund signal ■ can be obtained in the same way.

Refunds are made in the following manner based on the refund signal (2) obtained in this manner.

In the embodiment, as shown in the block diagram of FIG.
For the insertion of 0, YIOO coins, a Y50 coin count register 4 and a ¥100 coin count register 5 are provided to count the number of coins inserted.

In other words, in Figure 2, the Y50 sheet number register is R1, ¥
The 100-odd sheets are indicated by register R2.

Registers R1 and R2 sequentially set the flip-flop circuit each time an input is applied.
Register R2 can count up to 15 Y50 coins (up to 750 yen), and register R2 can count up to 8 coins (800 yen).

Y5 from the AND circuit 26 is input to the Y50 sheet number register R1.
0 coin input signal is being sent, and Y50
The coin input signal is A along with the output of the cycle timer 39.
is added to the ND circuit 53, and the output of the AND circuit 53 is ORed.
added to circuit 54.

Cycle timer 3 every time there is a coin input signal of Y50
Since the signal is applied to the AND circuit 53 only during the bit pulse period from 9 to t1 to t7, the output pulse signal of the OR circuit 54 is stored in the Y50 coin input number register R1.

Similarly, the ¥100 coin input signal from the AND circuit 27 is added to the ¥100 coin number register R2.

Furthermore, the ¥100 coin input signal is input to the cycle timer 39.
Since the output of the AND circuit 64 is applied to the OR circuit 67, the output pulse of the OR circuit changes the ¥100 coin input signal to ¥10.
It is stored in the 0-sheet count register R2.

At the same time as the refund signal (2) is generated, the refund signals ESC and RTRN for the ¥100 coin held in the escrow are issued, and the ¥100 coin held in the escrow is refunded.

The Y50 number register R1 includes an OR circuit 58, an AND circuit 59, an inverter circuit 60, and a flip-flop circuit FF.
At the same time as the Y50 coin input is added to the Y50 coin count register, the flip-flop circuit FF6 is set, and when the stored content of the Y50 coin count register becomes ``0'', the flip-flop circuit F6 is attached.
By resetting F6, the stored contents of the ¥50 number register R1 can be determined based on the output of the flip-flop circuit FF6.

Similarly, OR circuit ゜・69 is applied to ¥100 number register R2.
, an AND circuit 70, an inverter circuit 72, and a flip-flop circuit FF7 are attached, and the contents of the ¥100 number register can be determined based on the output of the flip-flop circuit FF7.

When the refund signal (2) is generated, the refund signal (2) is applied to the AND circuit 66, and by adding the clock pulse φ3 as another input to the AND circuit 66, the AND circuit 66 can obtain an output synchronized with the clock pulse φ3.

An OR circuit 71 whose inputs are the output of the AND circuit 66, the 00 sheet number register R2, and the flip-flop circuit FF7.
Since the output of the flip-flop circuit FF7 is added to the N-mount circuit 65, if the output of the flip-flop circuit FF7 is n1n, that is, ¥
While the number of ¥100 coins inserted is stored in the 100 coins register R2, an output "'1" is generated in the AND circuit 65, and a pulse is given to the ¥100 coins register R2 as an output of the OR circuit 67, and the YIOO coins register is output. The memory of R2 is sequentially moved toward the output end.

When a signal is output from the output end of the ¥100 sheet count register R2, that signal is added to the AND circuit 68 along with the output of the AND circuit 65, and a signal is output from the output end of the ¥100 sheet count register R2, and the number of ¥100 sheets is stored. The output "1" generated from the AND circuit 68 is outputted to the OR circuit 30 each time the subtraction is performed.
In addition to this, the input amount X stored in the shift register SR2 furnace is added in the same way as when paying out change for Y50 and YIO mentioned above.
Subtract ¥100 from .

By sequentially subtracting the number of sheets stored in the ¥100 sheet number register R2 in this manner, the stored contents of the FM00 sheet number register R2 are emptied.

As the storage contents of the YIOO sheet number register R2 become empty, the output of the OR circuit 71 becomes "0", and the NOR circuit 6
"0" is added to one input of the inverter circuit 56, and "1" is added to the AND circuit 63 as the output of the inverter circuit 56.

The AND circuit 63 also receives as inputs a signal from the output end of the Y50 sheet number register, a refund signal (2), and a signal (2) from the OR circuit 46.

If Y50 is turned on, flip-flop circuit FF6 is set, so the output of NOR circuit 61,
Therefore, the output O of the AND circuit 62 is not generated immediately, but the stored contents of the ¥50 sheet count register R1 and the ¥100 sheet count register R2 are simultaneously moved toward the output terminal via the AND circuit 57 and the OR circuit 54. Therefore, the Y50 sheet number register R produces an output after the cicada time, although it may be earlier or later depending on the stored contents.

This output causes the flip-flop FF6 to be reset via the inverter 60 to prevent further movement of the memory contents via the M medium circuit 57, and the NOR
The circuit 61 generates an output, and the output ◎ is generated only through the AND circuit 62.

The output of the Y50 sheet number register R1 is given to the AND circuit 63 on the other hand, and as a result, the AND circuit 63 outputs "1".
is generated, its output is applied to the OR circuit 76, and the above-mentioned Y
As in the case of dispensing 50 change, the Y50 dispensing signal B2 and the output O of the AND circuit 62 mentioned above are connected to the OR circuit 1 in FIG.
Y50 due to the coin payout signal B1 obtained through 34.
coins are paid out, and Y50 is subtracted from the memory contents of the total payout shift register SR2 in response to the change payout confirmation signal POS.

The change payout confirmation signal POS is applied to an AND circuit 55, and to the AND circuit 55, the signal from the output end of the Y50 number register R1 and the output of the inverter circuit 56 are added as other inputs, and the signal from the output terminal of the Y50 number register R1 and the output of the inverter circuit 56 are added to the AND circuit 55. If the memory content is empty and there is memory content in the ¥50 number register R1, an output "1" is generated in the AND circuit 55 by receiving the change payout confirmation signal POS, and this output is O.
It is sent to the Y50 sheet number register R1 via the R circuit 54,
Y50 The stored contents of the sheet number register R1 are moved by one to the output terminal force.

This process is repeated until the stored contents of the ¥50 number register R1 become empty.

When the stored contents of the Y50 coin number register R1 become empty, the output "1" of the AND circuit 63 disappears, and the payout of 50 coins ends.

When the stored contents of the Y50 sheet number register and the ¥100 sheet number register become empty, the stored contents remain in the shift register SR2 and the output ■ is generated from the OR circuit 46, but the AND circuit 62 still generates an output of 0. O because there is
The coin payout signal B1 continues to be outputted via the R circuit 134, and under the condition that this and the ¥50 coin payout signal B2 disappear, the same procedure as when paying out change is made.
Allow coins to be paid out.

Then, in the same way as when paying out change at YIO described above, the change payout confirmation signal POS is used to subtract from the shift register for total payout, star SR2, and the OR circuit 46
YIO coins are paid out until the output becomes 0'', that is, until the storage contents of the shift register SR2 become empty.

In this embodiment, Y50 sheet number register R1
By providing the ¥100 number register R2, the same amount and combination of coins can be refunded in case of refund.

In addition, in the embodiment, in order to deal with coin jams, when there is a coin input signal ■, the signal is ANDed.
By applying one force directly to the two input terminals of the circuit 151 and the other via the delay circuit Delay3, if the coin force ■ is still occurring even after the delay time, the AND circuit 151 outputs ゜゛1''. ' is generated, and by adding this output to the OR circuit 153, the output of the OR circuit 153 is "1".
This can prevent subsequent coin insertion.

However, the delay time of the delay circuit Delay3 is sufficiently long compared to the input signal time of the coin, and here it is 30
A value of 0 msec is used.

According to this method, when the power is interrupted and then turned on again (in case of a coin jam where a small coin input signal is generated), it is possible to prevent coin insertion after a delay time.

In the embodiment, the CREM is turned off (coin insertion inhibited state) in the following cases, that is, when the above-mentioned wired AND circuit WA2 outputs "1".

That is, when the input amount is equal to or exceeds the highest product setting price, there is no need to insert any more coins, so further coin insertion is prevented.

Further, when the sales signal T is sent, the manual refund manual PO, or the automatic refund signal ATPO is sent, the insertion of coins is prevented.

This can be done by adding the output of the wired AND circuit WA2, the output of the sales signal T1, the outputs of the flip-flop circuits FF1 and FF17 to the OR circuit 152, and adding the outputs of the OR circuits obtained as inputs to the OR circuit 153.
This can be implemented by performing CREM control using the output of the R circuit 153.

When operations such as sales, payout of change, and refunds are completed, operations for transitioning the control circuit unit to a state in preparation for the next sale (hereinafter referred to as "clear") are performed as follows.

That is, the coin payout signal B1 is applied to the NAND circuit 137 via the inverter circuit 136.

The NAND circuit 137 also receives the refund signal ■ and SE as inputs.
It consists of three people: applying the L signal e to the OR circuit 135 and applying the output of the OR circuit directly and via the delay circuit Delayl.

Therefore, when the coin payout signal B1 is not present and the refund signal (2) or the SEL signal (e) is generated, the output of the NAND circuit 137 becomes "'O" after a delay time.

The delay time of the delay circuit Delay1 is sufficiently long compared to other operating times of the embodiment device, and a value of 2 seconds is used here.

The output of the NAND circuit 137 is wired OR circuit WO1
Added to 3.

In addition to the wired OR circuit WO13, there is also a signal EXT clear signal indicating that it is not cleared from the outside.NAND circuit 1
30 outputs are added as inputs.

The EXT clear signal is an internal automatic clear signal ACL.
It is used when trying to obtain , and is usually ``'1''.

The NAND circuit 130 has a wired OR with the SEL signal e.
The outputs of circuits W014 and WO,, are added,
Since the wired-OR circuit changes the output to "0" when any of the inputs becomes "0", EX
When either the T, NAND circuit 130 or 137 becomes the output "0", a change in the output of the wired OR circuit W013 is applied to the inverter circuit 138, and the output of the inverter circuit 138 causes the flip-flop circuit FF to change.
The output of flip-flop circuit FF11 is inverted, and the output of flip-flop circuit FF11 is inverted.
When the output of is "1", an automatic clear signal ACL0 is obtained as an output to the inverter circuit 139.

That is, as is clear from the circuit diagram of FIG. 3, for example, even though the sales start signal T has arrived, the product selection signal SEL1
Or if SEL2' is not obtained, AND circuit 13
1 or 132 is not established, the output of the inverter 161 or 162 becomes "1", and as a result, the output of the NAND circuit 130 becomes "0" and the control circuit is automatically cleared.

Note that this automatic clear signal ACL■ is the comparator CO
Comparator COMP is added to MP1 to COMP9.
1 to COMP9 are reset.

In this way, the operation of the electronic control circuit unit for vending machine sales control of the present invention shown in FIG. 1 can be achieved by the embodiment shown in FIGS. 2 and 3, but as shown in FIGS. It is also possible to sell two or more products with different prices in one control circuit unit by further increasing the two product price setting circuits shown in 1 and adding other circuits accordingly.

Furthermore, the control circuit shown in Fig. 1 is considered as one unit,
When using a plurality of these units to control sales for a larger number of set prices, the sales enable signals VEND1 and VEND2 and product selection signals SEL1 and SEL2 related to the number of set prices are input and output from each unit individually. For other input/output signals, the signal lines from each unit may be wired OR (OR) connected for each signal.

If connected in this way, the input amount will be calculated for each unit, and a sellable signal will be sent for the set price at which the units can be sold.

When a product is selected, the sales signal T is input to all units, and the product selection signal is input to the unit with the selected set price, but the product selection signal is not input to the units that are not selected. The change payout signal is output only from the unit to which the product selection signal is input, and the units to which the product selection signal is not input are cleared.

In addition, when a manual refund manual PO is input, a refund payout signal is output from all units and the refund is paid out, but in this case, since the signal is output from all units to one payout mechanism at the same time, No extra money will be paid out.

As described above, according to the present invention, when a plurality of vending machine control circuit units are used, the vending (start) signal T
Even if the product selection signals SEL, SEL2 are not received, the corresponding control circuit unit is automatically cleared in preparation for the next sale, which not only helps to standardize the control circuit unit, but also prevents the product from interfering with sales. Sales control can be carried out accurately without any problems.

The above operations of the present invention are not limited to coins, for example,
Of course, this method can also be applied to items using 000 yen and 500 yen banknotes and IOO yen coins.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an electronic control circuit for a vending machine according to the present invention, and FIGS. 2 and 3 are circuit diagrams of an embodiment of the present invention. 1...Encoder, 2...Adder/subtractor,
3...Shift register for total payout,
4・・・・・・¥50 number register, 5・・・・・・¥
100 number register, 6...K≧50 comparator, 7...P1+90 adder, 8...
・P, +50 adder, 9...P2+90 adder, 10...P2+50 adder, 11...
・Comparator for P1, 12...Comparator for P2, 13...P1 price setting circuit, 14...
...P2 price setting circuit, 15...Bend control circuit for P1, 16...Bend control circuit for P2, 17...Coin payout control circuit, 18...・
... Coin jam detection circuit, 19 ... Refund latch circuit, 20 ... Brother movement refund circuit, 21 ...
... Select latch circuit, 22 ... CREM control circuit, 23 ... Two-phase clock pulse generation circuit, 24 ... Bit pulse generation circuit, 25 to 27
．． 37.49-53,55,57,59,62-66.
6B, 70, 73, 74, 77, 102, 106, 10
8,113,116,119,121 ,123,12
5,129,131-133,141 ,142,14
6,151,155,158...AND circuit, 28-31,38,40,44,46,54,5B
,67,69,71 ,76,80~B2,95,10
3～105,107,114,117.120124,
134,135,145,152-154,157...
...OR circuit, 32-35.83-94, 98-1
0L111, 112, 130, 137, 156...
...NAND circuit, 42, 61, 118, 1 22
, 126 , 148, 1 59...NOR circuit, 36, 41 , 43, 56, 60, 72, 75.7 &
79, 96, 97, 109, 110, 115, 127,
128,136,138-140,143,147,1
49,150,160-162... Inverter circuit, 39,163... Cycle timer, De
lay1 ~Delay4...Delay circuit, FF
1 to FF4 FF1, to FF18...Flip-flop circuit, COPM1 to COPM,...Comparator, WO1 to WO15...Wired OR circuit, WA1 to WA3゜゜゛...Wired AN
D circuit, SR,, SR2...Two-phase dynamic shift register, R1, R2...Register, F
A1 to FA4...Full adder, PRICEt,
2... Product setting price, POS... Coin payout confirmation signal, ATPO... Crying refund signal,
PO...Refund input, A1...YIO no change signal, A2...¥50 no change signal, B
１・・・・・・Coin payout signal, B2・・・・・・￥
50 coin payout signal, T...Sale signal, VE
ND12...Sale ready signal, ESC-RTRN
'・・・Coin refund signal in escrow, ESC-AC
C...Goin collection signal in escrow, EXT-
CL...External clear signal, SING...
・Price setting number selection signal, ■... Coin input signal, ■... Refund signal, ■... Shift register SR2 memory content existence signal, ■... X>P1
Signal, ■...X>P1+90 signal, ■...
・・X1P1 signal, ■・・・Auto clear signal AC
L, ■...X>P2 signal, ■...X>
P2+90 signal, ■...X=P2 signal, ■...
...P1-0 signal, ■...P2-0 signal,
e...Select signal SEL, ■...Select signal SEL ■...Select signal SEL
2,■・・・・・・Electronic control circuit operation signal for coin pick, ◎・・・・・・￥10 coin payout signal, [F]・
...X=P1+50 signal, ■...X=P
2+50 signal, SEL1SEL2...Select input signal, CREM...Coin insertion prevention signal,
t1~t7...Bit pulse, φ1, φ2, φ
3...Clock pulse.

Claims (1)

[Claims] 1. A control circuit that is capable of setting a plurality of prices, and has a function of comparing the input amount with each of these multiple set prices and sending out a sales enable signal for each set price at which the input amount exceeds the set price. In a control circuit for a vending machine comprising a plurality of units, each control circuit unit is configured to control only that unit on the condition that a product selection signal does not arrive even though a sales signal from the vending machine body arrives. A control circuit for a vending machine, characterized in that it includes a circuit that forms an automatic clear signal.