JPS598868B2 - Control circuit for vending machines - Google Patents

Description

[Detailed Description of the Invention] The present invention uses an electronic circuit to calculate the input amount, change, and return money in a vending machine, and to control the acceptance or return of input coins, the sending of a sellable signal, etc. Related to electronic control circuits for vending machines.

This type of electronic control circuit generally performs the following functions: (a) Counting the number of coins for each denomination (denomination) Accumulating the amount of money inserted (c) Setting and reading the product selling price (set price) (d)
Calculating the amount of change (input amount - product sales price) (e) Returning the inserted money at the time of cancellation and storing the input amount at the time of sale (f) Sending the sales ready signal (g) Selection signal and sales signal (vending machine It has arithmetic control functions such as (a signal indicating that a coin has entered a selling operation), (h) control of a return mechanism that returns the inserted coins as they are, and so on.

Among these, regarding setting and reading of product sales prices, as products and their sales prices become more diverse, it is desired to be able to set multiple prices with one control device.
In addition, product sales prices have been forced to change frequently due to price fluctuations since last year's oil shock, and this coupled with the spread of vending machines means that many people have no knowledge of the operating mechanisms of vending machines. It is desired that even a person can easily set or change prices.

However, the most common vending machine control mechanism on the market (so-called coin knock) is
When setting the selling price of a product, it is mandatory to set a specific setting part among multiple price setting parts as the highest selling price. Although this brings advantages to the manufacturer of the coin knock, it does not affect the user's side. This brought about an inconvenience that was often overlooked by manufacturers.

In other words, for the coin knock manufacturer, if there is an assumption that the maximum selling price is set in a specific setting section, it may be necessary to detect that the input amount has reached the upper limit, or to install an electromagnet for the immediate return of input coins.
Since control such as turning off the excitation of the magnet (commonly known as CREM) can be executed based only on the set price of the specific setting section, the advantage is that the circuit can be easily assembled.

However, for the general public, especially for users who are not familiar with the control operations of vending machines, such price setting restrictions are complicated, and if they are set incorrectly, it may become impossible to sell a specific product.

For example, if there are products priced at 50 yen, 60 yen, 70 yen, and 80 yen, you may mistakenly set 70 yen in the maximum selling price setting section, and set 50 yen, 60 yen, and 80 yen in the other setting sections.
If 0 yen is set, when 70 yen is inserted, the machine determines that the input amount has reached the maximum set price, de-energizes the electromagnet CREM, and prevents the next 10 yen coin from being inserted. Therefore, you will no longer be able to purchase products that cost 80 yen.

In order to eliminate this inconvenience, it is necessary to be able to set prices without distinguishing between high and low prices.

By the way, in conventional commercially available devices, the following additional restrictions have been set regarding price setting.

In other words, if any one of the multiple set prices is set to 0 yen, the electromagnet CRE
M was de-energized and did not accept any input coins.

For this reason, for example, in a device that can set 5 prices, if there are only 2 types of product sales prices at that time, the remaining 3 price setting sections may be set to match the lower product sales price, or It is necessary to take a method such as setting the maximum price for the device, which is not only complicated, but also has the disadvantage that it cannot deal with the following cases.

In other words, when a situation arises in which one of several products must be discontinued and recalled for some reason, the simplest method is to first set the set price of the product to 0 yen (if the set price is 0 yen). With yen, even if you do not insert money, the input amount = the set price, which means that you can purchase the product for free.Normally, a sellable signal is not sent under this condition.)If you do this, This means that sales of the product can be stopped immediately without waiting for time-consuming collection work, but with conventional devices, other products cannot be purchased in this case.

Incidentally, there is usually no special switch that can selectively stop sales of certain products.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a control circuit for a vending machine that can stop the sale of a given product and continue selling other products without making a distinction between high and low prices. There is a particular thing.

According to the present invention, the above object is to provide a price setting means capable of setting a plurality of prices, and to compare the input amount with the input amount for each of the plurality of prices set in the means, and the input amount is equal to or higher than the set price. A control circuit for a vending machine having means for sending a sellable signal for a set price, detects when any price setting of the setting means is ``0'' and sends the sellable signal for the set price. and all price settings of the setting means are ``0''.
This is achieved by providing a means for detecting this and forming a coin insertion prevention signal when this occurs.

Embodiments of the present invention will be described below with reference to the drawings.

In addition, in the example, the currency is ¥10, ¥50, ¥
Consider a case using 100 various coins.

FIG. 1 shows a block diagram illustrating the operation of a device according to the invention.

In the figure, 1 is the encoder, 2 is the adder/subtractor, 3 is the shift register for total payout, 4 is the Y50 number register, 5 is the ¥100 number register, 6 is the change amount K and Y5
K≧50 comparator that compares with 0, 7 is a P1+90 addition circuit that adds Y90 to the product setting price P1, 8 is a P1+50 addition circuit that adds Y50 to the product setting price P1, 9
is a P2+90 addition circuit that adds Y90 to the product setting price P2, and 10 is a P2+5 addition circuit that adds Y50 to the product setting price P2.
0 addition circuit; 11 is a comparator for product setting price Pl that compares the input amount with P1, P, +50, and P1+90; 12 is a comparator for product setting price P2 that compares the input amount with P2 and P2+50 and P2+90; P1 price setting circuit for setting product setting price P1; 14 is P for setting product setting price P2;
2 price setting circuit; 15 is a bend control circuit for P1 that controls the sale of a product with a set price P1 based on the output of the comparator 11 for P1; 16 is a bend control circuit for controlling the sale of a product with a set price P2 based on the output of the comparator 12 for P2; 17 is a coin payout control circuit, 18 is a coin jam detection circuit, 19 is a refund latch circuit, 20 is an automatic refund circuit, 21 is a select latch circuit, 22 is a CR
EM control circuit (described later), 23 is a two-phase clock pulse generation circuit, and 24 is a bit pulse generation circuit.

In addition, A1 is the change ¥10 missing signal, A2 is the change Y50 missing signal, B1 is the coin payout signal, B2 is the Y50 coin payout signal, VBND1 is the P1 product sales ready signal, VEN
D2 is the P2 product sales enable signal, POS is the coin payout confirmation signal, PO is the manual refund input, SEL1 is the product set price P
Select input of product 1, SEL2 is product setting price P2
Product selection input, t1 to t7 are bit pulses, E
SC-ACC and ESC-RTRN are ¥ in escrow
100 coin collection signal and refund signal are shown.

Terminals 1 to 2 and T correspond to those in FIG.

In the example, “1” in the decimal system is ¥1.
It is expressed as a 6-bit pure binary number that represents 0.

If the coins used here are YIO, Y50, and ¥100, then YIO is "000001" and Y50 is "0".
00101'' and ¥100 are respectively represented by the binary code of ``001010''.

Therefore, the maximum selling price when using 6 bits is 63
The maximum selling price can be increased by increasing the number of bits.

The operation of the electronic control circuit for a coin knock in a vending machine according to the present invention will be explained in detail based on the block diagram shown in FIG.

YIO, each time a coin of ¥50 x ¥100 is inserted, the inserted coin is converted by the encoder 1 into a binary code representing the amount as described above and applied to the adder/subtractor 2, and then to the shift register 3 for total payout. This is added to the previously stored input amount and the total input amount is stored in the total payout shift register 3.

The total payout shift register 3 is shifted by two-phase clock pulses.

At this time, the ¥100 coin is temporarily held in a space called escrow, and the ¥10 x ¥50 coins are automatically stored in their respective change cylinders.

Moreover, each time a coin is inserted for Y50XYIOO coins, the person's capulse is sent to the Y50 coin number register 4 and the YIOO coin number register 5, and the respective inserted numbers are stored.

If a coin is jammed when inserting a coin, the coin jam detection circuit 18 detects the coin jam;
Coin return magnet (Coin) that returns inserted coins as is.
Return Electromagnet. It has a function of sending the signal to the control circuit of CREM (hereinafter referred to as CREM) and preventing the insertion of coins.

Here, coin jam is a state in which coins are jammed and the coin input signal is output in a continuous manner.

The product price is expressed in a 6-bit pure binary binary code in which "'1" in the decimal system represents ¥10.

In the present invention, one vending machine coin knock electronic control circuit is provided with a P1 price setting circuit 13 and a P2 price setting circuit 14 for setting two product prices P1 and P2. To obtain a multi-price vending machine by making it possible to sell products with two different prices in an electronic control circuit for knocking, and installing a plurality of electronic control circuits for coin mechs in one vending machine. I can do it.

In this case, the values of P1 and P2 are P,,P
2 must be larger, but in the present invention, P1>P2,P
Any setting such as 1=P2, P1 minus P2 is possible.

In addition, in the present invention, it goes without saying that a product setting price of "0" means "000000" in the case of 6 bits.

Among the 6-bit pure binary binary codes set in the P1 price setting circuit 13 and P2 price setting circuit 14, the binary code of P1 is P1+50 addition circuit 8 and P1+90.
In addition circuit 7, the binary code of P2 is applied to P2+50 addition circuit 10 and P2+90 addition circuit 9.

In addition, a bit pulse of t1+t3, ie, ``000101'' representing Y50 is applied from the bit pulse generating circuit 24 to the P1+50 adder circuit 8 and the P2+50 adder circuit 10, and addition of P1+5 0 and P2+50 is performed.

In addition, an 11+14 bit pulse, ie, "001001" representing Y90, is applied from the bit pulse generating circuit 24 to the P1+90 adding circuit 7 and the P2+90 adding circuit 9, and the addition of P1+9 0 and P2+9 0 is performed.

The hit-hals generation circuit 24 generates a two-phase clock pulse φ1.
, φ2, and generates bit pulses from t1 to t7 in a clock pulse period, of which the bit pulses from t1 to t6 are used to represent the amount of money.

Product setting price P 1 t P 1 +5 0 t P
1+9 0, the total input amount X stored in the shift register 3 for total payout is the product setting price P1
In the comparator 11, the product setting price P2, P2+50
, P2+90, the total input amount X is the product setting price P2
X=P from the comparator 11 for product setting price P1 as the comparison result
, X>P1, X>P1+ 9 0 , 1 X=P, +50, comparator 12 for product setting price P2
From X=P2,X>P2,X>P2+90,X=P2+
50 outputs can be obtained.

Here, if the product setting price is "0", the input amount is 0.
It should be noted that in the case of a circle, X=P1 or X=P2 holds true.

The length from the comparator 11 for the product setting price P1 is P1
The output from the product setting price P2 comparator 12 is applied to the P2 bend control circuit 16, respectively.

P1t P2ff bend control circuit 15.16 also has change Y10 no change signal A1, change Y50 no change signal A2
has been added.

In the embodiment, bend control circuits 15, 1 for P1 and P2
P1, P2 products available for sale from 6 ■END1, ■E
ND2 is issued at the next Jotani.

1) X=P1orP2 (However, P1(O or P2\O
) (7E case ii) P, <X≦P 1 + 9 0 or P 2
If <x≦P2+90 and there is Y10 change, 111) If X=P1+50orX=P2+50 and there is ¥50 change, then with the conventional device, even if there is Y50 change,
If there was no IO change, sales that required change were not performed, but in the device of the embodiment, the number P + 50, which is the sum of the product setting prices P1 and P2 and Y50,
By comparing P2+50 with the total input amount l amount X, even if there is no change for YIO, it is possible to sell when there is change of ¥50 and the amount of change is Y50.

When the customer selects either the product with the P1 price or the P2 price, the select latch circuit 21 is operated manually by SEL1,
Or SBL2 is sent and select latch circuit 2
1 to determine whether to select the product with the product setting price P1 or the product with the product setting price P2, and select SEL or S.
Almost at the same time as EL2 1) Signal E to collect the ¥100 coin temporarily stored in the escrow due to the external sales signal T.
Send SC-ACC to escrow.

Next, the output signal of the select latch circuit 21 is sent to the P1 price setting circuit 13 when SEL1 is selected, and to the P2 price setting circuit 14 when SEL2 is selected, depending on whether S-EL1 or SEL2 is selected. It will be done.

When the P''1 price setting circuit 13 and the P2 price setting circuit 14 receive the output signal of the select latch circuit 21, they send a binary code representing the product setting price to the adder/subtractor 2.

In the adder/subtractor 2, the set price sent from the P1 price setting circuit 13 or the P2 price setting circuit 14 is subtracted from the input total amount X stored in the total payout shift register 3 at this time.

That is, subtraction of X-P1 or X-P2 is performed, and the subtraction result K is stored in the total payout shift register 3 as the change amount.

This stored content K indicates the amount of change.

That is, the total payout shift register 3 functions as a change register.

The stored contents K of the total payout shift register 3 are sent to a K≧50 converter 6, and compared to see if the change amount K is larger than 50 yen.

K≧50 Comparator 6 receives t1+ as Y50 signal
The bit pulse of t3 is P1+50 addition circuit 8 and P2
It is added in the same way as the +50 adder circuit 10.

K≧50 The output signal of the comparator is sent to the coin payout control circuit 17.

The coin payout control circuit 17 also receives as inputs a Y50 no change signal A2, a change amount K1 stored in the total payout shift register 3, an output signal representing the number of ¥50 coins inserted into the number register 4, and a coin payout confirmation signal. POS has been added.

Coin payout signal B in coin payout control circuit 17
1. Change payout using the Y50 coin payout signal B2 is performed as follows.

j) If K<Y50...Pay out Y10Xn pieces (n<5) ii) If K>¥50 and there is Y50 change ・River...¥
Payout with 50 x 1 piece, ¥10 x n pieces (n<5) iii
) If K>Y50 and Y50 change is not available, song...¥10Xn
In the embodiment where coins are paid out (10>n>0), the amount of change is always less than Y90 because it is possible to sell only products for which the change is less than Y90 when a coin is inserted.

This means that the output signals from the P, comparator 11 and the P2 comparator 12 are X>P1+ 9 0 , X>
P1 bend control circuit 15 and P2+90
VEND, , VEND2 from the bend control circuit 16 for 2
This can be done by controlling the signals of

Each time a coin is paid out, the coin payout control circuit 17 receives a coin payout confirmation signal POS and sends a signal 2 representing the payout amount.
The decimal code is sent to the adder/subtractor 2, and the paid change is subtracted from the change amount K stored in the total payout shift register 3.

Then, when the change amount K stored in the total payout shift register 3 reaches "0", the payout of change is stopped.

However, if the amount of change is larger than Y50, the output signal of the K>50 comparator 6 causes the ¥50 change to be paid out first and the remainder to be paid out in YIO.

When performing a manual refund, a manual refund manual PO is added to the refund latch circuit 19, and if there is no selection signal within a certain period of time, a full refund will be made.

¥100 will be paid out from the escrow that was temporarily held,
Subtraction is performed from the total input amount X by the adder/subtractor 2 and the shift register 3 for total payout until the contents of the ¥100 coin count register 5, which stores the number of ¥100 coins inserted, becomes "0".

Similarly, the adder/subtractor 2 and the total payout shift register 3 subtract from the input amount X until the number of inserted coins stored in the ¥50 coin number register 4 becomes "O".

In this case, the output signals of the ¥50 number register 4 and the ¥100 number register 5 are converted into binary codes representing the respective amounts via the encoder 1 as shown in the block diagram of FIG. Subtraction is performed by unit 2.

After Y50 and ¥100 are refunded, YIO is refunded until the remaining memory contents of the total payout shift register 3 become "O".

The refund ends when the stored content of the total payout shift register 3 becomes "0".

In addition, if the input amount
0 and automatically sends a signal to the refund latch circuit 19 to issue a full refund.

At this time, the refund latch circuit 19 sends out the ESC-RTRN signal, and the Y50 sheet number register 4 and the ¥1
Sends a signal to the 00 sheet count register 5.

Further, if a coin is jammed, a sale signal is issued, or a refund is being made, the CREM control circuit 22 outputs a signal CREM to prevent coin insertion.

Other operating conditions of CREM will be described later.

The operation of the control circuit of the present invention based on the block diagram of FIG. 1 as described above will be more clearly illustrated by the description of the embodiment of the block diagram of FIG. 1 shown in FIGS. 2 and 3.

FIGS. 2 and 3 are circuits showing an embodiment for performing the operation of the block diagram of the present invention shown in FIG. 1. FIG.

The present invention will be explained in detail based on FIGS. 1, 2, and 3.

In FIGS. 2 and 3, the signals from ■ to ■ are signals within the electronic control circuit for coin knocking in the vending machine according to the present invention, and the other signals are electronic signals from devices in the vending machine other than this electronic control circuit. Either it is sent to the control circuit, or it is sent from the electronic control unit to other vending machine equipment.

The circuit illustrating the embodiment of the encoder 1 in FIG.
In the figure, AND circuits 25 to 27, 37, OR circuit 28
~31, 38, NAND circuits 32 to 35, inverter circuits 36, 41, cycle timer 39, wired OR
It consists of the circuit WO.

Initially, the symbol O indicating that the electronic control circuit for the coin knock of the vending machine according to the present invention is in operation is "099", so the AND circuits 25 to 27 are connected to the inverter circuit 41.
Since "1" is added, coin input ¥10, Y
If there is ¥50 or ¥100, AND accordingly.
An output "1" is produced in the circuits 25 to 27, and the output "1" is applied to the OR circuits 28 to 30, and the output "1" which is the same as the output of the AND circuits 25 to 27 is produced in the OR circuits 28 to 30. .

In addition, the NAND circuit 32 has a bit pulse of t1, NAND
The D circuit 33 has a bit pulse of t2, and the NAND circuit 34
A bit pulse of t3 is applied to the NAND circuit 35, and a bit pulse of t4 is applied to the NAND circuit 35 from the shift register SR1.

The shift register SR1 is shown as the bit pulse generation circuit 24 in the block diagram of FIG. 1, and is a two-phase dynamic shift register, and is shifted by two-phase clock pulses φ1 and φ2 to generate bit pulses from t1 to t7. Configure it to occur.

The outputs of the OR circuits 29-31 are applied to the NAND circuits 32-35 in addition to the bit pulses t1-t4.

By doing this, if there is a YIO coin input, this input will be converted to NAN via OR circuits 2B and 31.
Since it is applied to the D circuit 32, the output of the NAND circuit 32 is synchronized with the bit pulse of t1, so it is expressed as "111110" in a 6-bit binary number, and is inverted by the inverter circuit 36 via the wired OR circuit WO1 to become "0".
0 0 0 0 1” and II 1 jl is YIO
By expressing it as Y in pure binary system,
A binary code indicating the IO can be obtained.

Similarly, the coin input of Y50 is connected to the NAND circuit 32,
34, and in synchronization with the bit pulses at t1 and t3, the output of the inverter circuit 36 appears as ``000101'', that is, a binary code indicating Y50.

Also, ¥100 coin input is NAND1 circuit 33.35
"001010", that is, a binary code indicating Yl 00, appears at the output of the inverter circuit 36 in synchronization with the bit pulses at t2 and t4.

The output of the inverter circuit 36 is applied to an AND circuit 37, but a signal from a cycle timer 39 is also applied to the AND circuit 37.

The outputs of the OR circuits 28 to 30 are output to the cycle timer 39.
It is applied via the R circuit 38.

In other words, the cycle timer 39 outputs an output for a certain period of time when a coin of ¥10, ¥50, or ¥100 is input.
■It functions to send “” to the AND circuit 37.

The fixed time is generally one cycle time of bit pulses from t1 to t7.

Therefore, the output of the AND circuit 37 is only for one cycle time from 11 to t7, that is, the pulse representing the coin input of ¥10, Y50, and ¥100 is output from the output terminal of the AND circuit 37 only once. Double counting of coins does not occur.

A pulse representing the input amount from the AND circuit 37 is sent to the adder/subtractor 2 as shown in the block diagram of FIG.

The adder/subtractor 2 and total payout shift register 3 shown in the block diagram of FIG. 1 are comprised of the OR circuit 44, adder/subtractor ADD1 shift register SR2, and OR circuit 46 shown in FIG.

The adder/subtractor ADD performs addition or subtraction depending on the output of the inverter 43. A pure binary adder/subtractor with mode switching (for the detailed internal circuit, please refer to the
Please refer to Figures 5 and 8, page 176 of "Calculator Technology Textbook - Basic Edition" published by Radio Gijutsusha, August 15, 2006.

), and for the output from shift register SR2,
This is a type of addition or subtraction of the binary code signals given through the OR circuit 44 and the result is stored in the shift register SR2, but this may also be of a type in which the complement is taken and subtraction is performed. However, a well-known adder/subtractor can be used.

By doing this, when there is a coin input in the adder/subtractor ADD, the inverter circuit 43 outputs "0".
'' is added, the mode becomes addition mode, and the pulse representing the input amount from the AND circuit 37 is added in the adder/subtractor ADD and stored in the shift register SR2.

Shift register SR2 is a two-phase dynamic shift register shifted by two-phase clock pulses.

P1, P2 price setting circuit 1 in the block diagram of Fig. 1
3.14 is PRICE1, PRICE2 in Figure 2
terminals and NAND circuits 83 to 94, 98, 99,
Wired OR circuit WO~WO1, inverter circuit 96
．． Implemented by 97.

NAND1 of each terminal of PRICE1 and PRICE2
The terminals connected to circuits 83 and 89 are NAND circuits 8
Since terminals 3 and 89 are connected so that the bit pulse of t1 is applied, they have a weight of "'1", and the terminals that are similarly connected to the NAND circuits 84 and 90 are "'".
The terminals connected to NAND circuits 85 and 91 have a weight of 4, and the terminals connected to NAND circuits 85 and 91 have a weight of 4.
, 92 has a weight of "8", and the terminal connected to NAN
The terminals connected to the D circuits 87 and 93 have a weight of "16", and the terminals connected to the NAND circuits 88 and 94 have a weight of "3".
2" weight, and by giving a signal to any of the terminals of PRICE, the NAND circuits 83 to 8
Since the output of 8 is connected to the inverter circuit 96 via the wired OR circuits WO to W06, the output of the inverter circuit 96 is the inverted version of the outputs of the NAND circuits 83 to 88, and is a 6-bit signal representing the product setting price P1. Pure 2
A base binary code can be obtained as the output of the inverter circuit 96.

Similarly, the product setting price P2 can also be set by applying a signal to any of the terminals of PRICE2.

Of the product setting prices P1 and P2 obtained in this way, P1 is sent to the P1+50 addition circuit 7XP1+90 addition circuit 8, and P2 is sent to the P2+
The signals are sent to a P2+90 adder circuit 9 and a P2+90 adder circuit 10, respectively.

In FIG. 2, the portion consisting of the full adder FA1, the AND circuit 49, and the flip-flop circuit FF1 is the P1+90 addition circuit 7, and the portion consisting of the full adder FA2, the AND circuit 50, and the flip-flop circuit FF2 is the P2+90 addition circuit 9. The portion consisting of the full adder FA3, the AND circuit 51, and the flip-flop circuit FF3 is the P1+50 addition circuit 8, and the portion consisting of the full adder FA4, the AND circuit 52, and the flip-flop circuit FF4 is the P2+50 addition circuit 10.

Full adders FA1 and FA2 include a two-phase shift register S.
Of the bit pulses t1 to t7 generated by R1, t
The bit pulses of 1 and t4 are connected to be applied as the output of the OR circuit 81, so that the binary number "001001" representing 90 is added to the full adders FA1 and FA2, and the bit pulses from the full adders FA1 and FA2 are applied. is P1+90
Alternatively, the output of P2+90 can be obtained, and the binary number "000101" representing Y50 is similarly applied to the full adders FA3 and FA4 as the output of the OR circuit 80 based on the bit pulses of t1 and t3. P1+50 and P2+50 can be obtained.

The P1 comparator 11 in the block diagram of FIG. 1 is replaced by the comparators COMP2 to COMP,
Also, the comparator 12 for P2 is the comparator COMP6.
~COMF.

A 6-bit binary code representing the total amount of input coins X>P1
The signal ■ is obtained.

The total amount of coins inserted into the comparator COMM3 is set to 2
From the 6-bit binary code expressed in decimal notation and the full adder FA1 mentioned earlier, P1+90 is expressed in pure binary notation 6
A bit binary code is applied, and as a result of the comparison, a signal 0 with X>P1+90 is obtained.

The same input as the comparator COMP2 is applied to the comparator COMP, and the comparison result is X=P
1 signal ■ is obtained.

This signal? naturally occurs when P1=O and X=0.

The total amount of coins inserted into the comparator COMP,
A 6-bit binary code expressed in decimal notation and a 6-bit binary code expressed in pure binary notation from the aforementioned full adder FA3 are applied, and the comparison result is X=P1+50. Signal ■ is obtained.

For the product setting price P2, in the same way as for the product setting price P1, the signal ■ of X>P2 is sent from the comparator COMP6, and the signal 0 of X>P2+90 is sent from the comparator COMP7.
A signal (2) with X=P2 is obtained from the comparator COMP8, and a signal (2) with X=P2+50 is obtained from the comparator COMP8.

Signal ■ naturally occurs when X=0 and P2=0.

In this way, by comparing the input amount with several amounts based on the set price of the product, the comparison results obtained are used to control sales and change disbursement as described later.

Output signals of comparators ■MP2 to ■MP shown in Fig. 2 ■X>P1tQX>P1+9 0, ■X=P1,
■X=P1+50,■X>P2,OX>P2+90,■
X=P2, OX=P2+50 is NA as shown in Figure 3.
ND circuits 100, 101, ANI) circuits 102, 106
, 108, OR circuit 105, 107, inverter circuit 1
09, 110, P1 bend control circuit consisting of NOR circuit 118, flip-flop circuit FF1, or NA
ND circuits 111, 112, AND circuits 113, 116,
119, OR circuit 114, 117, inverter circuit 11
5,110, an NO short circuit 118, and a flip-flop circuit FF13.

Considering a product with set price P1, X=P1
At this time, the signal (2) with X=P1 is applied to the OR circuit 105, and the output of the OR circuit 105 becomes one input of the AND circuit 106.

The other input of the AND circuit 106 is the output of the OR circuit 82, that is, the signal ``P1=0'' is added, so when the product setting price P1 is not 0, ``'1'' is added, so the signal of X=P1 is If this occurs, the OR circuit 10
``'1'' is added to one of the two input terminals of the AND circuit 108 as the output of 7.

The other input terminal of the AND circuit 108 is the NOR circuit 11B.
is connected to the output terminal of

The two input terminals of the NOR circuit 118 are wired AN
Signals from D circuit WA3 and flip-flop circuit FF11 are sent.

Flipflots? As described later, the circuit FF11 allows the customer to select a product using a push button, etc., and selects SEL1 or SE.
The input from the flip-flop circuit FFH to the NOR circuit 118 is "0" because it is in a reset state until L2 and the SEL signal (■) indicating that the product has been sold or the refund signal (■) which occurs a little later than that occurs. .

The wired AND circuit WA3 has as inputs the output of the flip-flop circuit FF1 inverted by an inverter circuit 149, the output of the flip-flop circuit FF18 inverted by an inverter circuit 147, and the NAND circuit 1.
56 outputs are added.

When there is no refund manual PO, flip-flop circuit FF
1 is not set, the output of the inverter circuit 149 is "1", and when there is no sales signal T, the flip-flop circuit FF18 is not set, so the output of the inverter circuit 147 is "1".

The output of the flip-flop circuit FF17 and a signal SING are applied to the NAND circuit 156 as inputs.

SING has two product price setting circuits in the embodiment, so when only one product price setting circuit is used, the price setting number selection signal SING is set to "0".
, if two product pricing circuits are used, add "1" and so on.

Regardless of the state of the SING signal, when there is no sales signal T, the output of the NAND circuit 156 is "1".

Therefore, when there is no manual power PO to refund the sales signal T1, the output of the wired AND circuit WA3 is "1", and this output is inverted by the inverter circuit 160 and the NOR circuit 11
Add "0" as input of 8.

Therefore, if there is no sales signal T1 refund manual PO, NO
The output of the R circuit 118 is "1", and when the output of the OR circuit 107 becomes "1", the flip-flop circuit FF1
is set to generate a signal VEND1 indicating that the product with the P1 price can be selected, thereby allowing the customer to select the product with the P1 price.

The product with the product setting price P2 is exactly the same as the product with the product setting price P1, and the OR circuit 95
This is performed based on the signal 2=0, and a signal VEND,2 can be obtained from the flip-flop circuit FF13.

The above signal P1-0 or P2=0 is "1" when the product setting price P1 or P2 is "'0", that is, in 6 bits, [o O 0 0 0 0J? For example, if no price is set, ``0''
'', and in this case, as is clear from the figure, the AND circuit 106 or 116 is not established, so the flip-flop circuit FF1 or FF13 is not set, and the salesable ridge number VEND1 or ■END2 is not sent out.

Therefore, if any price setting is set to "0", the corresponding product will not be sold.

On the other hand, if the sellable signals ■END1 and ■END2 are issued, the vending machine displays a display indicating that the product with the product set price P1 or P2 can be selected based on vEND1 and ■END2. When the customer selects either one, a signal SEL1 or SEL2 is sent together with the sales signal T to the electronic control circuit device for the automatic vending machine coin knock according to the present invention.

That is, the sales signal T is a signal that the product has been sold.

In addition, if a coin is inserted that causes the signal ■ of X>P1, the signal ■ of x>p is output to the AND circuit 10.
In addition to 2, as other inputs of the AND circuit 102, X>P
1+90 signal ■ inverted by NOT circuit 109, Y50 hookless signal A2 inverted by NOT circuit 110, and X=P, +50 signal [F] are NA
NA obtained by adding the output of the ND circuit 100 to the NAND circuit 101 together with the YIO hookless signal A1
By adding the output of the ND circuit 101, X>
If P1 and X≦P1+90 and there is a hook of YIO, an output "1" is generated in the M...circuit 102, and the output is ORed.
By adding it to the circuit 105, the VEND1 signal can be obtained in the same manner as in the case where X=P1 described above.

Also, when X = P1 + 50, there is no hook coin for YIO and it costs ¥50.
If there is a hook coin, the NAND circuit 100 has "1"
Since "'1" is added to the output, the output is "'O", and the output "0" is added to the NAND circuit 101 along with "1" indicating that there is no YIO hook, so the output of the NAND circuit 101 is ""l", and X=P1+50 is X>
Since P1 and X≦P1+90 are satisfied, AND
Since all the inputs of the circuit 102 are "1", the above-mentioned X>
Similarly to the case of P, the signal of VEND can be obtained.

Regarding the product setting price P2, X>P2, X=P2+50
In the case c)), the output of ■END2 can be obtained by considering the product setting price P1 in the same way as in the case of the product setting price P1.

When the sales signal T is generated, the following occurs in the device of the embodiment.

The sales signal T is added as an input to an OR circuit 154, and O
The output of R circuit 154 is applied to AND circuit 155.

The output of a NOR circuit 159 which receives the outputs of flip-flop circuits FF16 and FF11 as inputs is also added to the AND circuit 155.

The output of the flip-flop circuit FF16 is "0" when the sales signal T is generated, and the output of the flip-flop circuit FF1 is "0".
When the output force is 0'', it remains at 0, so NOR
The output of the circuit 159 is "1", and therefore, the output "1" is produced in the OR circuit 154, thereby setting the flip-flop circuit FF17.

This output is l 0 0 m by the delay circuit pelay4.
AND circuit 158 as the output of OR circuit 157 after s delay.
added to.

Since "1" is added to the AND circuit 158 from the aforementioned NOR circuit 159 as another input, the OR circuit 157
The flip-flop circuit FF18 is set by the output of "1".

Receipt signal ESC of the ¥100 coin held in the escrow by the output of the flip-flop circuit FF18
- Generate ACC.

Also, the output N 1 of the flip-flop circuit FF18? 1
is added to the AND circuit 132 together with the SEL2 signal.

Since the SEL1 and SEL2 signals are generated almost simultaneously with the sales signal T, the flip-flop circuit FF18
When the output N 1 11 occurs, C is already SEL,
, SEL2 is AND circuit 131 or 132
has been added to.

Therefore, at the same time that the output "1" of the flip-flop circuit FF18 is generated, the output "1" is generated from the AND circuit 131 or 132.
1" is generated, and the output of the AND circuit 131 is the output of the AND circuit 14.
The inverter circuit 161 and the wired OR circuit W0.4 are directly connected to one of the two input terminals of 1, and the other terminal is connected to the inverter circuit 161 and wired OR circuit W0.
2 is applied via the WO 15, the inverter circuit 143, and the cycle timer 163.

By applying it to the AND circuit 141 via the cycle timer 163, the output of the AND circuit 141 becomes bit pulse 1.
It will occur only once every 1 to 17 intervals.

Similarly, the output of the AND circuit 132 is output from the AND circuit 142.
The NOT circuit 162 and the wired OR circuit WO1, NO are directly connected to one of the two input terminals of the
Since it is applied via the T circuit 143 and the cycle timer 163, the output of the ANI17 circuit 142 is the bit pulse t1.
Occurs only once in the interval ~t7.

Assuming that the output of the AND circuit 141 is the SBL1 signal ■, and the output of the AND circuit 142 is the SEL2 signal ■, the SEL1 signal ■ is applied to the NAND circuit 98 in FIG.

The NAND circuit 98 also has an inverter circuit 9 as an input.
Since the binary code representing the product setting price P1 is added from 6 to 6, the binary code representing the product setting price P1 is added by the SEL1 signal ■ to the wired OR circuit WO, 2, the inverter circuit 79, and the OR circuit 44. The signal is added to the adder/subtracter ADD via the subtracter ADD.

That is, since the SEL1 signal ■ is generated only once in the interval from t1 to t7, the output of the OR circuit 44 is a binary code representing the product setting price P1.

The adder/subtracter ADD has an inverter circuit 43 as another input.
When there is no coin input signal ■, since "1" is added, the subtraction mode is entered, and the adder/subtractor ADD subtracts the product setting price P1 from the total input amount X, and the bill hook amount K is stored in the shift register SR2. Ru.

The same is true for the product setting price P2, and SE
The L2 signal ■ is applied to the NAND circuit 99, and the rest is performed in the same way as the product setting price P1.

These hook coin amounts are calculated using the cycle timer 16 in Figure 3.
3, and when the output of the cycle timer 163 disappears, the output of the inverter 140 becomes "1".

The AND circuit 133 receives the output of the inverter 140, the SEL signal e which is already "1", and the shift register S.
Since the signal ■ which becomes n 1 u when the content of R2 is not 0 is given, the content of shift register SR2 (i.e. the hook amount) when the output of the cycle timer 163 disappears.
When is not 0, the AND circuit 133 outputs an output,
A coin payout signal B1 is issued via the OR circuit 134 to start the coin payout operation.

Next, the mechanism for dispensing hook coins will be explained.

The stored contents of the shift register SR2 representing the coin amount K obtained by subtracting the product setting price P1 or P2 from the input amount X are sent to the comparator COMP1, which indicates K≧50 comparator 6 in FIG. 1, and is compared with Y50.

The output of the comparator COMP1 is applied to an AND circuit 77, but the AND circuit 77 also receives, as other inputs, the Y50 hookless signal A2 inverted by an inverter circuit 78, and the SEL signal which is the output signal of the flip-flop circuit FF18. e has been added.

Therefore, if there is a Y50 hook coin and a product with a hook coin value of Y50 or more is sold, the output of the AND circuit 77 will be ``
1'' is generated, and the Y50 coin payout signal B2 is generated as the output of the OR circuit 76, and the above-mentioned coin payout is performed.

The output of the OR circuit 76 is added to the AND circuit 74,
The D circuit 74 receives a hook payout confirmation signal PO as another input.
S is added, and when a hook coin of 50 yen is paid out, an output "1" is generated in the AND circuit 74, and this output is ORed.
Y is added to circuit 29 in the same way as when inserting a coin.
It is converted into a binary code representing 50 and added to the adder/subtracter ADD, but at this time, the output of the inverter circuit 43, which is the other input of the adder/subtracter ADD, is input to the AND circuits 25 to 2.
Since the output of 7 is "0", it is "'1", so the adder/subtractor ADD is in subtraction mode, so the hook amount K and Y5 are
A subtraction of 0 is performed.

When the hook amount K becomes smaller than Y50, the output of the AND circuit 77 becomes "0" and "1" is added to the AND circuit 73 via the ZOR circuit 76 and the inverter circuit 75.

The same coin payout confirmation signal POS as the AND circuit 74 is added to the AND circuit 73;
Like the D circuit 74, each time a hook coin is paid out, the output signal "1" is sent to the OR circuit 281 to subtract YIO from the hook coin amount K.

To pay out the YIO hook coin, if the hook coin amount K stored in the shift register SR2 still remains after subtracting the Y50 hook coin, the OR circuit 46 sends the hook coin to the shift register SR.
Since the signal ■ indicating that the memory contents remain in 2 continues to be generated, the AND circuit 133 and the OR circuit 134 continue to output the coin payout signal B1, and the condition that this and the Y50 coin payout signal B2 have disappeared. This is done by

These are known techniques, and generally the signal B1 is given to the hook payout motor, and the signal B2 is given to the Y50, YIO switching solenoid.

Since Y50 hook coin payout has priority over YIO hook coin payout,
It becomes possible to pay out the minimum number of hook coins.

? Consider the case of refund.

First, we will discuss the case of manual refund.

The coin input signal ■ generated from the OR circuit 40 is the OR circuit 1
20 and the output of the OR circuit 120 is added to the AND circuit 12.
Added to 1.

The AND circuit 121 also has a NOR circuit 122 as an input.
The output of is added.

To the NOR circuit 122, the sales signal T and the SEL signal [phase] are added to the NOR circuit 148 and the output of the inverter circuit 150 obtained through the inverter circuit 150, so when the sales signal T is not present, the NOR circuit 122 Since the output of is "1", if there is a coin input signal ■, A
``1'' is generated at the output of the ND circuit 121, and the flip-flop circuit FF14 is set.

The output of flip-flop circuit FF14 is manual refund P.
It is added to the AND circuit 123 along with O.

Therefore, when a refund manual PO occurs, an output "1" is generated in the AND circuit 123 and is applied to the AND circuit 125 via the NOR circuit 124.

Since the input of the NOR circuit 126 to which the same input as the aforementioned NOR circuit 122 is added is added to the AND circuit 125 as another input, the output of the AND circuit 125 is added by adding the output "'1" of the OR circuit 124. The output becomes "1" and flip-flop circuit FF15 is set.

The output of flip-flop circuit FF15 is connected to delay circuit Del.
ay2 is applied to the AND circuit 146 via the OR circuit 145.

Since the output of the above-mentioned NOR circuit 148 is added to the AND circuit 146 as an input, when the SEL signal ○ is not generated, "191" is generated, so the AND circuit 146 outputs "1". , flip-flop circuit F
F16 is set and a refund signal ■ can be obtained.

By doing this, if the sales signal ■ occurs before adding the refund manual PO, the flip-flop circuit FF
14 is reset, so no refund signal is obtained, and even after the refund manual PO is applied, if the sales signal ■ or the SEL signal e occurs during the delay time of the delay circuit Delay2, the flip-flop circuit FF1 is activated. It is reset to give priority to the sales signal T and SEL signal e.

In addition, an automatic refund signal ATPO, which will be described later, is added to the terminal of the manual refund manual PO.

Automatic refunds will be made in the following cases:

That is, the output of the flip-flop circuit FF1 mentioned above is sent to the wired AND circuit WA1 via the inverter circuit 127, and the output of the flip-flop circuit FF13 is sent to the wired AND circuit WN via the inverter circuit 128.
In addition to 1, AND the output of the wired AND circuit WA,
Add to circuit 129.

Also, the signal ■ of X>P1 and the signal ■ of X=P are added to the OR circuit 103, the signal [present] of X>P2 and the signal ■ of The output of the OR circuit 104 is added to the wired AND circuit WA2, and the output of the wired AND circuit WA2 is added to the AND circuit 1.
Add to 29.

By doing this, wired AND circuit WA2
When inputting an amount greater than or equal to the maximum product price setting value, an output "1" is generated, and the output of the wired AND circuit WA1 is the flip-flop circuit FF12, F.
"1" occurs when the output of F13 is not occurring, and AN
An automatic refund signal ATPO is obtained by the D circuit 129.

That is, in the embodiment, if the sales outputs vEND1 and vEND2 do not occur even if coins are inserted to the maximum limit, a refund is automatically made.

This automatic refund signal ATPO is added to the manual refund manual PO described above, and the refund signal (2) can be obtained in the same manner.

Refunds are made in the following manner based on the refund signal (2) obtained in this manner.

In the embodiment, as shown in the block diagram of FIG.
For the insertion of 0 and YIOO coins, a Y50 number register 4 and a YIOO number register 5 are provided to count the number of coins inserted.

In other words, in Figure 2, the ¥50 number register is R1, ¥
The 100 sheet count register is indicated by R2.

Registers R, , and R2 sequentially set the flip-flop circuit each time an input is applied, and register R1 can count up to 15 Y50 coins, or 750 yen, and register R2 can count 8 coins (SOO). It is possible to count the number of coins inserted up to.

Y5 from the AND circuit 26 is input to the Y50 sheet number register R1.
The 0 coin input signal is being sent, and the Y50 coin input signal is being sent along with the output of the cycle timer 39.
In addition to the D circuit 53, t1, the output of the %AND circuit 53 is O.
It is added to the R circuit 54.

Cycle timer 3 every time there is a coin input signal of Y50
Since a signal is applied to the AND circuit 53 only during the bit pulse period of 9, t, to t7, the output pulse signal of the OR circuit 54 determines whether the Y50 coin will be processed. The number of sheets received is stored in the Y50 sheet number register R1.

Similarly, the ¥100 coin input signal from the AND circuit 27 is added to the ¥100 coin number register R2.

Furthermore, the ¥100 coin input signal is input to the cycle timer 39.
The output of the AND circuit 64 is applied to the OR circuit 67, so the OR
The ¥100 coin input signal becomes YI due to the output pulse of the circuit.
It is stored in the OO number register.

At the same time as the refund signal ■ is generated, a refund signal ESC/RTRN for the YIOO coin held in the escrow is issued, and the ¥100 coin held in the escrow is refunded.

Y50 number register R1 2 is OR circuit 58, ArJD circuit 59, inverter circuit 60, flip-flop circuit F
A circuit consisting of F6 is attached, and when the ¥50 coin input is added to the Y50 coin count register, it sets the flip-flop circuit FF, and when the stored content of the ¥50 coin count register becomes "0", the flip-flop circuit FF is set. Circuit F
By resetting F6, the stored contents of the ¥50 number register R1 can be determined based on the output of the flip-flop circuit FF6.

Similarly, the OR circuit 69 and A are connected to the ¥100 number register R2.
A circuit consisting of an ND circuit TO, an inverter circuit 12, and a flip-flop circuit FF7 is attached, and the contents of the ¥100 number register can be determined based on the output of the flip-flop circuit FF7.

When the refund signal (2) is generated, the refund signal (2) is applied to the AND circuit 66, and by adding the clock pulse ψ3 as another input to the AND circuit 66, the AND circuit 66 can obtain an output synchronized with the clock pulse ψ3.

An OR circuit T whose inputs are the output of the AND circuit 66, the ¥100 number register R2, and the flip-flop circuit FF7.
1 is added to the AND circuit 65, so when the output of the flip-flop circuit FF7 is "'1", that is, while the number of YIOO coins inserted is stored in the ¥100 number register R2, the AND circuit 65 Output to ″
1'' is generated and a pulse is given to the ¥100 number register R2 as the output of the OR circuit 67.
The memories of are sequentially moved toward the output end.

When a signal is output from the output terminal of the YIOO sheet number register R2, that signal is added to the AND circuit 68 together with the output of the AND circuit 65, and a signal is output from the output terminal of the ¥100 sheet number register R2, and the number of stored sheets of ¥100 is subtracted. The output ``'1'' generated from the AND circuit 68 is added to the OR circuit 30 each time the input amount is inputted, and the input amount X stored in the shift register SR2 is added to the output amount Subtract ¥100 from .

In this way, by sequentially subtracting the number of sheets stored in the ¥100 sheet number register R2, the stored contents of the \100 sheet number register R2 are emptied.

Since the memory contents of the ¥100 number register R2 become empty, the output of the OR circuit 71 becomes "0", and the NOR circuit 6
"0"' is added to one input of the inverter circuit 56, and "1" is added to the κ circuit 63 as the output of the inverter circuit 56.

The AND circuit 63 also receives as inputs a signal from the output end of the Y50 sheet number register, a refund signal (2), and a signal (2) from the OR circuit 46.

If Y50 is turned on, flip-flop circuit FF6 is set, so the output of NOR circuit 61,
Therefore, the output ◎ of the AND circuit 62 does not occur immediately, but the stored contents of the Y50 sheet number register R1 and the ¥100 sheet number register R2 are simultaneously moved toward the output terminal via the AND circuit 57 and the OR circuit 54. Therefore, the ¥50 number register R1 produces an output after a short period of time depending on the stored contents.

This output, on the one hand, resets the flip-flop FF6 via the inverter 60 to prevent further movement of the memory contents via the AND circuit 57, and also
The R circuit 61 generates an output and the AND circuit 62 generates the output ■.

The output of the Y50 sheet number register R1 is given to the AND circuit 63 on the other hand, and as a result, the AND circuit 63 outputs "'1
" is generated, and its output is applied to the OR circuit 76, and the Y50 payout signal B2 is generated as in the case of the Y50 hook payout described above.
and the coin payout signal B1 obtained through the OR circuit 134 in FIG.
A coin of 0 is paid out, and Y50 is subtracted from the memory contents of the shift register SR2 for total payout in response to the coin payout confirmation signal POS.

The coin payout confirmation signal POS is applied to the AND circuit 55, which also receives as input the signal from the output terminal of the Y50 number register R1 and the output of the inverter circuit 56, and the signal from the output terminal of the Y100 number register R2. If the memory content is empty and there is memory content in the ¥50 coin count register R1, an output "1" is generated in the AND circuit 55 every time the coin payout confirmation signal POS is received, and this output is O.
It is sent to the Y50 sheet number register R1 via the R circuit 54,
Y50 The stored contents of the sheet number register R1 are moved by one toward the output end.

This process is repeated until the stored contents of the Y50 sheet number register R1 become empty.

When the stored contents of the Y50 coin number register R1 become empty, the output "'1" of the AND circuit 63 disappears, and the payout of 50 coins ends.

When the stored contents of the Y50 sheet number register and the ¥100 sheet number register become empty, if the stored contents remain in the shift register SR2 and the OR circuit 46 generates the output ■, the AND circuit 62 still generates the output ◎. O because there is
The coin payout signal B1 continues to be outputted via the R circuit 134, and based on the condition that this and the ¥50 coin payout signal B2 disappear, YIO is performed in the same manner as when paying out hook coins.
Allow coins to be paid out.

Then, in the same way as when paying out hook coins in YIO, subtraction is performed from the shift register SR2 for total payout in response to the hook payout confirmation signal POS until the output ■ of the OR circuit 46 becomes "0", that is, the shift register SR
YIO coins are paid out until the memory contents of 2 become empty.

In the example, the ¥50 number register R1 and the ¥100
By providing the number register R2, in the case of refund, the same amount and combination of coins can be refunded.

In the embodiment, in order to deal with coin jams, when there is a coin input signal (2), the signal is input to the AND circuit 15
One is directly connected to the two input terminals of 1, and the other is connected to the delay circuit De.
1 a y 3, if the coin force ■ is still occurring even after the delay time, an output "1" is generated in the AND circuit 151, and this output is sent to the OR circuit 15.
3, the output "1" of the OR circuit 153 can prevent subsequent coin insertion.

However, the delay time of the delay circuit Delay3 is sufficiently long compared to the input signal time of the coin, and here it is 300
A value of mSeC is used.

According to this method? In case of a coin jam in which a coin input signal is generated even if the coin is inserted again after being interrupted, the insertion of coins can be prevented after a delay time.

In the embodiment, there are other cases in which the CREM is turned off (coin insertion inhibited state) as follows.

That is, the output "1'" is output to the wired AND circuit WA2 described above.
” occurs.

That is, when the input amount is equal to or exceeds the maximum product setting price, there is no need to insert any more coins, so further coin insertion is prevented.

Further, when the sales signal T is sent and when the manual refund manual PO1 automatic refund signal ATPO is sent, coin insertion is prevented.

This can be done by adding the output of the wired AND circuit WA2 and the outputs of the flip-flop circuits FF15 and FF1 of the sales signal T1 to the OR circuit 152, and adding the resulting outputs of the OR circuit as inputs of the OR circuit 153.
This can be implemented by performing CREM control using the output of the circuit 153.

Also, even when all price settings are "0", X-P1
, P2 is established, and the signals ■ and ■ are both "1"
”, and the outputs of the OR circuits 103 and 104 are both “1”.
'', an output is generated in the wired AND circuit WA2, and CREM is turned off in the same manner as above.

When an operation such as a sale, a coin withdrawal, or a refund is completed, the operation (hereinafter referred to as "clear") for transitioning the electronic control circuit for the vending machine coin knock to a state in preparation for the next sale is as follows. It will be held in

That is, the coin payout signal B1 is applied to the NAND circuit 137 via the inverter circuit 136.

The NAND circuit 137 also receives the refund signal ■ and SE as inputs.
It consists of three people: applying the L signal O to the OR circuit 135 and applying the output of the OR circuit directly and via the delay circuit Delay1.

Therefore, if there is no coin payout signal B1 and a refund signal ■ or SEL signal [phase] occurs, the delay circuit Delay
After a delay time of l, the output of the NAND circuit 137 becomes "0".

The delay time of the delay circuit Delayl is sufficiently long compared to other operating times of the apparatus of the embodiment, and a value of 2 seconds is used here.

The output of the NAND circuit 137 is wired OR circuit W01
Added to 3.

Wired OR circuit WO13? In addition, a signal that is not cleared externally EXT clear signal NAND circuit 1
30 outputs are added as inputs.

EX. The T clear signal is an internal automatic clear signal AC.
It is used when trying to obtain L, and is always ``1''
It is.

The NAND circuit 130 has the SEL signal e and the wire FOR
The outputs of circuits WO14 and WO15 are added,
Since the wired-OR circuit changes the output to "0" when any of the inputs becomes "0", it is EXT.
1NAND circuit 130 or 137 outputs
0''', a change in the output of the wired OR circuit W013 is applied to the inverter circuit 138, and the output of the inverter circuit 138 causes the flip-flop circuit FF to change.
11 is inverted, and an automatic clear signal ACL@ is obtained as an output to the inverter circuit 139 when the output power of the flip-flop circuit FF1 is 1''.

AC'L signal ■ is comparator COMP1~COMP9
is added to reset the comparators COMP1 to COMP.

As described above, the operation of the electronic control circuit for vending machine vending control of the present invention shown in FIG. 1 can be achieved by the embodiment shown in FIGS. By further increasing the two product price setting circuits shown and matching other circuits, it is possible to sell two or more products with different prices using one electronic control circuit for vending machine vending control.

Further, according to the present invention as described above, if the price setting of any of the price setting means that can set a plurality of prices is "0", the corresponding product is not sold. Since the insertion of coins is prevented when all price settings are "0", it is possible to control the suspension of sales, etc. using the price setting means.

The above operations of the present invention are not limited to coins, for example,
Of course, the present invention can also be applied to items using 000 yen and 500 yen banknotes and 100 yen coins.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a vending machine electronic control circuit of the present invention, and FIGS. 2 and 3 are circuit diagrams of embodiments of the present invention. 1...Encoder, 2...Adder/subtractor,
3...Shift register for total payout,
4・・・・・・¥50 number register, 5・・・・・・¥
100 number register, 6...X≧50 comparator, I...P1+90 adder, 8...
・P1+50 adder, 9...P2+90 adder, 10...P2+50 adder, 11...
... Comparator for P1, 12 ... Comparator for P2, 13 ... P1 price setting circuit, 14
...P2 price setting circuit, 15 ...P1
Bend control circuit for P2, 16...Bend control circuit for P2, 17...Coin payout control circuit, 18.
... Coin jam detection circuit, 19 ... Refund latch circuit, 20 ... Brother movement refund circuit, 21 ...
...Select latch circuit, 22...CRE
M circuit, 23...2-phase clock pulse generation circuit, 24...Bit pulse generation circuit, 25-27
．． 37, 49-53.55, 57, 59, 62-66,
68, 70, 73, 74, 77, 102, 106, 10
8,113,116,119,121,123,125
,129,131~1 33,1 41 ,142,1
46, 151, 155, 158...AND circuit, 28-31, 38, 40, 44, 46, 54, 58
,67,69,7L76,80~82,95,103~
105, 107, 114, 117, 120, 124, 1
34,135,145,152-154,157...
...OR circuit, 32-35.83-94, 98-10
1,111,112,130,137,156...
・・NAND circuit, 42 , 61 , 118, 122,
126, 148, 159...NOR circuit, 36
,41 ,43,56,60 ,72,75 ,78
,79,96,97,109,110,115,127
, 128, 136, 138-140, 143, 1 47
, 1 49 , 150 , 1 60-16
2...Inverter circuit, 39,163...
... Cycle times Delay1 to Delay4 - delay circuits FF1 to FF4, FF11 to FF18...
・Flip-flop circuit, COMP1~COMP9...
...Comparator, WO1 to WO15...
Wired OR circuit, WA1-WA3...Wired AND circuit, SR1-SR2...2-phase dynamic shift register, R1, R2...Register, FA1-FA4...・Full adder, PRI
CE, , 2... Product set price, POS...
・・・・Coin payout confirmation signal, ATPO・・・Motor refund signal, PO・・・Refund input, A1・・・・
... YIO no hook coin signal, A2... ¥50 no hook coin signal, B, ...... coin payout signal, B2...
...¥50 coin payout signal, T...Sale signal, ■END1,2...Sellable signal, E
SC-RTRN...Coin refund signal in escrow, ESC-ACC...coin collection signal in escrow, EXT-CL...external clear signal, S
ING...Pricing number selection signal, ■...
・Coin input signal, ■... Refund signal, ■...
...Shift register SR2 memory content presence signal, ■...
...X>P1 signal, ■...X>P1+90
Signal, ■...X=P1 signal, ■...Auto clear signal ACL, ■...X>P2 signal, ■
......X>P2+90 signal, ■...X-
P2 signal, ■...P1=0 signal, ■...
・p2=o signal, [phase]...Select signal SE
L, ■...Select signal SEL1, ■...
...Select signal SEL2, ■...Electronic control circuit operation signal for coin pick, ■...¥10 coin payout signal, ■...X=P1+50 signal, ■
・・・・・・X-P2+50 signal, SEL1, SEL2
...Select input signal, CREM...
Coin insertion prevention signal, t1 to t7...Bit pulse, ψ1, ψ2, ψ3...Clock pulse.

Claims (1)

[Claims] 1. A price setting means that can set multiple prices, and compares each of the multiple prices set in the means with the input amount, and sends a sales enable signal to each set price at which the input amount exceeds the set price. In the control circuit for a vending machine, the control circuit for a vending machine has separate means for transmitting, when the price setting of any of the setting means is "0", detecting this and transmitting the sales enable signal for the set price. A control for a vending machine, characterized in that the control comprises means for preventing the setting of money, and means for detecting when all price settings of the setting means are "0" and forming a signal to prevent money from being inserted. circuit.