JPS5911159B2 - Control circuit for vending machines - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic control circuit for calculating the input amount, change amount, and refund amount in a vending machine, sending out a sales enable signal, and other controls.

This type of electronic control circuit generally functions together with a money sorting mechanism and a change dispensing mechanism, and counts the multiple types of input coins sorted by the coin sorting mechanism by denomination, calculates the input amount, and calculates the input amount. When the product exceeds the product sales set price, a sales enable signal is sent to the vending machine itself.

On the vending machine itself, the pushbutton corresponding to the price at which the sale ready signal was sent is lit up, and when the customer presses the lit pushbutton, a sales start signal (hereinafter simply referred to as simply Also called a sales signal.

) and a selection signal indicating which price has been selected to the electronic control circuit.

The electronic control circuit receives these signals and controls the subtraction of the product sales price from the input amount and the payout of change.

When the return button is pressed, the electronic control circuit returns the same amount of currency as the input amount to the return slot.

Although the above-mentioned technology is widely known, the following problems arise because the signals from the vending machine itself, that is, the sales signal and the selection signal, are generally sent via relays. was.

In other words, with the diversification of products and product sales prices,
This type of electronic control circuit is required to be able to set multiple prices, and since the amount of change will naturally vary depending on the set price, any set price other than the selected set price will be promptly responded to. It is necessary to take steps to deal with the fact that it has not been selected, that is, to generate a clear signal or to block future calculation operations.

This is to avoid paying out too much or too little change due to the generation of erroneous signals or noise signals.

Here, the sales signal from the vending machine itself is issued in common for all set prices, whereas the selection signal is issued in response to a specific set price. The processing for the non-selected set price is as follows.
It turns out that this can be done using the condition that the selection signal does not arrive even though the sales signal arrives.

However, as mentioned above, the sales signal and the selection signal are sent through relays, so although they are generated almost simultaneously, there is a possibility that one of them will be issued later than the other due to the difference in operating time of each relay. be.

For this reason, it is good if the selection signal arrives before the sales signal, but if the selection signal arrives later than the sales signal, the selection signal does not arrive even though the aforementioned sales signal has arrived. This condition is satisfied even if it is only for a short time, and the process that indicates that the set price is not selected proceeds.

Once the vending machine itself sends out a sales signal, it executes the product sales operation completely independently, resulting in a situation where the product can be purchased but no change is dispensed.

Therefore, an object of the present invention is to provide an electronic control circuit for a vending machine that can avoid the occurrence of such a situation.

According to the present invention, the above object is to send a sales enable signal to a vending machine when a plurality of prices can be set and the input amount exceeds at least one of these set prices. and a control circuit for a vending machine that receives a sales start signal based on the sales enable signal and a product selection signal for purchasing the product from the vending machine and enables the sale of the product corresponding to the corresponding price, This is achieved by providing a delay circuit that delays the sales start signal so that even if the product selection signal arrives slightly later than the sales start signal, the product selection signal is not invalidated.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a coin sorting and change dispensing control mechanism called a coin knock will be described below with reference to the drawings.

In addition, in the example, the currency is ¥10, ¥50, ¥
Consider a case using 100 various coins.

FIG. 1 shows a block diagram illustrating the operation of a device according to the invention.

In the figure, 1 is an encoder, 2 is an adder/subtractor, 3 is a shift register for total payout, 4 is a ¥50 number register, 5 is a ¥100 number register, 6 is a change amount K and Y5
K≧50 comparator that compares with 0, 7 is a P1+90 addition circuit that adds Y90 to the product setting price P1, 8 is a P1+50 addition circuit that adds Y50 to the product setting price P1, 9
is a P2+90 addition circuit that adds Y90 to the product setting price P2, and 10 is a P,+5 that adds Y50 to the product setting price P2.
0 addition circuit; 11 is a comparator for product setting price P1 that compares the input amount with P1, P1+50, and P1+90; 12 is a comparator for product setting price P2 that compares the input amount with P2 and P2+50 and P2+90; 13 is a product setting P1 price setting circuit for setting price P1, 14 is P for setting product setting price P2
2 price setting circuits; 15 is a bend control circuit for P1 which controls the sale of a product with a set price P1 based on the output of the comparator 11 for P1; 16 is a bend control circuit for controlling the sale of a product with a set price P2 based on the output of the comparator 12 for P2; Bend control circuit for P2 to control, 17 coin dispensing control circuit, 18 coin jam detection circuit, 19 refund latch circuit, 20 automatic refund circuit, 21 select latch circuit, 22 CR
EM control circuit (described later), 23 is a two-phase clock pulse generation circuit, and 24 is a bit pulse generation circuit.

In addition, A1 is the change ¥10 missing signal, A2 is the change Y50 missing signal, B1 is the coin payout signal, B2 is the Y50 coin payout signal, VEND1 is the P1 product sales ready signal, VEN
D2 is a P2 product sales enable signal, POS is a coin payout confirmation signal, PO is a manual refund input, SEL1 is a product selection input with a product set price P0, SEL2 is a product set price P
2 product selection input, t1 to t7 are bit pulses,
ESC/ACC and ESC-RTRN indicate the ¥100 coin collection signal and refund signal in the escrow.

Terminals 1 to 2 and T correspond to those in FIG.

In the example, the amount is f + 1 1 in decimal notation.
It is expressed as a 6-bit pure binary number where 1 represents ¥10.

The coins used here are ¥10, ¥50, Yl 0
If it is 0, YIO is ``000001'' ¥50
is represented by a binary code of ``000101'', and Y100 is represented by a binary code of ``001010''.

Therefore, the maximum selling price when using 6 bits is 63
The maximum selling price can be increased by increasing the number of bits.

The operation of the electronic control circuit for a coin knock in a vending machine according to the present invention will be explained in detail based on the block diagram shown in FIG.

Each time a coin of YIO, Y50, or YIOO is inserted, the inserted coin is converted by the encoder 1 into a binary code representing the amount as described above, applied to the adder/subtractor 2, and stored in the shift register 3 for total payout. The total amount of input is added to the amount of input so far, and the total amount of input is stored in the shift register 3 for total payout.

The total payout shift register 3 is shifted by two-phase clock pulses.

At this time, the ¥100 coin is temporarily held in a space called escrow, and the ¥10 and ¥50 coins are automatically stored in their respective change cylinders.

For Y50 and YIOO coins, each time a coin is inserted, the person's capulse is sent to the ¥50 coin count register 4 and the ¥100 coin count register 5, and the respective inserted numbers are stored.

If a coin is jammed when inserting a coin, the coin jam detection circuit 18 detects the coin jam;
Coin return electromagnet (Coi) that returns inserted coins as is.
n Return Electromagnet. It has a function of sending the signal to the control circuit of CREM (hereinafter referred to as CREM) and preventing the insertion of coins.

Here, a coin jam is a state in which coins are jammed and a coin input signal is continuously output.

The product price is expressed in a 6-bit pure binary binary code in which "'1" in the decimal system represents ¥10.

In the embodiment, one vending machine coin knock electronic control circuit is provided with a P1 price setting circuit 13 and a P2 price setting circuit 14 for setting two product prices P1 and P2. To obtain a multi-price vending machine by making it possible to sell products with two different prices in an electronic control circuit for knocks, and installing a plurality of electronic control circuits for coin knocks in one vending machine. I can do it.

In this case, the values of P1 and P2 are
Some regulations state that one of 2 must be larger, but here P1>P2, P1-P2
, P1<P2 can be set.

Among the 6-bit pure binary binary codes set in the P1 price setting circuit 13 and P2 price setting circuit 14, the binary code of P1 is P1+50 addition circuit 8 and P1+90.
In addition circuit 7, the binary code of P2 is applied to P2+50 addition circuit 10 and P2+90 addition circuit 9.

In addition to the P1+50 addition circuit 8 and the P2+50 addition circuit 10, a bit pulse of t1+t3, that is, ``O O O 1 0'' representing ¥50, is sent from the bit pulse generation circuit 24.
1'' is added, P1-}-5 0, P2
An addition of +5 0 is performed.

P, +90 adder circuit 7 and P2+90 adder circuit 9 receive 11+14 from the crab hit pulse generating circuit 24.
""001001" representing the bit pulse of Y90
is added, and addition of P1+90 and P2+90 is performed.

The bit Hals generation circuit 24 generates a two-phase clock pulse φ1.
, φ2, and generates bit pulses from t1 to t7 in a clock pulse period, of which the bit pulses from t1 to t6 are used to represent the amount of money.

Product setting price P1j P1+5 0, P1+9 0
, the total input amount X stored in the shift register 3 for total payout is sent to the comparator 11 for the product setting price P1 as the product setting price P2 , P2 + 5 0 + P
2+90, the total input amount X is added to the product setting price P2 comparator 12, and as a result of the comparison, from the product setting price P1 comparator 11, X=P1,
X>P1, X>P1+90, X1P1+50, X−P2,
, X>P2+90, X-P2+50 can be obtained.

The output from the comparator 11 for product setting price P1 is P1
The output from the product setting price P2 comparator 12 is applied to the P2 bend control circuit 16, respectively.

In addition, a change ¥10 missing signal A1 and a change Y50 missing signal A2 are added to the bend control circuits 15 and 16 for P1 and P2.

In the embodiment, the bend control circuit 15.1 for P1 and P2
6 to P1, P2 product sales enable signals VEND1, VEN
D2 is issued under the following conditions.

1) For X-P10rP2, i! ) P1<X<P1+9 0 or P2<X<
If P2+90 has YIO change, i! ! ) X= P1+ 5 0 or X= P2+
5 0 with Y50 change In this way, with the conventional device, even if there is Y50 change, ¥
If there was no change for 10, sales that required change were not performed, but in the device of the embodiment, the number P1+50, which is the sum of the product setting prices P1 and P2 and Y50,
YI by comparing P2+50 with the total input amount X
Even when there is no change for O, there is change Y50, and sales can be made when the change amount is Y50.

When the customer selects either the product with the P1 price or the P2 price, the select latch circuit 21 is operated manually by SEL1,
Or SEL2 is sent and select latch circuit 2
1 to determine whether to select the product with the product setting price P1 or the product with the product setting price P2, and select SEL1 or SEL1.
A signal ESC-ACC for collecting the ¥100 coin temporarily stored in the escrow is sent to the escrow in response to an external sales signal T generated almost simultaneously with EL2.

Next, the output signal of the select latch circuit 21 is sent to the P and price setting circuit 13 when SEL1 is selected, and to the P2 price setting circuit 14 when SEL2 is selected, depending on whether SEL1 or SEL2 is selected. It will be done.

When the P1 price setting circuit 13 and the P2 price setting circuit 14 receive the output signal of the select latch circuit 21, they send a binary code representing the product setting price to the adder/subtractor 2.

In the adder/subtractor B, the set price sent from the P1 price setting circuit 13 or the P2 price setting circuit 14 is subtracted from the input total amount X stored in the total payout shift register 3 at this time.

That is, subtraction of X-P1 or X-P2 is performed, and the subtraction result K is stored in the total payout shift register 3 as the change amount.

This stored content K indicates the amount of change.

That is, the total payout shift register 3 functions as a change register.

The stored content K of the total payout shift register 3 is sent to a K≧50 comparator 6, and compared to see if the change amount K is larger than Y50.

K≧50 Comparator 6 receives t1+ as Y50 signal
The bit pulse of t3 is P1+50 addition circuit 8 and P2
It is added in the same way as the +50 adder circuit 10.

K≧50 The output signal of the comparator is sent to the coin payout control circuit 17.

The coin payout control circuit 17 also receives as inputs a signal A2 indicating ¥50 without change and a change amount K stored in the total payout shift register 3. An output signal representing the number of coins inserted into the Y50 coin number register 4 and a coin payout confirmation signal POS are added.

Coin payout signal B in coin payout control circuit 17
, Y50 coin payout) Change payout using signal B2 is performed as follows.

i) When K<Y50...Pay out ¥10 x n pieces (n<5) i1i) When K>Y50 and there is Y50 change...
・Payout with Y50 x 1 piece, ¥10 x n pieces (n<5
)iiD K>Y5 0 and ¥50 without change...
...Payout with YIO x n pieces (1 0)n)O)
In the example, when a coin is inserted, the change is Y9.
Since only products with a value of 0 or less can be sold, the amount of change must be Y90 or less.

This means that the output signals from the P1 comparator 11 and the P2 comparator 12 are X>P1+'9 0, X
> VEND1, VEN from P1 bend control circuit 15 and P2 bend control circuit 16 by P2+90
This can be done by controlling the signal I)2.

Each time a coin is paid out, the coin payout control circuit 17 receives a coin payout confirmation signal POS and sends a signal 2 representing the payout amount.
The decimal code is sent to the adder/subtractor 2, and the paid change is subtracted from the change amount K stored in the shift register 3 for total payout.

Then, when the change amount K stored in the total payout shift register 3 reaches "0", the payout of change is stopped.

However, if the amount of change is larger than Y50, the output signal of the K>50 comparator 6 causes the Y50 change to be paid out first and the remaining amount to be paid out in YIO.

When performing a manual refund, a manual refund manual PO is added to the refund latch circuit 19, and if there is no selection signal within a certain period of time, a full refund will be made.

¥100 will be paid out from the escrow that was temporarily held,
Subtraction is performed from the total input amount X by the adder/subtractor 2 and the shift register 3 for total payout until the contents of the ¥100 coin count register 5, which stores the number of ¥100 coins inserted, becomes "0".

The adder/subtractor 2 and the total payout shift register 3 subtract from the input amount X until the input number sHO'' stored in the Y50 coin number register 4 is reached.

In this case, the output signals of the Y50 sheet number register 4 and the ¥100 sheet number register 5 are converted into binary codes representing the respective amounts via the encoder 1 as shown in the block diagram of FIG. 2 performs subtraction.

After refunding Y50 and ¥100, the remaining memory contents of the total payout shift register disk 3 are tt O u
YIO refunds will be made until .

The refund ends when the contents of the total payout shift register 3 reach '1 0 11'.

In addition, if the input amount
0, and automatically sends a signal to the refund latch circuit 19 to refund the amount.

At this time, the refund latch circuit 19 sends out the ESC-RTRN signal, and the ¥50 sheet number register 4 and the ¥1
Sends a signal to the 00 sheet count register 5.

Further, if a coin is jammed, a sale signal is issued, or a refund is being made, the CREM control circuit 22 outputs a signal CREM to prevent coin insertion.

The operation of the control circuit of the present invention based on the block diagram of FIG. 1 as described above will be more clearly illustrated by the explanation of the embodiment of the block diagram of FIG. 1 shown in FIGS. 2 and 3.

FIGS. 2 and 3 are circuits showing an embodiment for performing the operation of the block diagram of the present invention shown in FIG. 1. FIG.

The present invention will be explained in detail based on FIGS. 1, 2, and 3.

In FIGS. 2 and 3, the signals from ■ to ■ are signals within the electronic control circuit for coin knocking in the vending machine according to the present invention, and the other signals are electronic signals from devices in the vending machine other than this electronic control circuit. Either it is sent to the control circuit, or it is sent from the electronic control unit to other vending machine equipment.

The circuit illustrating the embodiment of the encoder 1 in FIG.
In the figure, it consists of AND circuits 25-27, 37, OR circuits 28-31, 3B, NAND circuits 32-35, invert circuits 36, 41, cycle timer 39, and wire FOR circuit WO0.

Initially, the symbol ■ indicating that the electronic control circuit for the coin knock of the vending machine according to the present invention is in operation is ゛゜0', so the AND circuits 25 to 27 are connected to the inverter circuit 41.
Since ゜゜1″ is added, the coin human power YIO,
If there is ¥50 or ¥100, AN correspondingly
Outputs $1 1 11 are generated in D circuits 25 to 27, and the output "1" is added to OR circuits 28 to 30 and
~30 has the same output H as the output of AND circuits 25~27.
produces ilt.

Also NA. The NAND circuit 32 receives a t1 bit pulse, the NAND circuit 33 receives a t2 pit pulse, and the NAND circuit 33 receives a t2 pit pulse.
A bit pulse at t3 is applied to the circuit 34, and a bit pulse at t4 is applied to the NAND circuit 35 from the shift register SR1.

The shift register SR1 is shown as a bit pulse generation circuit 24 in the block diagram of FIG. 1, and is a two-phase dynamic shift register, and is shifted by two-phase clock pulses φ1 and φ2 to generate bit pulses from t1 to t7. Configure it to occur.

The outputs of the OR circuits 29-31 are applied to the NAND circuits 32-35 in addition to the bit pulses t1-t4.

By doing this, if there is a coin input of ¥10, this input will be converted to NAN via the OR circuit 28.31.
Since it is applied to the D circuit 32, the output of the NAND circuit 32 is synchronized with the bit pulse of t, so it is expressed as 1 1 1 1 1 0'' in a 6-bit binary number, and is sent to the inverter circuit via the wired OR circuit WO1. By inverting at 36 to become "000001" and expressing "1" in YIO, a binary code indicating ¥10 in pure binary system can be obtained.

Similarly, the coin input of Y50 is connected to the NAND circuit 32.
34 and synchronized with the bit pulses of t1 and t3, the output of the inverter circuit 36 is ``000101''.
', that is, a binary code indicating Y50 appears.

Also, ¥100 coin input is NAND circuit 33, 35
is added to the output of the inverter circuit 36 in synchronization with the bit pulses at t2 and t4.
A binary code indicating 0 appears.

The output of the inverter circuit 36 is applied to an AND circuit 37, but a signal from a cycle timer 39 is also applied to the AND circuit 37.

The outputs of the OR circuits 28 to 30 are output to the cycle timer 39.
It is applied via the R circuit 38.

That is, the cycle timer 39 functions to send an output ``1'' to the AND circuit 37 for a certain period of time when a coin of ¥10, ¥50, or ¥100 is input.

The fixed time is generally one cycle time of bit pulses from t1 to t7.

Therefore, the output of the AND circuit 37 only occurs during one cycle time from t1 to t7, that is, the pulse does not represent the coin inputs of ¥10, ¥50, and ¥100, and only one pulse is output from the output terminal of the AND circuit 37. Therefore, double counting of coins does not occur.

A pulse representing the input amount from the AND circuit 37 is sent to the adder/subtractor 2 as shown in the block diagram of FIG.

The adder/subtractor 2 and total payout shift register 3 shown in the block diagram of FIG. 1 are made up of the parts shown in FIG. 2, including an OR circuit 44, an adder/subtractor ADD, a shift register SR2, and an OR circuit 46. .

The adder/subtractor AI)I) is a pure binary adder/subtractor whose addition and subtraction modes are switched in accordance with the output of the inverter 43 (for detailed internal circuitry, see for example the one published on August 15, 1970). , ■Please refer to Figures 5 and 8, page 176 of "Calculator Technology Textbook - Basic Edition" published by Radio Gijutsusha.

), and for the output from shift register SR2,
This is a type of addition or subtraction of the binary code signals given through the OR circuit 44 and the result is stored in the shift register SR2, but this may also be of a type in which the complement is taken and subtraction is performed. However, a well-known adder/subtractor can be used.

By doing this, when there is a coin input in the adder/subtractor ADD, the inverter circuit 43 outputs "0".
'' has been added, the mode is set to addition, and the pulse representing the input amount from the AND circuit 37 is added in the adder/subtractor ADD and stored in the shift register SR2.

Shift register SR2 is a two-phase dynamic shift register shifted by two-phase clock pulses.

P,,P2 price setting circuit 1 in the block diagram of Fig. 1
3.14 is PRICE1, PRICE2 in Figure 2
and NAND circuits 83-94. 98,9
9. Implemented by wired OR circuits WO2 to WO,2 and inverter circuits 96 and 97.

Among the PRICE1 and PRICE2 terminals, the terminals connected to the NAND circuits 83 and 89 are the NAND circuits 83 and 89.
, 89 are connected so that the bit pulse of t1 is applied, so they have a weight of '1°', and the terminals connected to the NAND circuits 84 and 90 in the same manner are '2'.
'', and has a weight of NAND [Which terminal is connected to circuits 85 and 91?+4 91, and
The terminals connected to the circuits 86, 92 have a weight of "8", and the terminals connected to the NAND circuits 87, 92 have a weight of "8". The terminal connected to NAND circuit 93 has a weight of ゜゛16'', and the terminal connected to NAND circuit 88.94 has a weight of ``32''.
NA by giving a signal to any of the terminals of CE1
The outputs of ND1 circuits 83 to 88 are wired OR circuit W0
2 to W06, the output of the inverter circuit 96 is NAND [circuit 83
It is the inverted output of ~88, and the product setting price P1
．． A 6-bit pure binary binary code representing , can be obtained as the output of the inverter circuit 96.

Similarly, the product setting price P2 can also be set by applying a signal to any of the terminals of PRICE2.

Among the product setting prices P1, P, 2 obtained in this way, P1 is P1+5 as shown in the block diagram of FIG.
0 addition circuit 7, P1+90 addition circuit 8, and P2 is connected to P
The signals are sent to a 2+50 adder circuit 9 and a P2+90 adder circuit 10, respectively.

In FIG. 2, the portion consisting of the full adder FA1, the AND circuit 49, and the flip-flop circuit FF1 is the P1+90 addition circuit 7, and the portion consisting of the full adder FA2, the AND circuit 50, and the flip-flop circuit FF2 is the P2+90 addition circuit 9. The portion consisting of the full adder FA3, the AND circuit 51, and the flip-flop circuit FF3 is the P1+50 addition circuit 8, and the portion consisting of the full adder FA/AND circuit 52 and the flip-flop circuit FF4 is the P2+50 addition circuit 10.

Full adders FA1 and FA2 include a two-phase shift register S.
Of the bit pulses t1 to t7 generated by R1, t
The bit pulses of 1 and t4 are connected to be applied as the output of the OR circuit 81, so that the full adders FA1 and FA2 receive the binary number ``O O 1 0 0'' representing 90.
1'' is added, and an output of P1+9.0 or P2+90 can be obtained from the full adders FA and FA2.

Also, in the full adders FA3 and FA4, the bit pulses of t1 and t3 are used as the output of the OR circuit 80.
By applying the binary number "O 0 0 1 0 1" representing 50, P1+50 and P2+50 can be obtained as the output.

The comparator 11 for P1 in the block diagram of FIG. 1 is the comparator COMP2 to COMP5 in FIG.
Also, the comparator 12 for P2 is the comparator COMP6.
This is the part consisting of ~COMP9.

A 6-bit binary code representing the total amount of input coins X>P1
The signal ■ is obtained.

? The total amount of coins inserted into the comparator COMP3 is 2
From the 6-bit binary code expressed in decimal notation and the full adder FA1 mentioned earlier, P1+90 is expressed in pure binary notation 6
A bit binary code is applied, and as a result of the comparison, a signal (2) with X>P1+90 is obtained.

The same input as comparator COMP2 is applied to comparator COMP4, and the comparison result is X-P
1 signal ■ is obtained.

The total amount of coins inserted into the comparator COMP,
A 6-bit binary code expressed in decimal notation and a 6-bit binary code expressed in pure binary notation from the full adder FA3 mentioned above are applied, and the comparison result is X=P1+50. Signal ■ is obtained.

For the product setting price P2, in the same way as for the product setting price P1, the signal ■ of X>P2 is sent from the comparator COMP6, and the signal ■ of X>P2+90 is sent from the comparator COMP7.
A signal (2) of X-P2 is obtained from the comparator COMP8, and a signal (2) of X-P2+50 is obtained from the comparator COMP9.

In this way, sales and change disbursements are controlled using the comparison results obtained by comparing the input amount with several amounts based on the product's set price, as will be described later.

Output signals of comparators COMP2 to COMP shown in Fig. 2 x>p1, x>p1+90, x-p1
, ■X=P1+50, ■X>P2, ■X>P290,
■X-P2, ■X-P2+50 is N as shown in Figure 3.
AN Roji 1 00 , 1 01 , AND circuit 102 ,
P1 bend control circuit consisting of 106, 108, OR circuits 105, 107, inverter circuits 109, 110, NOR circuit 118, flip-flop circuit FF1, or NAN circuits 111, 112, AND circuits 113, 11
6, 119, OR circuits 114, 117, inverter circuits 115, 110, NOR circuit 118, and flip-flop circuit WrFF13.

Considering a product with product setting price P1, X-P1
At this time, the signal (2) of X-P1 is applied to the OR circuit 105, and the output of the OR circuit 105 becomes one input of the ANI) circuit 106.

The other input of the ANI) circuit 106 is the output of the OR circuit 82, that is, the signals p, 1o are added, so when the product setting price p1 is not O, 1 is added, so the signal of X-P1 is What if it comes? adds “1” to one of the two input terminals of the AND circuit 108 as the output of the OR circuit 107.

The other input terminal of the AND circuit 108 is the NOR circuit 118
is connected to the output terminal of

The two input terminals of the NOR circuit 118 are wired AN
Signals from the D circuit WA3 and the flip-flop convex circuit FF11 are sent.

Flip-flop FF1, as described later, allows the customer to select a product by pressing a button, etc., and selects SEL1 or SEL2.
The input from the flip-flop circuit FF11 to the NOR circuit 118 is t+011 because it remains in the reset state until the SEL signal e or the refund signal (2) indicating that the product has been sold occurs, which occurs somewhat later.

The wired AND circuit WA3 receives as inputs the output of the flip-flop circuit FF1, which is inverted by an inverter circuit 149, the output of the flip-flop circuit FF18, which is inverted by an inverter circuit 147, and the output of a NAND circuit 156. .

When there is no refund manual PO, flip-flop circuit FF
1 is not set, the output of the inverter circuit 149 is "1", and when there is no sales signal T, the flip-flop circuit FF18 is not set, so the output of the inverter circuit 147 is "■".

The output of the flip-flop circuit FF1 and a signal SING are applied to the NAND circuit 156 as inputs.

SING has two product price setting circuits in the embodiment, so if only one product price setting circuit is used, "O" is used as the price setting number selection signal SING.
, if two product pricing circuits are used, add "1" and so on.

Regardless of the state of SINC4, when there is no sales signal T, the output of the NAND circuit 156 is "1".

Therefore, when there is no manual power PO to refund the sales signal T1, the output of the wired AND circuit WA3 is "1", and this output is inverted by the inverter circuit 160 and the NOR circuit 1
Add "0" as input of 18.

Therefore, if there is no sales signal T1 refund manual PO, NO
The output of the R circuit 118 is "1", and when the output of the OR circuit 107 becomes "1", the flip-flop circuit FF1
2 to generate a signal VEND, which indicates that the product with the P1 price can be selected, to enable the customer to select the product with the P1 price.

The product with the product setting price P2 is exactly the same as the product with the product setting price P1, and the OR circuit 95
This is performed based on the signal 2-0, and a signal END2 can be obtained from the flip-flop circuit FF13.

Based on this VEND1 and VEND2, a display is displayed on the vending machine indicating that the customer can select the product with the product set price P1 or P2, and when the customer selects either one, a signal SEL1 or SEL2 is sent to the sales signal T. It is also sent to the electronic control circuit device for the automatic vending machine coin knock according to the present invention.

That is, the sales signal T is a signal that the product has been sold.

Furthermore, if a coin is inserted that causes the signal ■ of X>P, the signal ■ of X>P1 is output to the AND circuit 10.
2 and as the other input of the AND circuit 102
The P1+90 signal ■ is inverted by the NOT circuit 109, the ¥50 no change signal A2 is inverted by the NOT circuit 110, and the signal [F] of X=P1+50 is NA
NA obtained by adding the output of the ND circuit 100 to the NAND circuit 101 together with the YIO no change signal A1
By adding the output of the ND circuit 101, X>
If P1 and X≦P1+90 and there is change of YIO, the AND circuit 102 generates an output "1"', and by adding that output to the OR circuit 105, the above-mentioned X=P
The VEND signal is obtained in the same manner as in case 1.

Also, when X = P1 + 50, there was no change for YIO and it was ¥50.
If there is change, the NAND circuit 100 has ``'1''.
” and “1” are added, so the output is “0”,
Since the output "0" is added to the NAND circuit 101 along with "1" indicating that there is no YIO change, the NAND circuit 10
1's output is 61'', and X=P1+50 satisfies X>P1 and X≦P1+90, so AND circuit 1
Since the inputs of 02 are all "1", the signal of VEND1 can be obtained in the same way as when x>p described above.

Regarding the product setting price P2, X>P2, X-P2+50
In this case, the output of VEND2 can be obtained by thinking in exactly the same way as for the product setting price P1.

The generation of the sales signal T causes the following to occur in the device of this embodiment.

Is the sales signal T added as an input to the OR circuit 154? Re, O
The output of R circuit 154 is applied to AND circuit 155.

The AND circuit 155 also has a NOR circuit 1 which receives the outputs of the flip-flop circuits FF16 and FF1 as inputs.
59 outputs are added.

The output of the flip-flop circuit FF16 is "091" when the sales signal T is generated, and the output of the flip-flop circuit FF1 is "091".
When the output of 8 is "0", it remains "0", so N
The output of the OR circuit 159 is "1", and therefore the output "1" is generated in the OR circuit 154, thereby setting the flip-flop circuit FF1.

This output is delayed by 100 ms due to delay circuit Delay4 and is applied to AND circuit 158 as the output of OR circuit 157.

This is the sales (start) signal T with Delay 4 of 100
This is to ensure that the SEL1 and SEL2 signals can be received by delaying by ms.

Since "1" is added to the AND circuit 158 from the aforementioned NOR circuit 159 as another input, the OR circuit 157
When "1" is generated as the output, the flip-flop circuit FF18 is set.

The receipt signal ESC- of the ¥100 coin held in the escrow is generated by the output of the flip-flop circuit FF18.
Generate ACC.

Further, the output n 1 u of the flip-flop circuit FF18 is sent to the AND circuit 131 together with the SEL1 signal, or
It is applied to the AND circuit 132 together with the SEL2 signal.

Since the SEL1 and SEL2 signals are generated almost simultaneously with the sales signal T, the flip-flop circuits FF and 8
When the output “1” occurs, it is already SEL1 or SEL
2 is added to AND circuit 131 or 132.

That is, when the AND circuit 131 or 132 is not established, the output of the NAND circuit 130 becomes ``0'' and is automatically cleared as described later, so in the present invention, the SEL
The AND circuits 131 and 132 are established by delaying the sales (start) signal T by a predetermined time by Delay4 so that the signal of 1 and SEL2 can be reliably received.

Therefore, at the same time the flip-flop circuit FF18 outputs "1", the AND circuit 131 or 132 outputs t!
1 11 occurs, the output of the AND circuit 131 is directly connected to one of the two input terminals of the AND circuit 141, and the other terminal is connected to the inverter circuit 161 and the wired OR circuit W.
It is applied via the inverter circuit 143 and the cycle timer 163.

By applying it to the AND circuit 141 via the cycle timer 163, the output of the AND circuit 141 becomes the bit pulse t.
, ~t7 will occur only once.

Similarly, the output of the AND circuit 132 is output from the AND circuit 142.
Directly connect one terminal of the two input terminals of
Since it is applied via the T circuit 143 and the cycle timer 163, the output of the AND circuit 142 is the bit pulse t, ~t.
Occurs only once every 7.

Assuming that the output of the AND circuit 141 is the SEL1 signal ■, and the output of the AND circuit 142 is the SEL2 signal ■, the SEL1 signal ■ is applied to the AND circuit 98 in FIG.

The NAND circuit 98 also has an inverter circuit 9 as an input.
Since the binary code representing the product setting price P is added from 6 to 6, the binary code representing the product setting price P1 is added by SEL and the signal ■ to the wired OR circuit WO12, the inverter circuit 79, and the OR circuit 44. The signal is added to the adder/subtracter ADD via the subtracter ADD.

That is, since the SEL1 signal ■ is generated only once in the interval from t1 to t7, the output of the OR circuit 44 is a binary code representing the product setting price P1.

The adder/subtracter ADD has an inverter circuit 43 as another input.
When there is no coin input signal ■, "1" is added, so the subtraction mode is entered, and the adder/subtractor ADD subtracts the product setting price P1 from the total input amount X, and the change amount K is stored in the shift register SR2. Ru.

The same is true for the product setting price P2, and SE
The L2 signal ■ is applied to the NAND circuit 99, and the rest is carried out in the same way as the product setting price P1.

These change amounts are calculated using the cycle timer 16 in FIG.
3, and when the output of the cycle timer 163 disappears, the output of the inverter 140 becomes 1''.

The AND circuit 133 receives the output of the inverter 140, the SEL signal e which has become "1" immediately, and the shift register S.
Since the signal ■ which becomes "1" when the content of R2 is not O is given, the content of shift register SR2 (that is, the amount of change) becomes 0 when the output of the cycle timer 163 disappears.
If not, the AND circuit 133 outputs an output, and the OR circuit 133 outputs an output.
A coin payout signal B1 is issued via the circuit 134 to start the change payout operation.

Next, the mechanism for dispensing change will be explained.

The stored contents of the shift register SR2 representing the change amount K obtained by subtracting the product setting price P1 or P2 from the input amount X are sent to the comparator COMP1, which indicates K≧50 comparator 6 in FIG. 1, and is compared with Y50.

The output of the comparator COMP1 is applied to an AND circuit 77, which also receives as other inputs the Y50 no change signal A2 inverted by an inverter circuit 78, and the SEL signal O which is the output signal of the flip-flop circuit FF18. has been added.

Therefore, if there is a change coin of Y50 and a product with a change amount of Y50 or more is sold, the output of the AND circuit 77 will be ``
1'' is generated, and the Y50 change payout signal B2 is generated as the output of the OR circuit 76, and this and the above-mentioned coin payout signal B1 are generated.
Y50 change is paid out using .

The output of the OR circuit 76 is added to the AND circuit 74,
The D circuit 14 receives a change payout confirmation signal PO as another input.
S is added, and when ¥50 change is paid out, an output "1" is generated in the AND circuit 74, and this output is ORed.
Y is added to circuit 29 in the same way as when inserting a coin.
It is converted into a binary code representing 50 and added to the adder/subtracter ADD, but at this time, the output of the inverter circuit 43, which is the other input of the adder/subtracter ADD, is input to the AND circuits 25 to 2.
Since the output of 7 is "0", it is "1", so the adder/subtractor ADD is in subtraction mode, so the change amount K and Y5 are
A subtraction of 0 is performed.

When the change amount K becomes smaller than Y50, the output of the AND circuit 77 becomes "0", so "'1" is added to the AND circuit 73 via the OR circuit 76 and the inverter circuit 75.

The same change payout confirmation signal POS as the AND circuit 74 is added to the AND circuit 73;
Like the D circuit 74, every time change is dispensed, the output signal "1" is sent to the OR circuit 28 to subtract YIO from the change amount K.

To pay out the change of YIO, if the change amount K stored in the shift register SR2 still remains after subtracting the change of Y50, the change is sent to the shift register SR by the OR circuit 46.
Since the signal ■ indicating that the memory contents remain in 2 continues to be generated, the AND circuit 133 and the OR circuit 134 continue to output the coin payout signal B1, and this and the ¥50 coin payout signal B2 have disappeared. This is done depending on the conditions.

These are known techniques, and generally the signal B1 is given to the change dispenser motor, and the signal B2 is given to the Y50, YIO switching solenoid.

Since Y50 change payout has priority over YIO change payout,
It becomes possible to pay out the minimum number of change.

Next, consider the case of refund.

First, we will discuss the case of manual refund.

The coin input signal ■ generated from the OR circuit 40 is the OR circuit 1
20 and the output of the OR circuit 120 is added to the AND circuit 12.
Added to 1.

The AND circuit 121 also has a NOR circuit 122 as an input.
The output of is added.

/d sales signal T (!: S E
L signal e to NOR circuit 1 48, inverter circuit 150
Since the output of inverter circuit 150 obtained through
Since the output of 22 is "1", when there is a coin input signal (2), the output of AND circuit 121 is "1", and the flip-flop circuits FF and 4 are set.

The output of the flip-flop circuit FF1 is a manual refund P.
It is added to the AND circuit 123 along with O.

Therefore, when a refund manual PO occurs, an output "1" is generated in the AND circuit 123 and is applied to the AND circuit 125 via the NOR circuit 124.

Since the AND circuit 125 has the input of the NOR circuit 126 added with the same input as the aforementioned NOR circuit 122 as another input, the output of the OR circuit 124 N 1 t+
is added, the output of the AND circuit 125 becomes "1"
'', and the flip-flop circuits FF, , are set.

The output of the flip-flop circuits FF, , is connected to the delay circuit Del.
ay2, AND circuit 146 via OR circuit 145
added to.

Since the output of the aforementioned NOR circuit 14i8 is also added to the AND circuit 146 as an input, when the SEL signal e is not generated, "1" is generated, so the AND circuit 146 outputs "1". , flip-flop circuit F
F1, is set and a refund signal ■ can be obtained.

By doing this, if the sales signal ■ occurs before adding the refund manual PO, the flip-flop circuit FF
14 is reset, so no refund signal is obtained, and even after the refund manual PO is applied, if the sales signal ■ or the SEL signal e occurs during the delay time of the delay circuit Delay2, the flip-flop? The circuit FF1 is reset to give priority to the sales signal T and SEL signal e.

In addition, an automatic refund signal ATPO, which will be described later, is added to the terminal of the manual refund manual PO.

Automatic refunds are available in the following cases: It is done.

That is, the output of the flip-flop circuit FF1 mentioned above is sent to the wired AND circuit WA1 via the inverter circuit 127, and the output of the flip-flop circuit FF13 is sent to the wired AND circuit WA1 via the inverter circuit 128.
1, AND the output of wired AND circuit WA1
Add to circuit 129.

Furthermore, the signal ■ of X>P1 and the signal ■ of x=p1 are added to the OR circuit 103, the signal ■ of X>P2 and the signal ■ of X=P2 are added to the OR circuit 104, and the OR circuit 103 and the OR circuit 1
04 output to the wired AND circuit WA2,
The wired AND circuit WA2 output is applied to the AND circuit 129.

By doing this, the wired ANp circuit WA2
When inputting an amount greater than or equal to the maximum product price setting value, an output of "1" is generated, and the output of the wired AND circuit WA is connected to the flip-flop circuits FF1 and FF.
, 3 is not generated, "1" occurs, AND
Circuit 129 provides an automatic refund signal ATPO.

That is, in this embodiment, if the sales outputs VEND, . . . VEND2 do not occur even if coins are inserted to the maximum limit, the money is automatically refunded.

This automatic refund signal ATPO is added to the manual refund manual PO described above, and the refund signal (2) can be obtained in the same manner.

Refunds are made in the following manner based on the refund signal (2) obtained in this manner.

In the embodiment, kY5 is used as shown in the block diagram of FIG.
For the insertion of coins of 0 and 100 yen, a 50 yen number register 4 and a 100 yen number register 5 are provided to count the number of coins inserted.

In other words, in Figure 2, the Y50 sheet number register is R1, ¥
The 100-sheet register is indicated by a horse.

The register R1 is used to sequentially set the flip-flop circuit each time an input is applied.
can count the insertion of up to 15 ¥50 coins, or 750 yen, and the register horse can count the insertion of up to 8 coins (800 yen).

Y50 number of sheets register R, ¥5 from AND circuit 26
The 0 coin input signal is being sent, and the Y50 coin input signal is also being sent to the AN along with the output of the cycle timer 39.
The output of the AND circuit 53 is applied to the OR circuit 54.

Cycle timer 3 every time there is a coin input signal of Y50
Since a signal is applied to the AND circuit 53 only during the bit pulse period from 9 to t1 to t7, the number of Y50 coins inserted is stored in the Y50 coin number register R by the output pulse signal of the OR circuit 54.

Similarly, the ¥100 coin input signal from the AND circuit 27 is added to the ¥100 coin number register.

Furthermore, the ¥100 coin input signal is input to the cycle timer 39.
Since the output of the AND circuit 64 is applied to the OR circuit 67, the output pulse of the OR circuit changes the ¥100 coin input signal to ¥10.
It is stored in the 0-sheet count register R2.

At the same time as the refund signal ■ is generated, a refund signal ESC/RTRN for the 100 yen coin held in the escrow is issued, and the 100 yen coin held in the escrow is refunded.

The Y50 number register R1 includes an OR circuit 58, an AND circuit 59, an inverter circuit 60, and a flip-flop circuit FF.
A circuit consisting of 6 is attached, and the flip-flop circuit FF6 is set at the same time as the ¥50 coin input is added to the Y50 coin number register, and when the memory content of the Y50 coin number register becomes ON O n, the flip-flop circuit FF6 is set. Reset the flip-flop circuit FF
The stored contents of the Y50 sheet number register R1 can be determined by the output of 6.

Similarly, OR circuit 69 and AN are applied to the ¥100 number register horse.
A circuit consisting of a D circuit 70, an inverter circuit 72, and a flip-flop circuit FF7 is attached, and the contents of the ¥100 number register can be determined from the output of the flip-flop circuit FF7.

When the refund signal (2) is generated, the refund signal (2) is applied to the AND circuit 66, and by adding the clock pulse φ3 as another input to the AND circuit 66, the AND circuit 66 can obtain an output synchronized with the clock pulse φ3.

An OR circuit 71 receives the output of the AND circuit 66, the ¥100 number register horse, and the flip-flop circuit FF7.
is added to the AND circuit 65, so when the output of the flip-flop circuit FF7 is "1", that is, while the number of YIOO coins inserted is stored in the ¥100 number register R2, the output is output to the AND circuit 65. '1''
is generated, and a pulse is applied to the YIOO sheet number register R2 as the output of the OR circuit 67', thereby sequentially moving the memory of the ¥100 sheet number register R2 toward the output end.

When a signal is output from the output end of the ¥100 sheet count register R2, that signal is added to the AND circuit 68 along with the output of the AND circuit 65, and a signal is output from the output end of the ¥100 sheet count register R2 to subtract the number of sheets stored in YIOO. The output “1” generated from the AND circuit 68 is output to the OR circuit 30 each time
In addition to that, the input amount
Subtract ¥100 from .

In this way, by sequentially subtracting the number of sheets stored in the ¥100 sheet number register R2, the stored contents of the \100 sheet number register R2 are emptied.

The output of the OR circuit 71 becomes "0" due to the storage contents of the ¥100 number register R2 becoming empty, and the NOR circuit 6
``0'' is added to one input of ``1'', and ``1'' is added to the AND circuit 63 as the output of the inverter circuit 56.

The AND circuit 63 also receives as inputs a signal from the output end of the Y50 sheet number register, a refund signal (2), and a signal (2) from the OR circuit 46.

If Y50 is turned on, flip-flop circuit FF6 is set and remains active. The output of the NOR circuit 61, and therefore the output O of the AND circuit 62, is not generated immediately, but is outputted via the AND circuit 57 and the OR circuit 54 to Y5.
Since the memory contents of the 0 sheet count register R1 are moved to the output end at the same time as the YIOO sheet count register R2, Y5 will be returned to Y5 after a short period of time, depending on the memory contents.
Zero sheet count register R1 produces an output.

This output, on the one hand, resets the flip-flop FF6 via the inverter 60 to prevent further movement of the memory contents via the AND circuit 57, and also
The R circuit 61 generates an output, and the output O is generated only through the AND circuit 62.

The output of the Y50 number register R1 is given to the AND circuit 63 on the other hand, and as a result, the AND circuit 63 outputs "■"
is generated, its output is applied to the OR circuit 76, and the above-mentioned Y
As in the case of dispensing 50 change, the Y50 dispensing signal B2 and the output O of the AND circuit 62 mentioned above are connected to the OR circuit 1 in FIG.
Y50 due to the coin payout signal B obtained through 34.
coins are paid out, and Y50 is subtracted from the memory contents of the total payout shift register SR2 in response to the change payout confirmation signal POS.

The change payout confirmation signal POS is applied to the AND circuit 55, and to the AND circuit 55, the signal from the output terminal of the ¥50 number register R1 and the output of the inverter circuit 56 are also added as inputs, and the signal from the output end of the ¥100 number register R2. The memory contents are empty, and the ¥50 number register. If there is a memory content in R1, an output "1" is generated in the AND circuit 55 by receiving the change payout confirmation signal POS, and this output is sent to the Y50 number register R, via the OR circuit 54, and the 50 yen The stored contents of the sheet number register R1 are moved by one toward the output end.

This process is repeated until the stored contents of the Y50 sheet number register R1 become empty.

When the stored contents of the Y50 coin number register R1 become empty, the output "1" of the AND circuit 63 disappears, and the payout of Y50 coins ends.

When the stored contents of the Y50 sheet number register and the ¥100 sheet number register become empty, if the stored contents remain in the shift register SR2 and the OR circuit 46 generates the output ■, the AND circuit 62 still generates the output ◎. O because there is
The coin payout signal B1 continues to be outputted via the R circuit 134, and based on the condition that this and the Y50 coin payout signal B2 have disappeared, ¥10 is issued in the same way as when paying out change.
Allow coins to be paid out.

Then, in the same way as when paying out change of 10 yen, the change payout confirmation signal POS is used to subtract from the total payout shift register SR2 until the output ■ of the OR circuit 46 becomes ``0'', that is, the shift register S
YIO coins are paid out until the memory contents of R2 become empty.

In this way, by providing the ¥50 number register R1 and the ¥100 number register R2, it is possible to refund the same amount and combination of coins in the case of refund.

In the embodiment, in order to deal with coin jams, when there is a coin input signal
One is directly connected to the two input terminals of 51, and the other is connected to the delay circuit D.
By adding via e l a y 3, if coin force ■ is occurring even after the delay time, AND
An output "1" is generated in the circuit 151, and this output is sent to the OR circuit 1.
53, the output N 1 of the OR circuit 153
? 1 can prevent subsequent coin insertion.

However, the delay time of the delay circuit Delay3 is sufficiently long compared to the coin input signal time, and here it is 30
A value of 0 mSeC is used.

According to this method, it is possible to prevent coin insertion after a delay time in the case of a coin jam in which a coin input signal is generated even when the power is interrupted and then turned on again.

In the embodiment, there are other cases in which the CREM is turned off (coin insertion inhibited state) as follows.

That is, the output "1" is output to the wired AND circuit WA2 described above.
If this occurs.

That is, when the input amount is equal to or exceeds the maximum product setting price, there is no need to insert any more coins, so further coin insertion is prevented.

Further, when the sales signal T is sent, the manual refund manual PO, and the automatic refund signal ATPO are sent, the insertion of coins is prevented.

This can be done by adding the output of the wired AND circuit WA2, the output of the sales signal T1 flip-flop circuits FF1 and FF,7 to the OR circuit 152, and adding the resulting outputs of the OR circuit as inputs to the OR circuit 153.
This can be implemented by performing CREM control using the output of the R circuit 153.

When operations such as selling, dispensing change, and refunding are completed, the operation (hereinafter referred to as "clear") for transitioning the electronic control circuit for the vending machine coin knock to a state in preparation for the next sale is as follows. It is done.

That is, the coin payout signal B1 is applied to the NAND circuit 137 via the inverter circuit 136.

The NAND circuit 137 also receives the refund signal ■ and SE as inputs.
It consists of three people: adding the L signal e to the OR circuit 135 and applying the output of the OR circuit directly and via the delay circuit Delay1.

Therefore, if there is no coin payout signal B1 and a refund signal ゛■ or SEL signal e is generated, the delay circuit Delay1
After a delay time of , the output of the NAND circuit 137 becomes "0".

The delay time of the delay circuit Delay1 is sufficiently long compared to other operating times of the device of this embodiment, and a value of 2 seconds is used here.

The output of the NAND circuit 137 is a wired OR circuit ■01
Added to 3.

In addition, the wired OR circuit W013 has a signal EXT clear signal indicating that it will not be cleared from the outside, and NAND13.
An output of 0 is added as an input.

EXT clear signal is automatically cleared internally, signal AC
It is used when trying to obtain L, and is always "1".

The SEL signal (a and the outputs of wired OR circuits WO, 4 and W015 are added to the NAND circuit 130, and the output of the wired OR circuit changes to "0" when any of the inputs becomes "0". E because it is something to do
When either the XT or NAND circuit 130 or 137 becomes the output "0'", the wired OR circuit WO1
The change in the output of flip-flop circuit FF1 is applied to the inverter circuit 138, and the output of the flip-flop circuit FF1 is inverted by the output of the inverter circuit 138.
When the output of 11 is "1", an automatic clear signal ACL@ is obtained as an output to the inverter circuit 139.

ACL signal 0 is applied to comparators COMP1-COMP, causing them to be reset.

As described above, the operation of the electronic control circuit for vending machine vending control of the present invention shown in FIG. 1 can be achieved by the embodiment shown in FIGS. By further increasing the two product price setting circuits shown and matching other circuits, it is also possible to sell two or more products with different prices in one electronic control circuit for vending machine vending control. It is possible.

The above operations of the present invention are not limited to coins, for example,
It goes without saying that this method can also be applied to items that use 100 yen coins, 000 yen papers, and 100 yen coins.

As described above, when a product selection signal is issued due to product selection, if a sales start signal is not given from the vending machine side, the control circuit will be automatically cleared. By delaying the product by the time of , the product selection signal is reliably received and automatic clearing of the control circuit is prevented, so that sales control is performed accurately without hindrance to sales.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a vending machine electronic control circuit of the present invention, and FIGS. 2 and 3 are circuit diagrams of embodiments of the present invention. 1...Encoder, 2...Adder/subtractor,
3...Shift register for total payout,
4...Y50 number register, 5...¥
100 number register, 6...K≧50 comparator, 7...P1+90 adder, 8...
・P1+5 0 adder, 9...P2+90 adder, 10...P2+50 adder, 11...
... Comparator for P1, 12 ... Comparator for P2, 13 ... P1゜ price setting circuit, 14
...P2 price setting circuit, 15...P8
Bend control circuit for P2, 16...Bend control circuit for P2, 17...Coin payout control circuit, 18.
... Coin jam detection circuit, 19 ... Refund latch circuit, 20 ... Automatic refund circuit, 21.
...Select latch circuit, 22...CR
EM control circuit, 23... Two-phase clock pulse generation circuit, 24... Bit pulse generation circuit, 25
~27,37.49~53,55.57,59.62~
66.68.70,73,74,77,102,106
,108,113,116,119,121,123,
125, 129, 131-133, 141, 142,
146, 151, 155, 158...AND circuit, 28-31.3B, 40, 44, 46, 54, 58
．． 67,69,71,76.80-82,95,103
~105,107,114,117,120,124,
134,135,145,152-154,157...
...OR circuit, 32-35.83-94.98-1
01, 111, 112, 130, 137, 156...
...NAND circuit, 42, 61, 118, 122,
126, 148, 159...NOR circuit, 36
,41,43,56,60,72,75,78,79,
96,97,109,110,115,127,128
, 136, 138-140, 143, 147, 149,
150, 160-162... Inverter circuit,
39,163,...cycle timer, Dela
y1~Delay4...Delay circuit, FF1~F
F4, FF11~FF18... Fritz. Pflotz circuit, COMP1 to COMP9...Comparator, WO-WO...Wired OR circuit, 1 15 WA-WA...Wired AND circuit, SR1, 13 SR2... ...2-phase dynamic shift register,
R1, R2...Register, FA1~FA4...
...Full adder, PRICE1.2...Product setting price, POS...Coin payout confirmation signal,
ATPO・・・Automatic refund signal, PO・・・・・・
Refund input, A1...¥10 no change signal, A2
...... ¥50 no change signal, B1... Coin payout signal, B2... Y50 coin payout signal, T... Sales signal, vEND1,2...・
...Sellable signal, ESC-RTRN...Coin refund signal in escrow, ESC-ACC coin collection signal in escrow, EXT-CL...External clear signal, SING...・Price setting number selection signal, ■
... Coin input signal, ■ ... Refund signal, ■ ... Tuft register SR2 memory content existence signal, ■ ... X>P, signal, ■ ... ...X>P
1+90 signal, ■...X=P1 signal, ■...
・・Lower movement clear signal ACL, ■・・・・X>P2 signal, ■・・・・X>P2+90 signal, ■・・・・
・X-P2 signal, ■...P1=0 signal, ■...
...P2-0 signal, e...Select signal S
EL,■...Select signal SEL■...
・・Select signal SEL2, ■・・・Electronic control circuit operation signal for digital injection, O・・・・YIO coin payout signal, [F]・・・X=P1+50 signal, ■・・・・...X-P2+50 signal, SEL1, SE
L2...Select input signal, CREM...
...Coin insertion prevention signal, t1-t7...Bit pulse, φ1, φ2, φ3...Clock pulse.

Claims (1)

[Claims] 1 It is possible to set multiple prices, and the input amount is compared with each of these multiple set prices, and a sellable signal is sent for each set price at which the inputted amount exceeds the set price, and the sellable signal is sent. A control for a vending machine receives a sales start signal and a product selection signal sent from the vending machine main body based on the above, and performs a selection judgment as to which of the set prices has been selected, and controls the dispensing of change. 1. A control circuit for a vending machine, characterized in that the selection decision is made after a predetermined period of time has elapsed from the arrival of the sales start signal.