JPS596505B2 - Method for diffusing impurities into semiconductor substrates - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a diffusion process from one entire surface of a semiconductor substrate into the semiconductor substrate, such as a base diffusion process of a triple diffused mesa transistor or a diffusion process to form an anode or cathode region of a rectifying element. This invention relates to a method of diffusing impurities.

For example, the formation of the base region (4 in FIG. 2) of a triple diffused mesa type NPN transistor is as shown in FIG.
It is usually formed by forming an N+ type high impurity concentration region 2 on one side of the type silicon substrate 1, and then diffusing P type impurities over the entire surface from the opposite surface.

Note that when diffusing P-type impurities to form this base region 4, it is necessary to prevent so-called out-diffusion, in which N-type impurities diffuse outside from the N+ type diffusion region 2 formed on the back surface, and to In order to prevent type impurities from diffusing into the N+ type region, the entire back surface is covered with an oxide film 3, and then a diffusion process is performed. Incidentally, the front surface of the N-type silicon substrate 1 is mirror polished, while the back surface is roughened by JIS #1200 lapping and has a thickness of 19 mm.
The N+ type diffusion region 2, which has a disc shape of approximately 0 μm and is formed by diffusing phosphorus from the back surface, has a diffusion depth of approximately 100 tt.
m, and the surface concentration is about 1020C-lrL-3.
By the way, if such a silicon substrate is heated at a high temperature (about 1200°C) for a long time in the base diffusion treatment process,
Since the thermal expansion coefficients of the silicon substrate 1 and the oxide film 3 covering the back surface thereof are different, a bimetal phenomenon occurs, and the silicon substrate subjected to the base diffusion process is warped. Figure 2 shows
This is a diagram illustrating the physical sensation of a silicon substrate on which a base region is formed. As shown in the figure, the silicon substrate is warped so that the side on which the P-type base region 4 is formed becomes a convex surface. This warping of the silicon substrate generates stress within the silicon substrate, which is called slip, which occurs in areas where stress tends to concentrate, such as the contact area with the quartz boat that houses the silicon substrate during the diffusion process. Linear lattice defects occur. Figure 3 shows
As a general example, the slip line 5 is generated linearly from the periphery of the silicon substrate along the crystal axis.

Furthermore, if a strong bimetal phenomenon is caused by increasing the thickness of the oxide film covering the back surface of the silicon substrate, stress will be concentrated at the center of the substrate, and the slip line 5 will be at the center as shown in FIG. It shows a tendency to decrease in the peripheral areas. This slip line is caused by the crystal lattice stretching along the crystal axis plane, and the crystal lattice collapses along the stretched plane, and can be easily observed because etching pits are generated in succession due to etching. . When a transistor is manufactured using a silicon substrate with such slip lines, the defective surface acts as a group of recombination centers for current carriers, resulting in deterioration of the withstand voltage characteristics of the manufactured transistor, increase in leakage current, or current amplification. Many inconveniences occur, such as a decrease in the rate.

The present invention has been made in order to eliminate the above-mentioned disadvantages, and can suppress the bimetal phenomenon that becomes noticeable in the diffusion treatment process in which the entire surface diffusion treatment is performed only on one side of the semiconductor substrate. The purpose of the present invention is to provide a method for diffusing impurities into a semiconductor substrate, which can prevent the occurrence of slip lines due to warping of the semiconductor substrate.

A feature of the present invention is that when an N-type or P-type impurity is diffused over the entire surface of a semiconductor substrate whose one surface is covered with an oxide film, an oxide film that is thinner than the oxide film that covers one surface of the semiconductor substrate is used. Alternatively, the entire other surface of the semiconductor substrate may be covered with a film such as a nitride film, and impurities may be diffused through the film.

The present invention will be described in detail below with reference to the drawings. FIG. 5 is a view showing the state immediately before base diffusion treatment of a triple diffusion mesa type NPN transistor in which a base diffusion region is formed by the method of the present invention. A coating, for example, an insulating coating 6, which is thinner than the oxide film 3 covering the back surface, that is, the entire surface of the N+ type diffusion region 2, is formed over the entire area. FIG. 6 is a cross-sectional view of the silicon substrate shown in FIG. 5 after a base diffusion process using a P-type impurity such as boron is performed, and as shown, a thin insulating film 6 is passed through the silicon substrate. Boron diffuses into the N-type silicon substrate 1 and forms the P-type base region 7.
According to the method of the present invention, although the bimetal phenomenon based on the difference in thermal expansion coefficient between the silicon substrate 1 and the oxide film 3 still occurs, the heat between the silicon substrate 1 and the insulating film 6 is A new bimetal phenomenon based on the difference in expansion coefficient has occurred, and since the directions of the forces acting on the semiconductor substrate to warp it due to both phenomena are opposite, they cancel each other out, and therefore , the silicon substrate 1 does not warp to the extent that a slip line occurs.

By the way, in the method of the present invention, since impurities are diffused through the film, there are some technical issues that must be taken into account. That is, when forming the insulating film 6, the strength of the bimetal phenomenon that occurs between the film and the silicon substrate occurs between the oxide film 3 and the silicon substrate. The thickness should be selected to be equivalent to the strength of the bimetal phenomenon caused by the insulating film, and to allow diffusion of impurities through the insulating film. The following table shows the insulating film (Si
1200 by changing the thickness of the O2 film) and making full use of the sealing tube method.
The results of an experiment in which boron was diffused for 8 hours at a temperature of .degree. C. are shown.

The boron concentration of the impurity source placed inside the tube is 2.5×
The furnace temperature was adjusted to 1020 cTn-3, and the furnace temperature was controlled by a slow heating and slow cooling program to avoid the effects of sudden temperature changes.

As is clear from this result, when the film thickness is 300λ or more, there is an effect of suppressing the occurrence of slip lines.

In addition, the upper limit of the film thickness should basically be smaller than the thickness of the oxide film on the back side, but if it is made too thick, the surface impurity concentration of the diffusion region will decrease, and the electrode cannot be directly connected to the diffusion region. Contact resistance increases when attached. Is the surface impurity concentration required to obtain good contact conditions 1018? -3 or more, and considering this and the effect of suppressing the generation of slip lines, the thickness of the insulating coating 6 should be approximately 1000 to 3.
It is effective to select approximately 000 people. As described above, according to the method of the present invention, it is possible to suppress the occurrence of slip lines and to perform a full-surface diffusion process on a semiconductor substrate.

Note that, in view of the purpose of the present invention, it is of course possible to use a film other than an insulating film such as an oxide film or a nitride film as long as it is a film that causes a bimetal phenomenon and allows diffusion of impurities.
Although the above description has been made using boron as an example of the impurity, other impurities such as phosphorus, arsenic, and aluminum can also be used. In particular, when aluminum is used as an impurity, the thickness of the insulating film is 20
It was confirmed that up to about 0.08, a surface impurity concentration comparable to that without an insulating film could be obtained without increasing the concentration of the impurity source. Furthermore, the present invention can also be applied to an open tube method; in the case of the open tube method, impurities are excessively present in the atmosphere in which the semiconductor substrate is placed; There is no need to pay attention to the amount of source.

Furthermore, semiconductor substrates are not limited to silicon;
It may be a germanium substrate or a compound semiconductor substrate.

Furthermore, the diffusion method of the present invention is applicable not only to the step of base diffusion of the triple diffused mesa transistor shown in the above embodiment, but also to the step of forming a predetermined region by full-surface diffusion treatment, such as the step of forming a predetermined region on the anode of a rectifying element or Of course, it can also be applied to cathode diffusion treatment steps, etc.

[Brief explanation of the drawing]

1 and 2 are diagrams for explaining the process of forming the base region of a triple diffused mesa type NPN transistor by the conventional method and the state after the base region is formed. A schematic diagram showing the state of occurrence of slip lines in a silicon substrate subjected to diffusion treatment,
FIGS. 5 and 6 are diagrams for explaining the step of forming a base region of a triple diffused mesa type NPN transistor according to the method of the present invention and the state after the base region is formed. 1...N-type silicon substrate, 2...N+
Type diffusion region, 3... Oxide film, 6... Insulating film, 7... P type base region.

Claims (1)

[Claims] 1. When diffusing donor or acceptor impurities over the entire surface from the other surface of a semiconductor substrate, one surface of which is covered with an oxide film having a thickness that prevents impurity from passing through, A film with a thickness selected to be in the range of 300 Å to 2000 Å is formed over the entire other surface of the semiconductor substrate, and then impurities are diffused over the entire surface through the film, so that electrode contact can be made over the entire other surface layer of the semiconductor substrate. A method for diffusing impurities into a semiconductor substrate, the method comprising forming a diffusion region having a surface impurity concentration.