JPS6051198B2 - semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which input/output terminals and a read-only memory are formed on the same semiconductor substrate.

Recently, read-only memory (hereinafter referred to as ROM) is available on the same chip.

), Random Read Memory (Random Access Memory, hereinafter referred to as RAM), ALU (Arjthmeticand
There are so-called single-chip microcomputers that include LogicUnit and the like.

These microcomputers are constructed so that their input/output terminals can be used for either input or output functions so that they can be used in a wide range of fields. Figure 1 is a circuit connection diagram showing a conventional example of such input/output terminals.
It is composed of S transistors.

F1 is a flip terminal with set terminal S) and reset terminal R.
In the flop, T1 to T12 are transistors, 0 is an input/output terminal, and 1, Q2 are terminals connected to other logics.
That is, by setting or resetting the flip-flop F according to the instructions written in the ROM, the flip-flop F is set or reset.
The terminal Wf■ is made to function as an output terminal or an input terminal. That is, when transistors T, T6 are cut off, input/output terminal 0 functions as an output terminal, and when turned on, output transistors Tl and T6 function as an output terminal. Since the output inverter composed of the input and output terminals 0, is in a floating state with high resistance, 01 functions as an input terminal, and the input inverter composed of the transistors Tl, , T, and 2 is used. Become. In addition, the function of these input/output terminals is generally fixed as input or output once the application target of the microcomputer to be used is determined; once an input/output terminal is determined to be an input, The same terminal is never used as an output.

This is because the relationship between the input and output of the circuit to be connected is also constant. Next, in the case of a single-chip microcomputer, these input and output terminals are grouped in groups of 4 or 8, depending on the function.
In order to reduce the number of flip-flops mentioned above, it is necessary to select either input or output for 4 or 8 terminals at once.On the other hand, it is possible to specify input or output for each terminal. In order to do this, it was necessary to have a flip-flop for each terminal.

7 In addition, any of the above methods requires an instruction to set the flip-flop, and if input or output is set for each terminal, the program memory area will be consumed by the instruction to set the flip-flop. There is a drawback that it can happen.

The present invention has been made with attention to these points, and provides a semiconductor integrated circuit having a simple configuration and suitable for high integration, in which at least an input/output terminal and a read-only memory are formed on the same semiconductor substrate. The purpose is to According to the present invention, in a semiconductor integrated circuit in which at least an input/output terminal and a read-only memory are formed on the same semiconductor substrate, a predetermined output transistor is made to have a high resistance in order to fix the function of the input/output terminal. A semiconductor integrated circuit is obtained, characterized in that the means for fixing the control electrode potential of the output transistor is of the same type as the memory element of the read-only memory.

In a read-only memory, an output signal or a set of output signals uniquely corresponds to a given input signal or set of input signals.

This correspondence is then provided by the memory element. The memory element is placed at a selected intersection of the input and output lines of the read-only memory. In practice, for example, it is common practice to arrange two types of MOS transistors with different threshold voltages at every intersection, but in this specification, one of the MOS transistors is defined as a memory element. Next, the present invention will be explained according to examples thereof and with reference to the drawings.

FIG. 2 is a circuit connection diagram showing an embodiment of the present invention.
This is the case for channel MOS. 01 is an input/output terminal, and 11 and 02 are connected to other logics.

In addition, they are arranged on the same chip (not shown).
) ROM is a memory that adjusts the threshold value by selectively implanting ions into MOS transistors placed at the intersections of input and output lines according to a program that determines the correspondence between given inputs and outputs. It is completed by making it into an element. First, the case where input/output terminal 0 is used as an input will be explained. Here, the transistors T4 and T6 connected to the gates, which are the control electrodes, of the output transistors Tl and T2, which are output buffers, are of the same type as the memory element,
Ions are implanted in the ROM ion implantation process and completed. As a result, T7 and T8 are
No matter how the voltage changes, the gates of T1 and T2 are kept at the lowest potential, and the output 4 terminal 01 becomes a floating state. Therefore, the signal input from 01 is transmitted to transistors T,
, Tl2 through the input buffer configured by Tl2.
01 will operate as an input terminal. On the other hand, when input/output IiU)1 is used as an output terminal, unless ion implantation is performed on T4 and T6, the respective transistors T4 and T5 will be in a cut-off state (that is, T4 and T5 will not substantially exist, and the memory It is not the same type as the element.

), it can be used as an output terminal since it does not cause any trouble to the gates of T1 and T2). Next, FIG. 3 is a circuit connection diagram showing another embodiment of the present invention.

In this example, the arrangement of memory elements to complete a ROM (not shown) is an N-channel MO completed by a contact process, a diffusion process, an aluminum wiring process, etc.
In the case of S, if 01 is used as an input terminal, P1
Alternatively, at the portion indicated by P2, it is connected by contact, diffusion, aluminum wiring, etc. to make it the same type as the ROM memory element. As a result, the gates of the output buffer transistors T1 and T2 are pulled down to the lowest potential, and the terminal 01 becomes a floating state and functions as an input terminal. On the other hand, when using 01 as an output terminal,
It is sufficient if the parts indicated by Pl and P2 are not connected.

As explained above, according to the present invention, the control electrode potential of the output transistor is fixed by the same type of means as the memory element, so the configuration is simple, and the input/output terminal and ROM
This has the effect of improving the degree of integration of a semiconductor integrated circuit formed on the same substrate. Although the explanation was given for the case using MOS transistors, bipolar
It goes without saying that the present invention can also be applied to transistors.

[Brief explanation of the drawing]

Figure 1 is a circuit connection diagram showing an example of conventional input/output terminals, Figure 2
The figure is a circuit connection diagram showing one embodiment of the invention, and FIG. 3 is a circuit connection diagram showing another embodiment of the invention. F1...Flip flop, 01...
Input/output terminals, Tl,...Tl2...Transistors, Pl, P2...Ion implantation regions.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit in which at least an input/output terminal and a read-only memory are formed on the same semiconductor substrate, in order to fix the function of the input/output terminal, a predetermined output transistor has a high resistance. A semiconductor integrated circuit characterized in that means for fixing a control electrode potential of a transistor is of the same type as a memory element of the read-only memory.