JPS6159674B2 - - Google Patents
Info
- Publication number
- JPS6159674B2 JPS6159674B2 JP54171544A JP17154479A JPS6159674B2 JP S6159674 B2 JPS6159674 B2 JP S6159674B2 JP 54171544 A JP54171544 A JP 54171544A JP 17154479 A JP17154479 A JP 17154479A JP S6159674 B2 JPS6159674 B2 JP S6159674B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- gaas
- film
- gate
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 36
- 239000010408 film Substances 0.000 claims description 28
- 239000010409 thin film Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 20
- 230000003647 oxidation Effects 0.000 claims description 18
- 238000007254 oxidation reaction Methods 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 10
- 230000002265 prevention Effects 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 238000007743 anodising Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 6
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 3
- 239000003086 colorant Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000002048 anodisation reaction Methods 0.000 description 2
- 239000008151 electrolyte solution Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- FEWJPZIEWOKRBE-JCYAYHJZSA-N Dextrotartaric acid Chemical compound OC(=O)[C@H](O)[C@@H](O)C(O)=O FEWJPZIEWOKRBE-JCYAYHJZSA-N 0.000 description 1
- FEWJPZIEWOKRBE-UHFFFAOYSA-N Tartaric acid Natural products [H+].[H+].[O-]C(=O)C(O)C(O)C([O-])=O FEWJPZIEWOKRBE-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 235000002906 tartaric acid Nutrition 0.000 description 1
- 239000011975 tartaric acid Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
Landscapes
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特に半
導体としてGaAsを用いたバルク導電型絶縁ゲー
ト電界効果トランジスタの製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a bulk conduction type insulated gate field effect transistor using GaAs as a semiconductor.
バルク導電型絶縁ゲート電界効果トランジスタ
(以下バルク導電型MOS FETと称す)は、第1
図に示すように、半絶縁性基板1上に一導電型の
半導体層2を設け、この半導体層2上にソース電
極3、ドレイン電極4を設け、また両電極間の半
導体層2上に絶縁膜5を介してゲート電極6を形
成した構造を有しており、ゲート電極6に印加す
る電圧によりソース電極3とドレイン電極4間の
半導体層2を流れる電流を制御するものである。
このバルク導電型MOS FETは、Siなどで広く実
用化されている反転型MOS FETに比べてキヤリ
ア移動度が大きいので高速動作が可能であり、ま
たゲート長を短くしても反転型MOS FETにみら
れるようなパルチスルー等の短チヤネル効果は起
らない。更にシヨツトキゲート型FETと異な
り、ゲート電極に正の電圧を印加してもゲート電
流が流れないので論理振幅を大きくとることがで
きる等の利点を有しており、高速動作に適した素
子であるといえる。そして、より高速動作を可能
にするには、Siよりもキヤリア移動度の大きい
GaAsを半導体材料に用いることが原理的に有利
であることから、近年その種の素子の開発研究が
押し進められている。 A bulk conduction type insulated gate field effect transistor (hereinafter referred to as a bulk conduction type MOS FET) is a
As shown in the figure, a semiconductor layer 2 of one conductivity type is provided on a semi-insulating substrate 1, a source electrode 3 and a drain electrode 4 are provided on this semiconductor layer 2, and an insulating layer is provided on the semiconductor layer 2 between both electrodes. It has a structure in which a gate electrode 6 is formed through a film 5, and the current flowing through the semiconductor layer 2 between the source electrode 3 and the drain electrode 4 is controlled by the voltage applied to the gate electrode 6.
This bulk conduction type MOS FET has higher carrier mobility than the inverted type MOS FET, which is widely used in Si, etc., so it can operate at high speed, and even if the gate length is shortened, it can be used as an inverted type MOS FET. Short channel effects such as pulch-through do not occur. Furthermore, unlike shot-gate type FETs, gate current does not flow even when a positive voltage is applied to the gate electrode, so it has the advantage of allowing a large logic amplitude, making it an element suitable for high-speed operation. I can say that. And to enable higher-speed operation, it has a higher carrier mobility than Si.
Since the use of GaAs as a semiconductor material is advantageous in principle, research and development of such devices has been promoted in recent years.
ところで、GaAsバルク導電型MOS FETを製
造する従来の方法に於いては、絶縁膜5の形成方
法として、一般に熱酸化法、電解溶液中での陽極
酸化法あるいはプラズマ酸化法等を用いてGaAs
の一部を直接酸化する方法や、CVD法、真空蒸
着法等を用いてGaAs上に他の絶縁膜を装荷する
方法が採用されている。しかし、これら従来の方
法によつて製造したGaAsバルク導電型MOS
FETでは、その半導体層2と絶縁膜5との界面
に多量の界面準位が存在するという致命的な欠点
を有している。その為、界面準位が応答する低周
波で充分な電流変化が得られず、バルク導電型
MOS FETの有する利点を充分に発揮することが
できなかつた。 By the way, in conventional methods for manufacturing GaAs bulk conduction type MOS FETs, the insulating film 5 is generally formed using a thermal oxidation method, an anodization method in an electrolytic solution, a plasma oxidation method, etc.
Methods of directly oxidizing a portion of GaAs, and methods of loading other insulating films on GaAs using CVD, vacuum evaporation, etc., have been adopted. However, GaAs bulk conduction type MOS manufactured by these conventional methods
The FET has a fatal drawback in that a large amount of interface states exist at the interface between the semiconductor layer 2 and the insulating film 5. Therefore, it is not possible to obtain a sufficient current change at low frequencies where the interface states respond, and the bulk conductivity type
The advantages of MOS FETs could not be fully demonstrated.
即ち、一般に論理素子を構成する場合、個々の
FETは次段との結合の問題と消費電力を小さく
する必要性からゲートに電圧を印加していないと
きに電流が流れないタイプいわゆるノーマリオフ
型のものが必要であり、このような素子では、正
のゲート電圧に対し充分な電流変化が得られるこ
とが要求される。ところが、従来の製法たとえば
絶縁膜5をプラズマ酸化法を用いて形成する方法
で製造したGaAsバルク導電型MOS FETでは、
その直流ドレイン特性は例えば第2図に示すもの
となり、界面準位密度が高いために正のゲート電
圧に対するドレイン電流の変化は小さなものにな
つてしまう。 In other words, when configuring a logic element, each
Due to coupling problems with the next stage and the need to reduce power consumption, FETs must be of the so-called normally-off type, in which no current flows when no voltage is applied to the gate. It is required that a sufficient current change can be obtained with respect to the gate voltage. However, in a GaAs bulk conduction type MOS FET manufactured using a conventional manufacturing method, for example, a method in which the insulating film 5 is formed using a plasma oxidation method,
Its DC drain characteristics are, for example, as shown in FIG. 2, and because the interface state density is high, the change in drain current with respect to a positive gate voltage is small.
本発明はこのような従来の欠点を改善したもの
であり、その目的は、GaAs半導体層と絶縁膜と
の界面特性の優れたGaAsバルク導電型MOS
FETを製造する方法を提供することにある。以
下実施例について詳細に説明する。 The present invention improves these conventional drawbacks, and its purpose is to provide a GaAs bulk conduction type MOS with excellent interface characteristics between a GaAs semiconductor layer and an insulating film.
The object of the present invention is to provide a method for manufacturing FETs. Examples will be described in detail below.
第3図乃至第8図は、本発明の実施例を説明す
る為の工程図であり、各図に於いて、7はGaAs
半絶縁性基板、8はGaAs層、9はAl薄膜、10
は陽極酸化阻止膜、11はAl酸化膜、12はソ
ース電極、13はドレイン電極、14はゲート電
極、15はゲート領域である。 3 to 8 are process diagrams for explaining embodiments of the present invention, and in each figure, 7 is a GaAs
Semi-insulating substrate, 8 is GaAs layer, 9 is Al thin film, 10
11 is an anodic oxidation prevention film, 11 is an Al oxide film, 12 is a source electrode, 13 is a drain electrode, 14 is a gate electrode, and 15 is a gate region.
まず、第3図に示すように、GaAs半絶縁性基
板7上に一導電型を有するGaAs層8を液相エピ
タキシヤル法等により形成し、そのGaAs層8の
両側をメサエツチングした後、ゲートとして用い
る領域だけをGaAs層8の途中までエツチングす
る。このような構造にする理由は、ソース抵抗を
下げる為とゲートの全領域がゲート電極下に含ま
れるようにする為である。 First, as shown in FIG. 3, a GaAs layer 8 having one conductivity type is formed on a GaAs semi-insulating substrate 7 by a liquid phase epitaxial method, etc., and after mesa etching both sides of the GaAs layer 8, a gate is formed. Only the region to be used is etched halfway through the GaAs layer 8. The reason for this structure is to lower the source resistance and to ensure that the entire region of the gate is included under the gate electrode.
次に第4図に示すように、GaAs層8の全面
に、Alを例えば800Åの厚さに真空蒸着してAl薄
膜9を形成し、次いでオーミツク電極を形成すべ
き位置のAl薄膜9上に、レジストあるいは絶縁
薄膜である陽極酸化阻止膜10を形成する。 Next, as shown in FIG. 4, on the entire surface of the GaAs layer 8, Al is vacuum-deposited to a thickness of, for example, 800 Å to form an Al thin film 9, and then on the Al thin film 9 at the position where the ohmic electrode is to be formed. Then, an anodic oxidation prevention film 10, which is a resist or an insulating thin film, is formed.
次に、これを電解質溶液たとえば酒石酸、エチ
レングリコール及び水の混合液を用いて陽極酸化
し、第5図に示すようにAl薄膜9を絶縁体であ
るAl酸化膜11に変える。ただし、オーミツク
電極を形成すべき領域のAlは、陽極酸化阻止膜
10がある為に酸化されず、そこにはAl薄膜9
が残存している。 Next, this is anodized using an electrolyte solution, such as a mixture of tartaric acid, ethylene glycol, and water, thereby converting the Al thin film 9 into an Al oxide film 11, which is an insulator, as shown in FIG. However, the Al in the area where the ohmic electrode is to be formed is not oxidized because of the anodic oxidation prevention film 10, and there is an Al thin film 9 there.
remains.
ここで重要なことは、Al薄膜9が完全に陽極
酸化されるように然もGaAsがあまり陽極酸化さ
れないように、即ち、陽極酸化がちようどGaAs
層8とAl薄膜9との界面まで達するようにする
ことである。このようにしたときに最も界面準位
密度の小さい絶縁膜を得ることができる。ただし
実験に依れば、Al薄膜9の酸化終了後に多少
GaAs層8まで酸化が進んでも、界面準位密度は
充分小さい値であることが確認されている。従つ
て定電流源を用いた場合に、陽極酸化終了時の陽
極電圧がAlの酸化が終了する電圧とその1.1倍程
度の電圧との間の範囲であれば、界面準位密度は
充分低く押えられるものである。尚、AlとGaAs
の陽極酸化の速度が異なるため、陽極電圧の時間
的変化を記録計に書かせると、Alの酸化終了前
と終了後とでその傾きが異なるので、これを利用
して上記範囲内で陽極酸化を行なわせることもで
きる。また、AlとGaAsの表面反射率が異なるた
め、酸化膜下がAlのときは干渉色は示さない
が、下がGaAsのときは干渉色を示す。従つて、
干渉色が見えはじめることはAlの酸化が終了し
たことを示しており、光学的にAlの酸化の終了
を検出することも可能である。 What is important here is to ensure that the Al thin film 9 is completely anodized but that the GaAs is not anodized too much.
The purpose is to reach the interface between the layer 8 and the Al thin film 9. In this way, an insulating film with the lowest interface state density can be obtained. However, according to experiments, after the oxidation of the Al thin film 9 is completed, some
It has been confirmed that even if the oxidation progresses to the GaAs layer 8, the interface state density is a sufficiently small value. Therefore, when using a constant current source, if the anode voltage at the end of anodic oxidation is in the range between the voltage at which oxidation of Al ends and a voltage approximately 1.1 times that voltage, the interface state density can be kept sufficiently low. It is something that can be done. Furthermore, Al and GaAs
Since the rate of anodic oxidation of Al is different, when the time change of the anode voltage is recorded on a recorder, the slope is different before and after the oxidation of Al is completed.Use this to perform anodization within the above range. You can also have them do this. Furthermore, since the surface reflectance of Al and GaAs is different, interference colors are not shown when the oxide layer is made of Al, but interference colors are shown when the layer is made of GaAs. Therefore,
The appearance of interference colors indicates that the oxidation of Al has ended, and it is also possible to optically detect the end of the oxidation of Al.
さて、次に第6図に示すように、陽極酸化阻止
膜10を剥離し、この領域の未酸化のAlを例え
ばリン酸を用いて選択的にエツチング除去する。
一般に、Alの酸化物は薬品に対してきわめて安
定であり、Alの酸化物を形成後にそれをエツチ
ング等で加工することは容易でない。一方、Al
は酸を用いて容易に除去できるので、本発明によ
る方法を採用することにより、ソース、ドレイン
以外の領域にAlの酸化膜を選択的にきわめて容
易に形成することが可能となる。 Next, as shown in FIG. 6, the anodic oxidation prevention film 10 is peeled off, and unoxidized Al in this region is selectively etched away using, for example, phosphoric acid.
Generally, Al oxides are extremely stable to chemicals, and it is not easy to process Al oxides by etching or the like after forming them. On the other hand, Al
can be easily removed using acid, so by employing the method according to the present invention, it becomes possible to selectively and extremely easily form an oxide film of Al in regions other than the source and drain.
次に、上記工程で得られた素子を、N2雰囲気
中において例えば400℃で30分間熱処理する。熱
処理温度は熱処理時間によつても異なるが、30分
間の熱処理に対しては、300℃末満の熱処理温度
では界面準位密度が大きくなり、また500℃より
高い温度での熱処理では、電圧印加時に絶縁膜が
絶縁破壊を起し易くなる。従つて、実用上好まし
い範囲としてはほぼ300℃〜500℃である。 Next, the element obtained in the above step is heat-treated at, for example, 400° C. for 30 minutes in an N 2 atmosphere. The heat treatment temperature also varies depending on the heat treatment time, but for heat treatment for 30 minutes, the interface state density increases at a heat treatment temperature of less than 300℃, and for heat treatment at a temperature higher than 500℃, the voltage application At times, the insulating film becomes susceptible to dielectric breakdown. Therefore, the practically preferred range is approximately 300°C to 500°C.
次に、第7図に示すように、未酸化のAlをエ
ツチング除去した領域にAuGeNiなどのオーミツ
ク金属を被着し、ソース電極12及びドレイン電
極13を形成する。そして最後に第8図に示すよ
うに、ゲート領域部分のAl酸化膜11上に例え
ばAlのゲート電極14を形成する。ここで、
GaAs層8の幅狭く限定された領域15がゲート
領域になるものである。 Next, as shown in FIG. 7, an ohmic metal such as AuGeNi is deposited on the region where the unoxidized Al has been etched away to form a source electrode 12 and a drain electrode 13. Finally, as shown in FIG. 8, a gate electrode 14 made of, for example, Al is formed on the Al oxide film 11 in the gate region. here,
A narrow region 15 of the GaAs layer 8 serves as a gate region.
第9図は、以上のようにして製造したGaAsバ
ルク導電型MOS FETの直流ドレイン特性の一例
を表わす線図であり、同図に示すように、正負両
極性のゲート電圧に対しドレイン電流は同様に大
きく変化しており、本発明によるGaAsバルク導
電型MOS FETの界面特性が従来に比し格段に優
れていることが判る。 Figure 9 is a diagram showing an example of the DC drain characteristics of the GaAs bulk conduction type MOS FET manufactured as described above. As shown in the figure, the drain current is the same for both positive and negative polarity gate voltages. It can be seen that the interface characteristics of the GaAs bulk conduction type MOS FET according to the present invention are significantly superior to those of the conventional one.
このように本実施例方法は、GaAs層8上にAl
薄膜9を蒸着し、オーミツク電極を形成すべき位
置のAl薄膜9上にレジスト等の陽極酸化阻止膜
を形成したのちこれを陽極酸化することにより、
オーミツク電極を形成すべき領域以外のAl薄膜
9をAl酸化膜11に変化させるようにしたもの
であつて、陽極酸化がちようどAl薄膜9のみ行
なわれるように制御することにより、界面準位密
度の小さいゲート絶縁膜を形成することができる
ものである。 In this way, in the method of this embodiment, Al is formed on the GaAs layer 8.
By depositing the thin film 9, forming an anodic oxidation prevention film such as a resist on the Al thin film 9 at the position where the ohmic electrode is to be formed, and then anodizing this,
The Al thin film 9 in areas other than the area where the ohmic electrode is to be formed is changed to the Al oxide film 11, and by controlling the Al thin film 9 to be anodized only, the interface state density is increased. It is possible to form a gate insulating film with a small thickness.
以上説明したように、本発明に依れば、界面準
位密度の小さい良質なAlの酸化膜を、ソース、
ドレイン以外の領域に選択的に形成することがで
きるので、特性の優れたGaAsバルク導電型MOS
FETを確実に製造することができる利点があ
る。また、オーミツク電極を形成する領域を除
き、素子主面に装荷したAlを陽極酸化するた
め、ゲート絶縁膜を形成すると同時に他の領域の
不動態化(パツシベーシヨン)が同時に行なえる
という効果がある。従つて、本発明をGaAsバル
ク導電型MOS FETあるいはその集積回路に適用
すれば非常に有効である。なお、集積回路に適用
する場合には、Alを選択的に陽極酸化すること
によつて、ゲート絶縁膜の形成と同時にAlの配
線パターンを形成すれば、工程が簡略化されて有
効である。 As explained above, according to the present invention, a high-quality Al oxide film with a low interface state density can be used as a source,
GaAs bulk conduction type MOS with excellent characteristics because it can be selectively formed in regions other than the drain
There is an advantage that FETs can be manufactured reliably. In addition, since the Al loaded on the main surface of the device is anodized except for the area where the ohmic electrode is to be formed, the gate insulating film is formed and other areas can be passivated at the same time. Therefore, it is very effective to apply the present invention to GaAs bulk conduction type MOS FETs or their integrated circuits. Note that when applied to an integrated circuit, it is effective to form an Al wiring pattern simultaneously with the formation of a gate insulating film by selectively anodizing Al to simplify the process.
第1図はバルク導電型MOS FETの断面図、第
2図は従来方法を用いて製造したGaAsバルク導
電型MOS FETの直流ドレイン特性を示す線図、
第3図乃至第8図は本発明の実施例を説明する為
の工程図、第9図は本発明方法により製造した
GaAsバルク導電型MOS FETの直流ドレイン特
性の一例を表わす線図である。
7はGaAs半絶縁性基板、8はGaAs層、9は
Al薄膜、10は陽極酸化阻止膜、11はAl酸化
膜、12はソース電極、13はドレイン電極、1
4はゲート電極、15はゲート領域である。
Figure 1 is a cross-sectional view of a bulk conduction type MOS FET, Figure 2 is a diagram showing the DC drain characteristics of a GaAs bulk conduction type MOS FET manufactured using a conventional method.
Figures 3 to 8 are process diagrams for explaining examples of the present invention, and Figure 9 is a diagram showing the process of manufacturing according to the method of the present invention.
FIG. 2 is a diagram showing an example of DC drain characteristics of a GaAs bulk conduction type MOS FET. 7 is a GaAs semi-insulating substrate, 8 is a GaAs layer, and 9 is a GaAs semi-insulating substrate.
Al thin film, 10 is an anodic oxidation prevention film, 11 is Al oxide film, 12 is a source electrode, 13 is a drain electrode, 1
4 is a gate electrode, and 15 is a gate region.
Claims (1)
GaAs層を形成し該GaAs層のゲート領域部分を途
中までエツチングする工程と、前記GaAs層全面
にAl薄膜を形成する工程と、オーミツク電極を
形成すべき位置の前記Al薄膜上に陽極酸化阻止
膜を形成したのち前記Al薄膜を陽極酸化するこ
とによりオーミツク電極を形成すべき領域以外の
前記Al薄膜をAl酸化膜に変化せしめる工程と、
前記陽極酸化阻止膜を剥離後未酸化のAl薄膜を
エツチング除去する工程と、該工程後に熱処理す
る工程と、前記未酸化のAl薄膜をエツチング除
去した領域にオーミツク電極を形成し前記ゲート
領域部分の前記Al酸化膜上にゲート電極を形成
する工程とを含むことを特徴とする半導体装置の
製造方法。1 One conductivity type on GaAs semi-insulating substrate
A step of forming a GaAs layer and etching the gate region part of the GaAs layer halfway, a step of forming an Al thin film on the entire surface of the GaAs layer, and an anodizing prevention film on the Al thin film at the position where the ohmic electrode is to be formed. forming the Al thin film, and then anodizing the Al thin film to change the Al thin film other than the area where the ohmic electrode is to be formed into an Al oxide film;
A step of etching away the unoxidized Al thin film after peeling off the anodic oxidation prevention film, a heat treatment step after this step, and a step of forming an ohmic electrode in the region where the unoxidized Al thin film was etched away, and forming an ohmic electrode in the gate region portion. A method for manufacturing a semiconductor device, comprising the step of forming a gate electrode on the Al oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17154479A JPS5696863A (en) | 1979-12-29 | 1979-12-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17154479A JPS5696863A (en) | 1979-12-29 | 1979-12-29 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5696863A JPS5696863A (en) | 1981-08-05 |
| JPS6159674B2 true JPS6159674B2 (en) | 1986-12-17 |
Family
ID=15925085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17154479A Granted JPS5696863A (en) | 1979-12-29 | 1979-12-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5696863A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3456790B2 (en) * | 1995-04-18 | 2003-10-14 | 三菱電機株式会社 | Method of manufacturing semiconductor device and silicon substrate cassette for selective etching |
-
1979
- 1979-12-29 JP JP17154479A patent/JPS5696863A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5696863A (en) | 1981-08-05 |
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