JPS6249636B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a frequency control device for an electronic musical instrument. Conventionally, in order to reduce the capacity of a memory that stores frequency information, such as a ROM, information for one specific octave is stored, and information for other octaves is stored in the frequency information stored in this memory. , it is common practice to shift and generate according to the octave. However, in order to perform such a shift, a shift circuit for shifting data of many bits is required, which has the drawback of increasing the burden on hardware. The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a frequency control device for an electronic musical instrument that uses a simple circuit configuration to generate a scale clock corresponding to the scale frequency of a musical tone. The present invention will be described in detail below with reference to an embodiment shown in the drawings. FIG. 1 shows a schematic block circuit of this embodiment, and numeral 1 in the figure is a scale code generation circuit. This electronic musical instrument is an 8-tone polyphonic instrument, and scale codes for these 8 notes are sequentially output in a time-division manner. Incidentally, a scale code is generated and supplied to this scale code generation circuit 1 from a CPU (not shown), and is held in this scale code generation circuit 1. Then, from this scale code generation circuit 1, 4
A bit note code and a 2-bit octave code are output, and the above note code is a frequency
Applied to ROM2. That is, the frequency ROM 2 stores frequency information of, for example, 1 octave and 12 tones, and is accessed by a note code.
The upper 5 bits of data are supplied to a scale clock generation circuit 3, and the lower 4 bits of data are supplied to a gate circuit 4. The scale clock generation circuit 3 outputs a scale clock and supplies it to the waveform address generation circuit 5 under the control of the output of the gate circuit 4, the output of the frequency ROM 2, and the octave code that is the output of the scale code generation circuit 1. be done. The scale clock generating circuit 3 is shown in detail in FIG. 2 and will be described later. Furthermore, the scale clock is also provided to the gate circuit 4. The waveform address generation circuit 5 generates address data by counting scale clocks, and its output is applied to the musical waveform memory 6 and also supplied to the gate circuit 4. Next, the operation of the block circuit diagram shown in FIG. 1 will be explained. That is, the frequency information read out from the frequency ROM 2 based on the note code output from the scale code generation circuit 1 basically corresponds to the number of clocks between one step of the waveform. In other words, of the frequency information, the numerical value expressed in the higher-order data (now referred to as "n") is the basic number of clocks per step, and the numerical value expressed in the lower-order data (now referred to as "m") is the basic number of clocks in one step. ) is the number of corrections for each step. For example, if a tone waveform is stored in the tone waveform memory 6 with one cycle divided into 16 steps, this tone waveform will have a clock count of 16n+m when the octave is not considered.
This is the time width of the cycle. As described above, the number of clocks to be corrected is determined by this lower data, but the step at which the clock number is set to +1 is determined by the output of the waveform address generation circuit 5, that is, the waveform address output. Set by. Therefore, gate circuit 4
Now, the +1 signal is applied to the scale clock generation circuit 3 in steps corresponding to the address output of the waveform and the lower data of the frequency information. Next, detailed configurations of the scale clock generation circuit 3 and the gate circuit 4 will be explained with reference to FIG.
It should be noted that the positions of input and output signals in this drawing are different from those in FIG. 1. That is, the upper 5 bits of frequency information provided from the frequency ROM 2 are applied to input terminals A1 to A5 of the 5-bit full adder 7 via transfer gates G1 to G5. And this 5
Each output of the bitful adder 7 is applied to an 8-bit shift register group 8. Each register performs a read operation at clock _φ1 and a read operation at clock _φ2 . The output of this shift register group 8 is applied to AND gates 9-13, and the output of each AND gate 9-13 is applied to the input terminals B1-B of the 5-bit full adder 7.
given to 5. In addition, this AND gate 9-1
3, an inverted signal of the reset signal RE, which is normally a "0" signal, is applied. Therefore, at the time of reset, the contents of the shift register group 8 are cleared, and the output is transferred to the 5-bit full adder 7.
, AND gates 9-13 supply. Further, among the outputs of the shift register group 8, the least significant bit is applied to the inverter 14, and the other outputs are directly applied to the NOR gate 15. Further, this NOR gate 15 is supplied with a signal obtained by inverting a signal OS, which will be described later. The resulting output signal is supplied as a scale clock to the waveform address generation circuit 5, as well as to the gate circuit 4, and further to the NAND gate 16 and the NAND gate 17. The output of the gate circuit 4 is further supplied to the NAND gate 16 via an inverter 18, and the signal OS is applied thereto. The output of the NAND gate 16 is the 5-bit full adder 7.
is given to the carry input terminal of In addition to the scale clock, a signal OS is applied to the NAND gate 17, and its output is supplied to the AND gate 9 and is also applied via the inverter 20 as a gate control signal for the transfer gates G1 to G5. be done. Further, the output of the NAND gate 17 is directly applied as a gate signal to the transfer gates G6 to G10.
Note that this transfer gate G6 has a signal
OS is applied via the inverter 21, and a voltage signal V _D (signal "1") is supplied to the other transfer gates G7 to G10. The outputs of these transfer gates G6 to G10 are applied to input terminals A1 to A5 of the 5-bit full adder 7. Furthermore, the octave code given from the scale code generation circuit 1 is the octave signal Oct1, Oct
2, converted to Oct3 and applied to the gate circuit 22. Furthermore, this gate circuit 22 receives outputs A and B of 2-bit registers 23-1 and 23-2 which perform a latch operation at the timing of every 8th clock _φ8 (that is, output every 8 clocks _φ1 ). The signal is applied to the AND gates 16, 17 and the inverter 21 as a 1-bit output, that is, the signal OS, and is supplied to the NOR gate 15 as an inverted signal. When the octave signal Oct1 is at the "1" level, the gate circuit 22 outputs a signal obtained by ANDing the signal A and the signal B, and the octave signal Oct2 is at the "1" level. When the octave signal Oct3 is "1", a signal of "1" is normally output. Note that octave signal Oct3 corresponds to the highest octave, octave signal Oct2 corresponds to the middle octave, and octave signal Oct3 corresponds to the highest octave.
1 corresponds to the lowest octave. The signal A is applied to the register 23-1 via the NOR gate 24, and is also applied to one end of the exclusive NOR gate 25. Further, the signal B is applied to the exclusive NOR gate 25. The output of the exclusive NOR gate 25 is output from the NOR gate 26.
It is applied to the register 23-2 via the register 23-2. A reset signal RE is further applied to the NOR gates 24 and 26. Therefore, when the reset signal RE becomes "1" level, the register 23
-1 and 23-2 are reset, and thereafter, the reset signal RE becomes "0", so the registers 23-1 and 23-2 perform operations as described later. In addition, the gate circuit 4 converts the waveform addresses "0000" to "1111" into the following four types of signals, namely "***1", "**10", "*100", and "1000". and supplied. Note that this "*" means that it may be either "0" or "1". Furthermore, the F-order data (4-bit data) of the frequency ROM 2 is supplied to this gate circuit 4, and furthermore, the scale clock is supplied to this gate circuit 4. Therefore, when the scale clock is input, a 1-bit signal is output from the gate circuit 4 as shown in the following table, depending on the lower 4 bits of frequency information.

[Table] In the above table, "〇" indicates the timing when "1" output is obtained. For example, if the lower data of frequency information is "10", the address is "1", "3", " 4”, “5”, “7”, “9”, “
11",
Since the “1” signal is obtained from this gate circuit 4 at 10 points “12”, “13”, and “15”, the number of clocks is as follows.
It will be clocked by "+10" in one cycle of the waveform. Next, the operation of the circuit shown in FIG. 2 will be explained.
FIG. 4 shows the basic timing of the circuit shown in FIG. 2, and it is clear that each channel time varies every eight clocks. Therefore, since the processing of each channel is performed every 8 clocks, the minimum unit of the number of clocks of the waveform address is _8φ1 . The operation of one specific channel will be described below. First, when the output of the gate circuit 22 becomes "1" and the scale clock becomes "1", the output of the NAND gate 17 becomes "0", and therefore, by opening the transfer gates G1 to G5, the frequency information is The higher-order data is applied to the input terminals A1 to A5 of the 5-bit full adder 7. At that time, if the output of the gate circuit 4 is "1", the output of the NAND gate 16 is "1", or if the output of the gate circuit 4 is "0", the output of the NAND gate 16 is "0".
In either case, the 5-bit full adder 7
is applied to the carry input terminal Cin. At this time, the least significant bit of the output of the shift register group 8 is "1" and all bit outputs beyond that are zero, but the AND gate 9 is also closed by the output of the NAND gate 17. Therefore, in the end, the data supplied to the input terminals B1 to B5 of the 5-bit full adder 7 become all "0". In this way, when the scale clock outputs,
The frequency information is transmitted via the 5-bit full adder 7.
It is applied to the shift register group 8. Then, at the next channel time, the contents are output from the shift register group 8. The signals are then applied to input terminals B1 to B5 of the 5-bit full adder 7 via AND gates 9 to 13. At that time, if the output of the gate circuit 22 is "1" and the signal OS is "1", the NAND gate 1
6 output becomes "1" and is applied to the carry input terminal Cin, and the 5-bit data supplied via transfer gates G6 to G10 becomes "11110". Therefore, in the 5-bit full adder 7, the data output from the shift register group 8 is "-1".
The calculation is executed and the resulting data is stored in the shift register group 8 again. In this way, from the initially preset frequency information, each time the channel timing arrives,
When the "-1" operation is executed and finally the output of the shift register group 8 becomes "00001", the scale clock is output from the NOR gate 15, and the frequency information is transmitted again via the 5-bit full adder 7. , and will be preset in the shift register group 8. By the way, as shown in FIG.
When the output signals A and B of -1 and 23-2 change, for example, when the octave signal Oct2 is applied to the gate circuit 22, the signal A is output as the signal OS. Therefore, as the signal OS, When a "1" signal is output, the above-mentioned operation is performed, but when a "0" signal is output, the following operation is performed. That is, since the NAND gate 17 outputs a "1" signal, the AND gate 9 is opened and the transfer gates G6 to G10 are also opened. Since the signal supplied to the transfer gate G6 is "1", all "1" signals are output to the B input terminal of the full adder 7. Further, since the signal OS is "0", a "1" signal is applied to the carry input terminal Cin of the 5-bit full adder 7. As a result, the output of the shift register group 8 is applied to the shift register group 8 again via the AND gates 9 to 13 and the 5-bit full adder 7 without performing any calculations. Furthermore, even if the output of the shift register group 8 becomes "00001" when the signal OS is "0", the NOR gate 15 will always output a "0" signal because the signal is "1". Therefore, no scale clock occurs. In this way, when the octave signal Cct2 is "1", the timing to execute the "-1" operation from the first preset value is once every two cycles (8 channels x 2), and therefore , in the end, the frequency of the scale clock becomes exactly twice as long. Similarly, when the octave signal Oct1 is "1", a signal obtained by ANDing both signals A and B shown in FIG. 4 will be output from the gate circuit 22, and therefore "- 1" operation is executed by the 5-bit full adder 7 as described above.
This occurs once every cycle (8 channels x 4), and therefore, the period of the scale clock is exactly 4 times as long. In this way, in this embodiment, the "-1" calculation is repeatedly performed from the preset frequency information at a cycle corresponding to the octave of the musical tone, and when a predetermined condition is satisfied, a scale clock is generated.
Since the frequency information is preset again, it is now possible to generate a scale clock with a small amount of hardware, which is very effective. In the above embodiment, the 5-bit full adder 7
Although the "-1" calculation was executed in , the value can be changed as appropriate. Further, in the above embodiment, the electronic musical instrument is an 8-tone polyphonic instrument, but it may be an electronic musical instrument having a maximum simultaneous polyphony of more or less than that. As mentioned above, this invention has a simple configuration,
It has the advantage of being able to generate clocks of any octave and any scale without the need for a shift circuit, making it ideal for LSI implementation.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention; FIG. 1 is a block circuit diagram, FIG. 2 is a detailed view of the main part of FIG. 1, FIG. 3 is a diagram showing basic timing signals, and FIG. 4 is a diagram showing basic timing signals. The figure is a diagram showing a time chart of a specific control signal. 2... Frequency ROM, 3... Scale clock generation circuit, 7... 5-bit full adder, 8... Shift register group, 15... NOR gate, 23-1, 2
3-2...Register, 24, 26...Noah gate, 25...Exclusive Noah gate.

Claims (1)

[Claims] 1. A frequency information memory that stores frequency information of a specific octave, an addition/subtraction means in which frequency information is preset according to the note code of the musical tone read from the frequency information memory, and a musical tone from the frequency information preset in the addition/subtraction means. means for adding or subtracting a predetermined control value at a cycle according to an octave code; and when the output value of the adding/subtracting means satisfies a predetermined condition, outputting a scale clock and adding/subtracting the above-mentioned adding/subtracting means again; A frequency control device for an electronic musical instrument, comprising means for presetting frequency information read from the frequency information memory.