JPS5833713B2 - Non-volatile memory unit cell - Google Patents

Description

[Detailed Description of the Invention] Semiconductor memories have been developed using canine integrated circuits (hereinafter referred to as LSI) due to the fact that stored information can be easily retrieved as electrical signals at high speeds and the development of integrated circuit (hereinafter referred to as IC) technology. Due to its improved bit density and reliability, it has recently been used as a high-speed memory device for electronic computers.

However, unlike magnetic memories, semiconductor memories have the disadvantage that when the supply of bias power is cut off, the stored contents disappear (hereinafter referred to as volatility).

In order to obtain a semiconductor memory that does not have this drawback, research has been carried out on the memory function of semiconductor glasses such as chalcogenide glass, but this has not yet reached a practical stage.

In addition, silicon semiconductor I is used as a non-volatile semiconductor memory.
In the field of C, metal (M), silicon nitride film (N),
An MNO8 field effect transistor with a structure of silicon oxide film (0) and silicon (S) has been developed, but in this case, the silicon oxide film (S102) must be made thin enough to allow carriers on the semiconductor surface to tunnel through. Therefore, pinholes are likely to occur in this silicon oxide film, and since the storage mechanism is based on trap levels, there is a risk that productivity and reproducibility will be poor, so it has not been put to practical use in electronic computers.

However, as a field of semiconductor memory other than these, there is a read-only memory (hereinafter referred to as ROM) which takes advantage of the high bit density and high speed of semiconductor memory to read fixed storage contents.

There are two ways to configure this ROM, one of which is the IC
This is a method to imbue fixed information on the glass mask used for photo-etching when manufacturing.

Another method is to uniformly manufacture ICs regardless of the content to be stored, and then electrically write information in accordance with the content to be stored.

Three methods of the latter method are known.

That is, the first method is to fuse the wiring with a current pulse, the second method is to use the memory characteristics of alumina traps, and the third method is to cut the wiring using a MOS transistor when no channel current flows. Based on the avalanche timing of the junction between the drain and the semiconductor substrate, carriers having the same shape as the semiconductor substrate are injected into the oxide film, and the carriers charge the polycrystalline silicon thin film layer embedded in the oxide film to write information. This is how it was done.

The present invention relates to the third of these three methods, and the conventional method will first be described in more detail with reference to FIG.

In this case, as shown in FIG. 1A. In the substrate 1, a drain region 2 and a source region 3 having a conductivity type opposite to that of the substrate 1 and having a high impurity concentration, a gate silicon oxide film 4, and a silicon oxide film 4 and 5 are embedded. A field effect transistor 7 including a silicon polycrystalline layer 6 is formed.

In this field effect transistor 7, when the drain voltage is increased, a depletion layer 8 is formed from the drain region 2 into the substrate 1.
However, as shown by the arrow, the electric field is concentrated particularly in the lower part 9 of the silicon polycrystalline layer 6, and the electric field becomes higher than in other parts of the depletion layer 8, and finally reaches the critical point of avalanche deposition. reach the electric field.

At this time, electron-hole pairs of electrons 10 and holes 11 are generated in this portion 9 as shown in FIG. 1B, and the substrate 1 is
In the case of a shape, the electrons 10 are accelerated by the electric field in the direction of the oxide film 4 as shown by the arrow 12, thereby gaining high energy and being injected into the oxide film 4.

The electrons 10 injected in this manner pass through the oxide film 4 and reach the silicon polycrystalline layer 6, charging it negatively.

On the other hand, the holes 11 are transported to the drain region 2 as shown by an arrow 13 by the electric field.

In this way, information can be written by obtaining a charged state of the silicon polycrystalline layer 6, and on the other hand, information once written in this way can, in principle, be erased by irradiating the field effect transistor 7 with ultraviolet rays or X-rays. I can do it.

However, when such a semiconductor memory is generally used in an actual device, it is housed in a package and fixedly wired inside the device's casing. In practice, it is extremely difficult to take out the specimen and irradiate it with X-rays each time.
Furthermore, it is virtually impossible to selectively rewrite only arbitrary bits in memory.

Moreover, the unit cell configuration that can stably perform address selection during writing has not been clear.

Therefore, the present invention takes the above-mentioned points into consideration and aims to provide a nonvolatile memory unit cell in which information can be stably and reliably written.

Of course, the configuration of the present invention can also be applied to a nonvolatile memory unit cell in which information can be rewritten as is even when the package is incorporated into a device.

The present invention has the following configuration.

That is, a drain region and a source region formed in the first semiconductor region, a gate insulating film and an insulating film continuous thereto, deposited on the surface of the semiconductor region, and a gate insulating film and an insulating film continuous thereto. a memory nonvolatile field effect transistor having at least a first gate electrode embedded between the films; and an address selection insulator having a drain or source region connected to the source or drain region of the memory field effect transistor. a gate field effect transistor, and the gate insulating film of the address selecting field effect transistor is configured to be thicker than the gate insulating film of the memory field effect transistor to eliminate destruction or characteristic change of the address selecting field effect transistor. This is a non-volatile memory unit cell that enables stable and reliable writing.

Regarding the method of injecting carriers into the first gate electrode of the nonvolatile field effect transistor for storage used in the present invention, the following method can be newly considered.

For example, by selecting one of two types of carriers having different codes obtained in the semiconductor substrate depending on the information to be written, and injecting each carrier from the surface of the semiconductor substrate into the insulating film. , respectively, so that different states of charge can be obtained, and thus the memory contents can be erased or rewritten.

In addition, in the present invention, as a first method for injecting carriers in a semiconductor substrate into an insulating film, hot carriers are obtained in a pinch-off (high field velocity saturation) region of a channel of a field effect transistor and then injected. Adopt a method to do so.

Furthermore, in the present invention, as a second method for injecting carriers into an insulating film, two types of junctions are formed in a semiconductor substrate,
It is also possible to adopt a method of injecting the carrier obtained by sequentially causing avalanche precipitation in these junctions.

The features of the memory unit cell and related nonvolatile field effect transistor according to the present invention will become clear from the detailed description below in conjunction with the drawings.

First, referring to FIG. 2, an example of the storage method of the nonvolatile field effect transistor for storage used in the present invention will be described.
The memory field effect transistor 21 in this case has the same configuration as the field effect transistor 7 in FIG. 1, except that the second gate electrode 23 is provided on the insulating film 27 made of a silicon oxide film. .

In FIG. 2, 22 is a gate insulating film, 24 is a semiconductor substrate, 25 is a drain region, 26 is a source region, 27 is an insulating film continuous with the gate insulating film 22, and 28 is the gate insulating film 22 and the semiconductor substrate. The first gate electrode is buried between the insulating films 27, and 29 represents a depletion layer.

By the way, in order to inject carriers in the substrate 24 into the gate insulating film 22 of the field effect transistor 21, it is necessary to give enough energy to the carriers to cross the barrier between the substrate 24 and the insulating film 22. .

Therefore, in the case of FIG. 2, in order to obtain a charge state of 1 on the gate electrode 28, the field effect transistor 21 is put into a pinch-off state, and thereby the carriers become hot carriers at a position near the drain side of the channel and are transferred to the insulating film. Inject into 22.

On the other hand, in order to obtain a different charging state of the gate electrode 28, the drain voltage is increased to cause avalanche breakdown at the portion of the surface of the substrate 24 below the gate electrode 28 in contact with the drain region 25, thereby causing the case shown in FIG. Similarly, the depletion layer 2 of the substrate 24
The carriers generated in 9 are injected into insulating film 22 .

In this case, the sign of the charge of the carriers injected by the former is opposite to that of the latter, and therefore the gate electrode 28 in the above-mentioned first charged state is converted to another charged state with the opposite sign. I can do it.

Therefore, the information once written to the field effect transistor 21 (i.e., the gate electrode 28 is in a state of charge of 1) is erased, and the opposite information is written (i.e., the gate electrode 28 is in a different state of charge). can be done, and of course vice versa.

The above is the outline of the operation of the nonvolatile field effect transistor and the carrier injection method with respect to FIG. 2, and next, it will be described in more detail along with the structure for realizing this.

In FIG. 2, first, a potential is applied to the gate electrode 23 to generate an electric field as shown by the arrow between the gate electrode 23 and the buried gate electrode 28, and a potential based on this electric field is applied to the electrode 28.

On the other hand, a channel 30 is induced in the substrate 24, and a pinch-off region 31 is formed near the drain region 25 side of the channel 30.
form.

Therefore, an electric field as shown by the arrow is generated between the electrode 28 and the substrate 24.

In this state, between the carrier density no at the end of the channel 30 on the source region 26 side and the carrier density np at the pinch-off region 31, a relationship of current continuity is approximately established in the channel 30. Here, vo is the carrier velocity at the side edge of the source region 26,
Vp is the carrier velocity in the pinch-off region 31, and ■ is related to the channel current, so vp>V.

It is clear that

This means that in the pinch-off region 31, the carriers in the channel 30 have the highest energy among the carriers in the crystal.

In this specification, the pinch-off region has a broad meaning as a channel region where the carrier velocity of the channel is close to velocity saturation and has become so-called hot.

Therefore, compared to the potential of the electrode 28 buried in the insulating film 22, the potential of the region 31 is higher in the case of a P channel or lower in the case of an n channel, even if the absolute value of the drain voltage is large. The obtained carriers are drawn into the pinch-off region 31 and the electric field between the channel 30 or the pinch-off region 31 and the electrode 28 on the source side of the pinch-off region 31, are injected into the insulating film 22, are accelerated, and reach the electrode 28. As a result, the first gate electrode 28 is charged to the same polarity as the carriers in the channel 30.

Next, in this charging state, the potential of the second gate electrode 23 is removed, for example, to the same potential as the substrate 24, and a voltage higher than the breakdown voltage with the substrate 24 is applied to the drain region 25.

In this way, avalanche precipitation occurs between the drain region 25 and the substrate 24, which causes a charge having the opposite sign to that of the carrier charge previously injected from the channel 30, based on the electric field between the electrode 28 and the breakdown point. Carriers are accelerated in the direction of the electrode 28 and injected into the insulating film 22, eventually reaching the electrode 28.
will be charged with the opposite polarity from the previous charging state.

According to the first method described above with reference to FIG. 2, information can be written or rewritten as desired by simply changing the bias conditions of the memory field effect transistor as a memory element. This can be done reliably, and the information once written can be retained without applying a bias to the element.

Therefore, even when a large number of memory unit cells having storage transistors according to the first method are incorporated into an actual device, it is extremely easy to select desired bits and write or rewrite information individually. obtain.

Further, according to the configuration shown in FIG. 2 for realizing the first method, since the electrode 23 is provided, when carriers are injected from the pinch-off region 31, a potential that accelerates the injected carriers is applied to the electrode 28. As a result, the first gate electrode 28 can be sufficiently charged with a high carrier injection rate and efficiency, and a storage field effect transistor with good performance as a storage element can be obtained.

FIG. 3 shows a modification of the configuration shown in FIG. 2, in which the insulating film 2
The electrodes 33 embedded in the electrodes 2 and 27 have a so-called offset configuration in which they overlap only with a portion of the channel region.

According to this configuration, the effect shown in FIG. 2 is obtained, and the remaining portion of the channel region and the gate electrode 23 opposite thereto
Since an electric field 34 is formed directly between the pinch-off region 31 and the pinch-off region 31, the efficiency of carrier injection from the pinch-off region 31 can be further promoted by this electric field.

In this case, the electric field 34 can induce a channel 35 in the remaining portion of the channel region, so by changing and controlling the electric field 34, the field effect transistor 21 can be turned on and off more reliably than in the configuration shown in FIG. Operation can also be controlled.

FIG. 4 shows another modification of the structure shown in FIG. 2, in which a through hole 36 is provided in the electrode 33 across its thickness, so that the through hole 36 in the electrode 23 and the substrate 24 can be Since an electric field 37 is directly formed between the opposing portions, this electric field 37 induces a channel 38 in the region of the substrate 24 facing the through hole 36, and a pair of pinch-off regions 39 are formed at both ends of the channel 38. and 39'.

Therefore, the hot carriers in regions 39 and 39' are
Since the carriers are directly accelerated by the carriers, the injection speed and efficiency of the carriers can be further promoted.

Furthermore, FIG. 5 shows a modification of the configuration shown in FIG. 3, in which the electrode 3
4 has a configuration with both an offset structure similar to that shown in FIG. 3 and a through hole 36 similar to that shown in FIG. It also has the same effect.

Although I did not specifically mention FIGS. 2 to 5, in order to make the potential of the pinch-off region in these configurations suitable for reaching the buried second gate electrode, It is also effective to make the impurity concentration of the substrate in the pinch-off region and its vicinity higher than in other parts.

Next, a circuit example in which the storage transistor according to the first storage method described above is applied to an arbitrary address write/read memory (random access memory) will be described together with equivalent circuits shown in FIGS. 6 to 11.

In FIG. 6, numeral 41 indicates a unit cell among a large number of memory cells of the arbitrary address write/read memory, and the unit cell 41 has a "1" write/storage transistor Q1 and a "1" write/storage transistor Q1.
0” write transistor Q2, address selection transistor Q3, and “0” write address selection transistor Q4.
It is assumed that at least transistors Q1 and Q2 are formed on the same semiconductor substrate.

The transistor Q1 is the field effect transistor 7 shown in FIG. 1, and has a source S, a drain d, and a gate g, which correspond in sequence to the source region 3, drain region 2, and silicon polycrystalline layer 6 shown in FIG.

The transistor Q2 is a field effect transistor 21 according to the present invention shown in FIG. 2, and has a source S, which corresponds in sequence to the source region 26, drain region 25, first gate electrode 28, and second gate electrode 23 shown in FIG. It has a drain d, a first gate g1, and a second gate g2.

The drain d of the transistor Q1 is connected to the source (or drain) of the transistor Q3, the drain (or source) of the transistor Q3 is connected to the address selection line X, and the source S of the transistor Q1 is connected to the common ground line G.

Also, the source S of the transistor Q2 is connected to the source (or drain) of the transistor Q3, and the drain d of the transistor Q2 connects the drain (or source) to the address selection line
, the gates are connected to the sources (or drains) of the transistors Q4 connected to the rOJ write address selection line E, and the gate g1 of the first option is connected to the transistor Q1 within the insulating film.
A second gate 1'g2 is connected to the "0" write address selection line E to the gate g.

Further, the gate of the transistor Q3 is connected to the "1" write and information read address selection line W.

In such a configuration, when writing "1" information to the transistor Q1, a voltage Vx whose absolute value is larger than the drain-to-substrate breakdown voltage HH of the transistor Q1 is applied to the line X,
On the other hand, a voltage VW having an absolute value larger than the voltage HH is applied to the line W.

When such a bias condition is applied, the voltage 1 turns on the transistor Q3, and through this, the voltage 2 is applied to the drain d of the transistor Q1.

Therefore, as described above with reference to FIG. 1, avalanche breakdown occurs between the drain d and the substrate of the transistor Q1, thereby charging the gate g and the first gate g1 of the transistor Q2 connected thereto.

In this case, when the substrate is n-type, a negative charge is applied to the gate of the transistor Q1 and hence to the gate g1 of the transistor Q2.
When they are P-type, they are charged with positive charges.

Accordingly, transistors Q2 and Ql are then rendered conductive, with their respective gates maintaining their charged states.

Thus transistor Q1. "1" information is written in Q2.

Next, when writing "O" information using transistor Q2, apply voltage H to line X, which is lower than voltage HH but sufficiently higher than the pinch-off of transistor Q2, and
Apply a high voltage of about H.

Transistor Q4 is then fully conductive, through which voltage Vx on line The carriers flowing through the channel are charged to the first gate gi and hence to the gate of the transistor Q1.

The charge of the carrier at this time has the opposite sign to that of the charge charged to the gates of transistors Q2 and Ql when writing the above-mentioned "1" information, and therefore
1 (therefore Q2) is then made non-conducting.

Thus transistor Q1. "0" information is written to Q2.

In this way, "1" or "0" stored in transistor Q1
” When reading information, apply voltage H to line W.

In this way, transistor Q3 becomes conductive, but at the time of this conduction, when "1" is written in transistor Q1, since transistor Q1 is in a conductive state, a voltage is passed through line X - transistor Q3 - Q1 - line G. Current flows, while '
When "O" is written, transistor Q1 is non-conductive, so no current flows through it.

Therefore an external circuit (not shown) connected between lines X and G
By detecting the presence or absence of current at this time,
The memory contents are read out.

Unit cell 41 in the above write or read mode
The bias conditions are summarized in Table 1.

FIG. 7 shows another embodiment of the unit cell 41, in which case the source S of the transistor Q2 is disconnected from the source (or drain) of the transistor Q3 and connected to the line G in FIG. It has the following configuration.

Therefore, although corresponding parts are shown with the same reference numerals, in the case of FIG. 6, when writing "O", based on charging to the first gate g1 of transistor Q2, this continues until transistor Q1 becomes non-conductive. In contrast, in the case of FIG. 7, the gate gx can be sufficiently charged through the line G.

8 and 9, transistors Q2 and 04 of FIGS. 6 and 7 are replaced with a single transistor Q, in which case transistor Q is the same as that of FIG. The field effect transistor 21 has the so-called offset structure described above.

In this case, except that the drain d of the transistor Q5 is directly connected to the line X, the configurations are similar to those in FIGS. 6 and 7, respectively.

In these configurations, as described above with reference to FIG. 2, when the voltage at the second gate g2 is 0, the transistor Q5 is cut off because the channel 35 (FIG. 3) is not induced; When the voltage is close to the voltage HH, the channel 35 becomes conductive.

Therefore, transistor Q5 is similar to transistors Q2 and Q4.
Both of the functions (FIG. 6 or FIG. 7) can be achieved, and the structure of the unit cell as a whole can be simplified by reducing the number of transistors by one.

In these cases, the bias conditions shown in Table 1 may be applied.

In the configurations of FIGS. 6 to 9 described above, if the channel lengths of transistors Q2 and Q5 are made longer than the channel length of transistor Q1, and the current at the time of writing "0" is limited to a small value in advance, , the power consumption of the unit cell 41 as a whole can be miniaturized.

FIG. 10 shows still another example of the circuit of the unit cell 41.

In this case, the unit cell 41 includes an address selection and current limiting transistor Q7, and a writing and storage transistor Q7.
6.

Transistor Q7 is a conventional insulated gate field effect transistor, and transistor Q6 is a field effect transistor 21 with an offset structure as described above with respect to FIGS. 3 and 5.

The source S of the transistor Q6 is the drain (or source)
is connected to the source (or drain) of the transistor Q7 connected to the common address selection line W, and the drain d is connected to the common address selection line E.

On the other hand, the second gate g2 of the transistor Q6 is connected to the common address selection line EY, and the gate of the transistor Q7 is connected to the common address selection connection line Y.

In this configuration, bias conditions as shown in Table 2 are applied when writing "1" information to transistor Q6, when writing "0" information, and when reading out information.

In this way, when writing "1", avalanche breakdown occurs between the source S and the substrate of the transistor Q6, and as a result, the injected carriers charge the gate g1, thereby writing "1".
A write is performed, and a 10J write is performed by applying a dog voltage to line EY to pinch off transistor Q6, thereby charging gate g1 with injected carriers, and a read is performed by applying a dog voltage to line EY, pinching off transistor Q6, and charging gate g1 with the resulting injected carriers.
7 is made conductive, and as a result, depending on whether or not current flows through the transistor Q6, "1" information is read out if current flows, and "O" information is read out if it does not.

According to the configuration of FIG. 10, the number of transistors is only three, so that the unit cell 41 can be further simplified.

FIG. 11 shows still another embodiment of the unit cell 41. In this case, a transistor Q9 having the same channel type as the transistor Q8 is connected in parallel, the gate of the transistor Q is connected to the W line, and the gate g2 of the transistor Q8 is connected to the W line. It has the same configuration as the configuration shown in FIG. 10, except that the gates of Q8 and Q8 are connected to the Y line, respectively, and the X-ray EY is omitted.

In such a configuration, information is written to the transistor Q6,
Alternatively, the bias conditions for reading this are set as shown in Table 3.

Here, when writing "1" when the voltage of the line W is applied to the source S of the transistor Q6, the voltage of the Y line is 7 and therefore the voltage of the second gate g2 is O. H
-H
It is designed to increase by an amount corresponding to a fraction of H.

Then, a voltage of H or HH is applied to the line Y of all the units connected to the common line W, excluding the unit to which "1" should be written, and the specified address is The arrangement is such that a voltage of O or of the opposite sign is applied only to the line Y.

Therefore, when writing 11'', the transistor Q9 becomes conductive, through which the voltage on the line W is applied to the source S of the transistor Q6, and the voltage on the fifth line Y is applied to the second gate g2, and the voltage on the line W is applied to the source S of the transistor Q6. " is written.

Also, when writing "0", the transistor Q is
6 and Q8 are made conductive, and the voltage on line E is set to H to obtain the pinch-off state of transistor Q6.Furthermore, for readout, transistor Q8 is made conductive, and as a result, current flows through transistor Q6 or not. If it flows,
1", and if it does not flow, rOJ is read.

In order to allow two types of carriers to reach the buried gate electrode as needed according to the first storage method, carrier injection by avalanche of the junction between the drain and the semiconductor substrate or between the source and the substrate, and the channel on the semiconductor surface are performed. It has become clear that nonvolatile memory storage can be achieved by injecting carriers from the pinch-off region depending on the information to be written.

Although the memory transistors and unit cells for implementing this memory method have been described with reference to FIGS. 2 to 11, a second memory method that can be used in the present invention will now be described in detail.

The second storage method involves sequentially charging two types of charges to a substance embedded in an insulator, and creating two types of junctions with different impurity concentrations or materials under the embedded substance. Two different types of carriers are injected into the insulator by avalanche breakdown of the junction.

An example of a storage field effect transistor implementing such a method is shown at 45 in FIG.

The transistor 45 has a source region 26 and a drain region 25 of conductivity type opposite to that of the semiconductor substrate 24, and
Gate insulating film 22 on 4 and insulating film 27 continuous thereto
The first gate electrode 28 is buried in between, which is similar to the configuration shown in FIG. 1.

However, in this case, this source region 2 is placed in the source region 26.
A region 46 having a conductivity type different from that of 6 and having a high concentration of impurities is formed.

On the other hand, the impurity concentration of the source region 26 is the same as that of the gate electrode 2.
The thickness is selected to be low so that the depletion layer 47, which is thicker than the thickness of 8, extends between the source regions 26.

In the above configuration, if avalanche occurs in the region near the surface of the substrate under the gate electrode 28 at the junction between the drain region 25 and the substrate 24, it will occur in the same manner as described above with reference to FIG. Carriers from the substrate 24 are injected into the insulating film 22 from that region, thereby charging the electrode 28 to a 1 charge state.

On the other hand, if avalanche occurs in the region 48 under the electrode 28 at the junction between the source region 26 and the region 46 formed therein, the insulating film 2
2, the carriers in the source region 26 (their charges are
(sign opposite to that of the carriers injected from 4) is injected, thereby charging the electrode 28 to another charging state.

By obtaining different states of charge in this manner, information can be written using this field effect transistor 45, and the state of charge of one of the electrodes 28 can be rewritten to another state of charge (or vice versa). Each time you charge the battery, you can rewrite the memory contents as needed.

Therefore, the same effects as the above-mentioned first method can be obtained using this second method as well.

In the configuration shown in FIG. 12, the region 46 is the semiconductor substrate 24,
It is obvious that the same effect as described above can be obtained even if the junction is formed by a heterojunction, a Schottky junction, or the like formed of a material different from that of the source region 26.

Further, FIG. 13 shows an embodiment in which an emitter junction and a collector junction of a transistor are used as two types of Pn junctions.

In the figure, the buried electrode 28 is a part 1 of the junction between the emitter region 106 and the base region 105 (referred to as an emitter junction) in contact with the semiconductor surface via the gate insulating film 22.
09, a part of the surface of the base region 105 and the base region 1
The buried electrode 28 is disposed so as to cover a part 108 of the junction between the gate insulating film 22 and the collector region 102 (referred to as the collector junction) in contact with the semiconductor surface, and the buried electrode 28 is connected to the gate insulating film 22 and the insulating film connected thereto. It is embedded in 27.

By reverse biasing the emitter region 106 with respect to the base region 105 and causing avalanche breakdown at the surface portion 109 of the emitter junction, the base region 106
Majority carriers at 5 (holes in an npn transistor, electrons in a pnp t' transistor) are injected into the insulating film 22 and charge the buried electrode 28.

By reverse biasing the base region 105 with respect to the collector region 102 and causing avalanche breakdown at the surface portion 108 of the collector junction, majority carriers in the collector region 102 are injected into the insulating film 22;
The embedded electrode 28 is charged in a direction with a sign opposite to that described above.

These two charging states are set to "1" or "1" in the information, respectively.
A junction that causes avalanche surrender is selected depending on the information to be stored or written.

The information detection method is to determine "1" or "O" based on the magnitude of the collector current when a constant base current is passed.

This takes advantage of the fact that the current amplification factor of a bipolar transistor strongly depends on the surface condition of the base region.

In other words, the fact that the state of the surface of the base region below the buried electrode 28 depends on the charged state of the buried electrode 28 is used.

When the buried electrode is more positively charged, the current amplification factor of the npn transistor is smaller than in other charging states, and therefore the value of the collector current is also smaller than in other charging states.

The opposite is true for pnp transistors. 13th
In the bipolar transistor structure example shown in the figure, at least the emitter region 106, base region 105, and collector region 102 under the buried electrode 28 must be formed in this order so that the impurity concentration becomes smaller.

This is because the depletion layer spreads further toward the base region at the emitter junction and toward the collector at the collector junction, and carriers need to be injected from there.

However, the impurity concentration may be higher in the portions other than under the buried gate electrode 28 than in the base region 105, such as in the collector contact 107 and the collector buried layer 101.

Note that 104 is a region for base contact and for blocking a channel (which may occur on region 105), 103 is a separation layer, and 100 is a substrate.

Although FIG. 13 shows an isolated transistor structure, even if the isolation layer 103 and the collector buried layer 101 are not present and the collector region 102 is formed from the substrate, it is possible to fully perform the function as a memory element. It is.

Next, an example in which the storage transistor according to the storage method described above with reference to FIG. 12 is applied to an arbitrary address write/read memory will be described with reference to FIGS. 14 to 16.

In FIG. 14, 50 indicates one of the many memory unit cells in the memory, and the unit cell 50 includes an address selection transistor Qll, a storage transistor QIO,
It has a current limiting transistor Q1□.

As shown in FIG. 15 corresponding to FIG. 14, the transistor QIO has a drain d1, a source S, and a gate g1 corresponding to a drain region 25, a source region 26, and a first gate electrode 28 in this order.

In this case, the transistor Q12 forms a region 51 of a conductivity type different from that of the source region 26 (FIG. 15) of the transistor Q1o, and uses this region 51 as a drain d,
The region 46 is the source, and the gate electrode 5 on the gate insulating film 52
It consists of a field effect transistor with 3 as the gate.

As is clear from the above, the configuration in FIG.
Except for configuring the transistor Q1□ in 6.
It has the same configuration as FIG. 12.

The drain d of the transistor QIO is connected to the source (or drain) of a transistor Q11 whose drain (or source) is connected to a common write line W and whose gate is connected to a common address selection line Y, and whose source S is connected to a common ground. Connected to line G.

Further, the drain d of the transistor Q12, whose source is formed and connected within the source S of the transistor Q1o, and its gate g are connected to the common erase line E.

In the configuration shown in FIG. 14, the fourth
The bias conditions shown in the table are given.

In Table 4, H++ indicates a voltage higher than the breakdown voltage at the semiconductor surface of the junction in region 46 (Figure 15);
-- indicates a negative voltage whose absolute value is larger than the breakdown voltage of the drain junction of transistor QIO, and H- indicates a negative voltage whose absolute value is smaller than the breakdown voltage of the drain junction of transistor Q1o.

Also, in Table 4, transistors Q, O and Qll are p
Although the case where the channel and Q1□ are n channels is shown, if the signs of these channels are reversed, the voltages ■, ■E, and v
Just reverse the sign of Y.

In this way, when writing "1", the transistor Q1□ becomes conductive, and through this, the voltage VW of the line W becomes the transistor Q1o.
is applied to the drain d of the transistor Q1o, causing an avalanche breakdown at its drain junction, and the transistor Q1o becomes charged to "1".

In this way, "1" information is written into transistor QIO.

On the other hand, during rOJ writing, the transistor Q1□ becomes conductive, and through this, the region 4 in the source region 26 (FIG. 15)
The application of voltage 1E on line E to 6 causes avalanche breakdown at the junction between source regions 26 and 46, causing transistor QIO to be in the "O" charging state.

These states of charge are maintained as they are until they are switched to other states of charge.

Also, during reading, transistor Qll is turned on, but in this case, since the voltage applied to the W line is small, transistor Q1
No avalanche breakdown occurs at the drain junction of o, so that if current flows through transistor Qlo, a ``1'' can be read, and if no current flows, a ``0'' can be read.

In this way, the memo IJ Uni' according to the second storage method:
The same effect as described above with respect to the first method can also be obtained by using /tocell.

In Fig. 14, the gate of transistor Q1□ is connected to line E.
However, it will be obvious that the gate may be connected to another separately provided address selection line instead.

FIG. 16 shows a modification of FIG. 15, in which a diffusion layer 54 having the same impurity concentration as the drain region 25 is provided around the source region 26 of FIG.

In this way, it is possible to obtain the same effects as the configuration shown in FIG. 15, and also to effectively avoid the possibility that a parasitic channel will be formed.

In this case, contact may be made from the diffusion layer 54.

So far, we have described storage methods that can be used in the unit cell of the present invention, as well as examples of nonvolatile field effect transistors, nonvolatile bipolar transistor memories, and various unit cells.

Now, in the present invention, on the same semiconductor substrate on which the memory field effect transistor having the first gate electrode is formed,
When forming a memory unit cell by forming other transistors, the thickness of the gate insulating film of the transistor having a buried first gate electrode is larger than that of the address selection transistor having no buried first gate electrode. The thickness of the gate insulating film is increased.

In this way, the drain junction breakdown voltage of the address selection transistor can be made higher than the breakdown voltage of the transistor having the first gate, so when the drain or source junction of the storage transistor is avalanche breakdown when writing information. The transistor for address selection does not cause avalanche breakdown and can stably and sufficiently write information.

A circuit diagram of an embodiment of the unit cell 50 of the present invention using the nonvolatile transistor shown in FIG. 12 is shown in FIG. 17, and a cross-sectional view is shown in FIG. 18.

In this case, the unit cell 50 is a memory transistor Q13.
, address selection and current limiting transistors Q1 and Q
14.

In fact, a large number of unit cells 50 can be integrated on a common semiconductor substrate 60 as shown in FIG. 18 to form an integrated circuit.

Transistor Q13 is similar to field effect transistor 4 of FIG. 12, except that region 46 within source region 26 is electrically connected to substrate 60 via its extension 61.
It has the same configuration as 5.

Transistor Qll has its source region connected to transistor Q
It is common to the drain region 25 of No. 13, and consists of a drain region 62, a gate insulating film 63, and a gate electrode 64.

Further, the transistor Q14 includes a drain region 65 formed at one edge of the source region 26 of the transistor Q13, a source region 66, a gate electrode 67, and a gate insulating film 68.

The drain d of the transistor Q13 is the transistor Qll.
The source S is connected to the common "1" write line W through the transistor Q14, and the source S is connected to the common ground/write line E through the transistor Q14.
Further, the gates of transistors Qll and Q14 are connected to common address selection lines Y and EY, respectively.

In the unit cell 50 having the above-described structure, the bias conditions shown in FIG. 5 are applied.

In this way, when writing "1", "1" is written to transistor Q13 via transistor Qll, when writing "0", "O" is written via transistor Q14, and when reading, transistor Qll is written. and Q14 are both in a conductive state, and if current flows through transistor Q13, it becomes "1".
If the information does not flow, "0" information can be read respectively.

In this case, transistors Qll and Q14 limit the current flowing to the drain junction of transistor Q13 and the junction of region 46.

Note that in the configurations shown in FIGS. 12 and 18, the transistor 4
For example, a second gate electrode similar to the second gate electrode 23 in FIG. 2 may be provided on the insulating film 27 of Nos. The electric field can accelerate the carriers produced by avalanche, thereby increasing the writing speed.

In the above embodiments, the present invention will be specifically explained as follows.

That is, when forming a memory unit cell by forming other transistors on the same semiconductor substrate on which the memory field effect transistor having the first gate electrode 28 is formed, for example, as shown in FIG. In this case, the thickness of the gate insulating films 63 and 68 of the other address selection transistors Qll and Q14 which do not have a buried gate electrode is greater than the thickness of the gate insulating film 22 of the transistor Q13 having the buried first gate electrode 28. It thickens the texture.

This will reduce the drain junction breakdown voltage of the other transistors Q11 and Q14 to the transistor Q1 with the first gate.
By being able to make the breakdown voltage higher than the breakdown voltage of 3,
A memory unit cell with stable operation can be obtained.

As a result of an experiment using the field effect transistor 70 shown in FIG. 19, the relationship shown in FIG. 20 was obtained.

In this case, the semiconductor substrate 24 is made of n-type silicon with an impurity concentration of 5×10 13 /−, and the region 46 of the source region 26
The surface impurity concentration near the junction with is approximately 1016 particles/birth,
The thickness 11 of the gate insulating film (Sin2) 22 is approximately 1000 mm.
The thickness 12 of the insulating film (S 102) 27 is 1000 mm, the channel length is approximately 10 μm, and the buried gate electrode (S 102) is
When the voltage i) is “1” written to the substrate 24, O
■ to -4V equivalent, in case of "0" writing -4■ to O
■Measure the time required for the respective changes to correspond to the corresponding values, and apply the results to the second gate electrode 23 (AI) and the source region 2.
It is expressed as time t with respect to the terminal voltage ■G of 6(P).

In FIG. 20, symbol ■ indicates that the drain terminal and the source terminal S are grounded, a positive bias is applied to the substrate terminal B, and the reverse direction current of the junction between the source region 26 and the region 46 is set to 100%.
The curve obtained when μA is the symbol ■ is the board terminal B
The curves obtained are shown in the following diagrams, in which the drain terminal S is grounded, a negative bias is applied to the drain terminal, a slight negative bias is applied to the source terminal S, and the reverse current at the junction between the substrate 24 and the drain region 25 is 10 μA.

From this measurement result, firstly, it is possible to write and rewrite either "1" or rOJ information, and these memories are non-volatile, and secondly, the second gate electrode 2
It has been demonstrated that the write time can be significantly speeded up by providing 3, and thirdly that the write time decreases in inverse proportion to the avalanche current of the junction undergoing breakdown.

As described above, according to the present invention, the drain region and the source region formed in the first semiconductor region, the gate insulating film adhered to the surface of the semiconductor region and the insulating film continuous thereto, and the gate A non-volatile field effect transistor for storage having at least an insulating film and a first gate electrode embedded between the insulating film continuous with the insulating film, and a drain or a drain connected to the source or drain region of the field effect transistor for storage. an insulated gate field effect transistor for address selection having a source region, and the gate insulating film of the field effect transistor for address selection is configured to be thicker than the gate insulating film of the field effect transistor for storage to configure a nonvolatile memory unit cell. As a result, the following major effects occur.

In other words, since the voltage applied during writing and rewriting of the nonvolatile field effect transistor for storage can be set to the necessary and sufficient voltage, it is possible to ensure the writing and rewriting operations of the nonvolatile field effect transistor for storage and to ensure stable operation. It has the advantage of being able to

In the above description, the stored content is digital information of "1" and "O", but it is clear that it can also be used to store non-volatile analog information.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a field effect transistor used to explain a conventional information writing method, and FIG. 2 is a cross-sectional view of a field effect transistor for storage used to explain an example of a storage method of a nonvolatile field effect transistor used in the present invention. 3 to 5 are sectional views showing the structure of a memory field effect transistor for realizing the method of the present invention, and FIGS. 6 to 11 are sectional views showing the structure of a memory field effect transistor shown in FIGS. 2 to 5. FIG. 12 is an equivalent circuit diagram showing an example of a memory unit cell configured to include a field-effect transistor for storage, and FIG. 13 is a sectional view showing the configuration of a storage bipolar transistor for realizing the method of the present invention, and FIG. 14 shows an example of a memory unit cell configured including the storage field effect transistor of FIG. 12. Equivalent circuit diagrams, FIGS. 15 and 16 are cross-sectional views showing the configuration when the memory unit cell of FIG. 14 is formed on the same semiconductor substrate, and FIG. 17 is another example of the memory unit cell of FIG. 14. 18A and 18B are respectively a plan view and a sectional view taken along the line B-B of the memory unit cell shown in FIG. 17 in an integrated circuit, and FIGS. 19 and 20 are FIG. 3 is a diagram showing experimental results according to an example of the invention method. In the figure, 21, 45, 70... memory field effect transistor, 22... gate insulating film, 23...
...Second gate electrode, 24...Semiconductor substrate, 25...Drain region, 26...
Source region, 27...Insulating film, 28...
・First gate electrode, '29, 47... Depletion layer, 30, 35, 3B... Channel, 31°3
9, 39'...pinch-off area, 36...
...Through hole, 41.50...Memory unit cell, Q, ~Q14...Transistor.

Claims (1)

[Claims] 1 A drain region and a source region formed in a first semiconductor region, a gate insulating film and an insulating film continuous thereto, deposited on the surface of the semiconductor region, and the gate insulating film and an insulating film continuous thereto. a storage nonvolatile field effect transistor having at least a first gate electrode buried therebetween; and an address selection insulated gate having a drain or source region connected to the source or drain region of the storage field effect transistor. 1. A nonvolatile memory unit cell comprising a field effect transistor, wherein a gate insulating film of the address selection field effect transistor is made thicker than a gate insulating film of the storage field effect transistor.