JPH0219997B2 - - Google Patents
Info
- Publication number
- JPH0219997B2 JPH0219997B2 JP22618285A JP22618285A JPH0219997B2 JP H0219997 B2 JPH0219997 B2 JP H0219997B2 JP 22618285 A JP22618285 A JP 22618285A JP 22618285 A JP22618285 A JP 22618285A JP H0219997 B2 JPH0219997 B2 JP H0219997B2
- Authority
- JP
- Japan
- Prior art keywords
- copper foil
- inner layer
- hole
- holes
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 29
- 239000011889 copper foil Substances 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 10
- 238000007747 plating Methods 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 230000007547 defect Effects 0.000 claims description 5
- 239000007788 liquid Substances 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 28
- 239000000243 solution Substances 0.000 description 7
- 238000005553 drilling Methods 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 239000003054 catalyst Substances 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 239000012670 alkaline solution Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- SOCTUWSJJQCPFX-UHFFFAOYSA-N dichromate(2-) Chemical compound [O-][Cr](=O)(=O)O[Cr]([O-])(=O)=O SOCTUWSJJQCPFX-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000012286 potassium permanganate Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明はアデイデイブ法による多層配線板の製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a method for manufacturing a multilayer wiring board by the addi-dive method.
従来の技術
多層配線板は、両面に配線パターンを設けた内
層配線板と、銅張り積層板をプリプレグを介在し
て積層プレス法で積層した後、孔明けを行い、全
面に化学めつき及び電気めつきを施した後、エツ
チング処理して不用の銅箔を除去し外層回路を形
成して製造している。Conventional technology A multilayer wiring board is made by laminating an inner wiring board with wiring patterns on both sides and a copper-clad laminate using a lamination press method with prepreg interposed therebetween. After plating, an etching process is performed to remove unnecessary copper foil and form an outer layer circuit.
また、最近は、スルーホール用の孔明け加工を
行つた後、シーダー処理によるシーダーの付着を
行つたり、絶縁層を形成する際に絶縁樹脂にめつ
き触媒を添加しておき、無電解めつきのみでスル
ーホール回路を形成する方法が開発されている。
更には、外層回路とスルーホールを同時に無電解
めつきのみで形成する方法が開発されている。 Recently, after drilling through-holes, seeders are attached using seeder treatment, and when forming an insulating layer, a plating catalyst is added to the insulating resin. A method has been developed to form a through-hole circuit using only a laminate.
Furthermore, a method has been developed in which outer layer circuits and through holes are simultaneously formed only by electroless plating.
発明が解決しようとする問題点
多層配線板における重要な特性にスルーホール
の信頼性がある。特にスルーホール内での内層銅
箔とスルーホールめつきとの導通信頼性が重要で
ある。スルーホールの信頼性に最も影響する要素
にドリルで穴明け7する際に発生する熱の影響で
絶縁樹脂6が溶融し、内層銅箔4の切断端面に絶
縁樹脂6が付着し(スミヤという。)このスミヤ
8が残置していると、内層銅箔4とスルーホール
銅15との導通性を損い、冷熱サイクルを繰返す
と、このところでめつきが切断する事故の原因と
なる。他方、スミヤ除去を行う際に用いるスミヤ
処理液は銅に対する溶解作用があるので、内層銅
箔4が侵食され穴7の表面から内部に後退し(エ
ツチドバツクという。)欠陥部9Aができ、特に
電気めつきでスルーホールを形成するときに障害
になる。従つて通常はエツチドバツクが少なく、
かつスミヤ除去が確実に行える条件が求められて
いる。Problems to be Solved by the Invention An important characteristic of a multilayer wiring board is the reliability of through holes. In particular, the reliability of conduction between the inner layer copper foil and the through-hole plating within the through-hole is important. The insulating resin 6 melts under the influence of the heat generated when drilling 7 into the element that most affects the reliability of the through-hole, and the insulating resin 6 adheres to the cut end surface of the inner layer copper foil 4 (called smear). ) If this smear 8 remains, it will impair the conductivity between the inner layer copper foil 4 and the through-hole copper 15, and if the cooling/heating cycle is repeated, it will cause an accident where the plating breaks. On the other hand, since the smear treatment liquid used when removing smear has a dissolving effect on copper, the inner layer copper foil 4 is eroded and retreats from the surface of the hole 7 (referred to as an etched back) to the inside, creating a defective part 9A. It becomes an obstacle when forming through holes by plating. Therefore, there are usually few etched backs,
In addition, conditions are required to ensure smear removal.
問題点を解決するための手段
本発明は、内層配線板の上に絶縁層、接着剤層
を順次積層し、さらにめつきレジスト層を形成し
た後、スルーホール用の穴明けを行い、その後ス
ミヤ処理液でスミヤの除去を行う際にスミヤを若
干残置した状態で、内層銅箔を溶解する溶液で処
理し、スルーホール用の穴に面した内層銅箔の端
面に欠陥部を形成させ、スルーホール及び外層回
路を形成するための銅めつき処理を行う多層配線
板の製造方法である。Means for Solving the Problems The present invention involves sequentially laminating an insulating layer and an adhesive layer on an inner layer wiring board, further forming a plating resist layer, and then drilling holes for through holes. When removing smear with a processing solution, some smear remains, and the inner layer copper foil is treated with a solution that dissolves it, forming a defective part on the end surface of the inner layer copper foil facing the hole for the through hole, and removing the through hole. This is a method of manufacturing a multilayer wiring board that performs copper plating treatment to form holes and outer layer circuits.
内層銅箔を溶解する溶液としては、HBF4重ク
ロム酸塩素溶液又はNaF、H2SO4、CrO3系溶液
を用い、スミヤ処理液としてはKMnO4のアルカ
リ溶液や濃硫酸が用いられる。 As a solution for dissolving the inner layer copper foil, an HBF tetrachlorine dichromate solution or a NaF, H 2 SO 4 , CrO 3 based solution is used, and as a smear treatment liquid, an alkaline solution of KMnO 4 or concentrated sulfuric acid is used.
実施例
実施例 1
ガラス基材エポキシ樹脂1に触媒入り接着剤2
が塗布され、めつきレジスト3を除く箇所に内層
銅箔4が形成され、その上に絶縁層6、接着剤層
12が形成され、ドリルでスルーホール用の孔明
け7を行つた後、スミヤ8を過マンガン酸カリ50
g/、荷性ソーダ30g/からなるスミヤ処理
液で60℃、10分間浸漬し、いまだスミヤ8が点在
して残置されていることを確認し、CrO340g/
、H2SO4350g/、NaF35g/の溶液を用
い30℃、15分間浸漬して、内層銅箔4が第6図に
示す如く、少なくとも、スルーホール用穴7に面
した内層銅箔の端面4Aの一部を残置した状態で
テーパ状の欠陥部9Bを形成した端面形状にし
た。この後シーダー処理を行い、無電解めつき液
に浸漬してスルーホール15及び外層銅箔14を
形成して多層配線板20を製造した。Examples Example 1 Glass base epoxy resin 1 and catalyst-containing adhesive 2
is coated, an inner layer copper foil 4 is formed in the area excluding the plating resist 3, an insulating layer 6 and an adhesive layer 12 are formed thereon, and after drilling holes 7 for through holes with a drill, smearing is performed. 8 to potassium permanganate 50
It was immersed for 10 minutes at 60℃ in a smear treatment solution consisting of CrO 3 /30g/, and CrO 3 40g/
, H 2 SO 4 350 g/, NaF 35 g/ for 15 minutes at 30° C., so that the inner layer copper foil 4 is coated at least on the end surface of the inner layer copper foil facing the through-hole hole 7, as shown in FIG. An end face shape was formed in which a tapered defect portion 9B was formed with a portion of 4A remaining. Thereafter, a seeder treatment was performed, and the multilayer wiring board 20 was manufactured by immersing it in an electroless plating solution to form through holes 15 and outer layer copper foil 14.
実施例 2
実施例1において、CrO3、H2SO4、NaFの溶
液の代りに、HBF4550g/、Na2Cr2O725g/
の溶液を用い45℃で15分間処理し、第6図に示
す如く、少なくとも、スルーホール用の穴7に面
した内層銅箔4の端面4Aの一部を残置した状態
でテーパ状の欠陥部9Bを形成した他は実施例1
と同一製法で多層配線板を製造した。Example 2 In Example 1 , HBF 4 550 g/, Na 2 Cr 2 O 7 25 g/
As shown in FIG. 6, at least a part of the end surface 4A of the inner layer copper foil 4 facing the hole 7 for the through hole is left in the tapered defect area. Example 1 except that 9B was formed.
A multilayer wiring board was manufactured using the same manufacturing method.
比較例 1
実施例1において、同一のスミヤ処理液を用い
60℃、25分間の処理を行つた。スミヤ8が完全に
除去された後、スルーホールの銅めつきを行つ
た。Comparative Example 1 Using the same smear treatment liquid as in Example 1,
Treatment was performed at 60°C for 25 minutes. After the smear 8 was completely removed, the through holes were copper plated.
以上の実施例及び比較例の製造方法により製作
した多層配線板をホツトオイル(260℃、10秒)
を用い熱衝撃テストを行つた。その結果スルーホ
ールの抵抗値が10%を超えるサイクル数は
実施例1 60サイクル
実施例2 55サイクル
比較例1 40サイクル
となり、実施例1、2とともに従来の製法である
比較例より増加し、内層回路4との接続信頼性が
向上した。破壊テストを行つたところ、すべて内
層銅4とスルーホール銅15との界面で生じた。 Multilayer wiring boards manufactured by the manufacturing methods of the above examples and comparative examples were heated in hot oil (260°C, 10 seconds).
A thermal shock test was conducted using As a result, the number of cycles in which the resistance value of the through hole exceeded 10% was Example 1, 60 cycles, Example 2, 55 cycles, Comparative Example 1, and 40 cycles. The reliability of connection with circuit 4 has been improved. When a destructive test was performed, all of the defects occurred at the interface between the inner layer copper 4 and the through-hole copper 15.
発明の効果
本発明の多層配線板の製造方法によれば、内層
銅箔とスルーホール銅箔との接続が強まり、信頼
性の高い配線板が得られた。Effects of the Invention According to the method for manufacturing a multilayer wiring board of the present invention, the connection between the inner layer copper foil and the through-hole copper foil was strengthened, and a highly reliable wiring board was obtained.
第1図は本発明の方法で製造した配線板の断面
図、第2図は内層配線板の断面図、第3図乃至第
4図は従来の製造方法を示す断面図であり、第3
図はスミヤ処理前を示し、第4図はスミヤ処理後
の断面図、第5図及び第6図は本発明を示し、第
5図はスミヤを残置してスミヤ処理を行つた断面
図、第6図は内層銅箔処理液で処理した後内層銅
箔の端面がエツチドバツクした状態を示す断面図
である。
図面において、1:絶縁基板、4:内層銅箔、
6:絶縁層、7:穴明け、8:スミヤ、9:欠陥
部、10:内層配線板、14:外装銅箔、20:
多層配線板。
FIG. 1 is a sectional view of a wiring board manufactured by the method of the present invention, FIG. 2 is a sectional view of an inner layer wiring board, FIGS. 3 and 4 are sectional views showing a conventional manufacturing method, and FIG.
The figure shows the state before smearing, FIG. 4 is a sectional view after smearing, FIGS. 5 and 6 show the present invention, and FIG. FIG. 6 is a sectional view showing a state in which the end face of the inner layer copper foil is etched back after being treated with the inner layer copper foil treatment liquid. In the drawings, 1: insulating substrate, 4: inner layer copper foil,
6: Insulating layer, 7: Drilling, 8: Smear, 9: Defect part, 10: Inner layer wiring board, 14: Exterior copper foil, 20:
Multilayer wiring board.
Claims (1)
さらにめつきレジスト層を形成した後、スルーホ
ール用の穴明け加工を行い、スミヤ処理液で45〜
60℃で10〜15分間スミヤを若干残置した状態でス
ミヤ処理を行い、内層銅箔を溶解する溶液で処理
して少なくともスルーホール用の穴に面した内層
銅箔の端面の一部を残置した状態でテーパ状の欠
陥部を形成し、その後スルーホール及び外層銅箔
を形成するための銅めつき処理を行うことを特徴
とする多層配線板の製造方法。1 Form an insulating layer and adhesive on the inner layer wiring in sequence,
After forming a plating resist layer, holes are drilled for through holes, and smear treatment liquid is applied to
Smearing was performed at 60°C for 10 to 15 minutes with some smear remaining, and the inner layer copper foil was treated with a solution that dissolves it to leave at least a portion of the end face of the inner layer copper foil facing the hole for the through hole. 1. A method for manufacturing a multilayer wiring board, which comprises forming a tapered defect in a state, and then performing a copper plating process to form a through hole and an outer layer copper foil.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22618285A JPS62188298A (en) | 1985-10-11 | 1985-10-11 | Manufacture of multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22618285A JPS62188298A (en) | 1985-10-11 | 1985-10-11 | Manufacture of multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62188298A JPS62188298A (en) | 1987-08-17 |
| JPH0219997B2 true JPH0219997B2 (en) | 1990-05-07 |
Family
ID=16841170
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22618285A Granted JPS62188298A (en) | 1985-10-11 | 1985-10-11 | Manufacture of multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62188298A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0511142U (en) * | 1991-07-30 | 1993-02-12 | 博 久保 | Optical device holder |
-
1985
- 1985-10-11 JP JP22618285A patent/JPS62188298A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0511142U (en) * | 1991-07-30 | 1993-02-12 | 博 久保 | Optical device holder |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62188298A (en) | 1987-08-17 |
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