JPH0239109B2 - TASOHAISENBANNOSEIZOHOHO - Google Patents
TASOHAISENBANNOSEIZOHOHOInfo
- Publication number
- JPH0239109B2 JPH0239109B2 JP26794585A JP26794585A JPH0239109B2 JP H0239109 B2 JPH0239109 B2 JP H0239109B2 JP 26794585 A JP26794585 A JP 26794585A JP 26794585 A JP26794585 A JP 26794585A JP H0239109 B2 JPH0239109 B2 JP H0239109B2
- Authority
- JP
- Japan
- Prior art keywords
- smearing
- cro
- wiring board
- multilayer wiring
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010410 layer Substances 0.000 claims description 34
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 19
- 238000007747 plating Methods 0.000 claims description 18
- 239000000853 adhesive Substances 0.000 claims description 10
- 230000001070 adhesive effect Effects 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 239000007788 liquid Substances 0.000 claims description 5
- WGLPBDUCMAPZCE-UHFFFAOYSA-N Trioxochromium Chemical compound O=[Cr](=O)=O WGLPBDUCMAPZCE-UHFFFAOYSA-N 0.000 claims description 4
- 238000005553 drilling Methods 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims 1
- 239000012939 laminating adhesive Substances 0.000 claims 1
- 239000011889 copper foil Substances 0.000 description 9
- 239000000243 solution Substances 0.000 description 8
- 239000003054 catalyst Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は印刷配線板に関し特には多層配線板の
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to printed wiring boards, and more particularly to a method for manufacturing multilayer wiring boards.
従来の技術
従来の多層印刷配線板は両面に配線パターンを
有する内層配線板と、銅貼り積層板とをプリプレ
グを間に介在して重ね合わせ、積層プレスを用い
積層後、穴を明けて全面に化学銅めつきと電気銅
めつきを施し、その後エツチングレジストを塗布
し、不用の銅箔をエツチング処理して製造してい
る。Conventional technology A conventional multilayer printed wiring board consists of stacking an inner layer wiring board with wiring patterns on both sides and a copper-clad laminate with prepreg interposed between them, and after laminating them using a lamination press, holes are made to cover the entire surface. It is manufactured by applying chemical copper plating and electrolytic copper plating, then applying etching resist, and etching the unnecessary copper foil.
発明が解決しようとする問題点
従来の多層印刷配線板は、電気銅めつきで銅回
路層を形成し、ついでエツチング処理して回路を
形成しているために、銅が無駄に使用されてい
る。このため外層回路を形成する以外の箇所に、
めつきレジストを塗布し、スルーホールと外層回
路とを同時に無電解めつきで形成する方法を試み
た。Problems to be Solved by the Invention In conventional multilayer printed wiring boards, the copper circuit layer is formed by electrolytic copper plating, and then the circuit is formed by etching, which results in wasted use of copper. . Therefore, in places other than forming the outer layer circuit,
We tried a method of applying a plating resist and simultaneously forming the through holes and the outer layer circuit by electroless plating.
多層印刷配線板を製造する上で、最も重要な特
性は、スルーホールの信頼性である。中でもスル
ーホール内の内層銅箔とスルーホールめつき銅と
の導通信頼性が重要である。 In manufacturing multilayer printed wiring boards, the most important characteristic is the reliability of the through holes. Among these, the reliability of conduction between the inner layer copper foil in the through-hole and the through-hole plated copper is important.
スルーホールの信頼性に影響を与える要因とし
て、スミヤ除去処理の問題がある。配線板にスル
ーホール用の穴明けをドリルを用いて行うが、こ
の穴明け時の発熱で絶縁樹脂が溶融し、第３図に
示す如く、内層銅箔４の切断面に樹脂８が付着す
る（スミヤという）。このスミヤ８が残置すると
内層銅箔４とスルーホール銅との導電性をそこ
ね、配線板として冷熱サイクルが加わると断線事
故が発生し易い。従つてスミヤ８の除去処理が行
われている。 One of the factors that affects the reliability of through-holes is the problem of smear removal processing. A drill is used to drill holes for through-holes in the wiring board, but the heat generated during drilling melts the insulating resin, and as shown in FIG. 3, resin 8 adheres to the cut surface of the inner layer copper foil 4. (called Sumiya). If this smear 8 remains, it impairs the conductivity between the inner layer copper foil 4 and the through-hole copper, and when a wiring board is subjected to a cooling/heating cycle, a disconnection accident is likely to occur. Therefore, the smear 8 is removed.
このスミヤ処理は、スミヤ処理液に浸漬して行
つているが、このとき、内層銅箔４に対しても溶
解作用してエツチングがなされ、第４図に示す如
く穴７から内部に向つて後退するエツチドバツク
９現象が生じ、スルーホールめつきを形成する際
の障害になる。従つて、エツチドバツク９が少な
く、かつスミヤ８を完全に除去しうる条件が求め
られている。 This smearing process is performed by dipping it in a smearing solution, but at this time, the inner layer copper foil 4 is also dissolved and etched, retreating inward from the hole 7 as shown in FIG. An etched back phenomenon occurs, which becomes an obstacle when forming through-hole plating. Therefore, there is a need for conditions in which the amount of etched back 9 can be reduced and the smear 8 can be completely removed.
問題点を解決するための手段
本発明は、接着剤を塗布した絶縁板にめつきレ
ジストを塗布し無電解銅めつきを行つて内層回路
を形成し内層回路板となし、この内層回路板の上
に絶縁層、接着剤層を順次積層した後、貫通する
穴明けを行い、外層めつきレジストを塗布した
後、CrO3、H2SO4及びNaFからなるスミヤ処理
液でスミヤ処理を行い、無電解めつきを行つてス
ルーホールと外層回路を形成して多層配線板を製
造する。Means for Solving the Problems The present invention applies a plating resist to an insulating board coated with an adhesive, performs electroless copper plating to form an inner layer circuit, and forms an inner layer circuit board. After sequentially laminating an insulating layer and an adhesive layer on top, a penetrating hole is made, an outer plating resist is applied, and a smear treatment is performed using a smear treatment solution consisting of CrO 3 , H 2 SO 4 and NaF. Electroless plating is performed to form through holes and outer layer circuits to produce a multilayer wiring board.
作 用
このスミヤ処理液を用いることにより、接着剤
１２の表面粗化が行われるので外層回路の付着力
を高める効果があり、スミヤ処理する際にスミヤ
処理液としてCrO3を用いた後、CrO3、H2SO4及
びNaFのスミヤ処理液を用いることもよいこと
がわかつた。Effect By using this smearing liquid, the surface of the adhesive 12 is roughened, which has the effect of increasing the adhesion of the outer layer circuit. It has also been found that it is also effective to use a smearing solution of 3 , H 2 SO 4 and NaF.
実施例
実施例 １
めつき触媒入り絶縁基板１にめつき触媒入り接
着剤２を塗布した1.1mm厚のガラス基材エポキシ
樹脂積層板の所定箇所にめつきレジストインクで
スクリーン印刷し、30μm厚のめつきレジスト層
３を形成し、160℃、30分間加熱硬化し、粗化液
で接着剤２表面を化学粗化し、洗浄後無電解めつ
き液に浸漬し30μm厚の銅箔の内層両面銅箔４を
形成し、内層回路板１０をうる。（第２回）。Examples Example 1 A 1.1 mm thick glass-based epoxy resin laminate coated with a plating catalyst-containing insulating substrate 1 and a plating catalyst-containing adhesive 2 was screen printed with plating resist ink at predetermined locations. Form a plating resist layer 3, heat cure at 160°C for 30 minutes, chemically roughen the surface of the adhesive 2 with a roughening solution, wash it, then immerse it in an electroless plating solution to form a copper foil on both sides of the inner layer of a 30 μm thick copper foil. A foil 4 is formed and an inner layer circuit board 10 is obtained. (Part 2).
この内層回路板１０の内層銅箔４の表面を粗面
化処理し、この表面に絶縁層としてエポキシ樹脂
系インクをスクリーン印刷法にて40μm厚の絶縁
層６を形成し、160℃、70分間乾燥硬化し、更に
めつき触媒入り接着剤１２をカーテンコータ法で
30μm厚塗布し、160℃、90分間加熱硬化した。 The surface of the inner layer copper foil 4 of the inner layer circuit board 10 is roughened, and an insulating layer 6 with a thickness of 40 μm is formed on this surface using an epoxy resin ink as an insulating layer by screen printing, and then heated at 160° C. for 70 minutes. After drying and curing, apply the plating catalyst-containing adhesive 12 using a curtain coater method.
It was applied to a thickness of 30 μm and cured by heating at 160°C for 90 minutes.
この後ドリルでスルーホールの穴明け７を行
い、穴内にシーダ処理を行つた。次に外層回路を
形成するためのめつきレジスト層１３を形成し、
CrO340g／、H2SO4350ml／及びNaF28g／
からなるスミヤ処理液でスミヤ処理を行うと共
に、接着剤１２表面を粗化し、洗浄した後無電解
銅めつき液に浸漬して30μm厚の外層銅箔回路１
４とスルーホールとを形成して４層の多層配線板
２０を製造した。 Thereafter, a through hole was drilled 7 using a drill, and the inside of the hole was treated with seeder. Next, a plating resist layer 13 for forming an outer layer circuit is formed,
CrO 3 40g/, H 2 SO 4 350ml/ and NaF 28g/
At the same time, the surface of the adhesive 12 is roughened and washed, and then immersed in an electroless copper plating solution to form a 30 μm thick outer layer copper foil circuit 1.
4 and through holes were formed to produce a four-layer multilayer wiring board 20.
このスミヤ処理液の濃度はCrO3が30−60g／
、H2SO4が250〜450ml／及びNaFが20−40
ｇ／の範囲がのぞましい。 The concentration of this smearing solution is 30-60g/ CrO3 .
, H 2 SO 4 250-450ml/and NaF 20-40
A range of g/ is desirable.
この多層配線板２０は、ホツトオイルテスト
（260℃、10秒）を用いての熱衝撃テストでスルー
ホールの抵抗が10％増に達するサイクル数が60で
あつた。 This multilayer wiring board 20 was tested in a thermal shock test using a hot oil test (260° C., 10 seconds), and the number of cycles at which the through-hole resistance increased by 10% was 60.
実施例 ２
実施例１において、スルーホール用の穴明け後
にCrO3900g／液を40℃で15分間処理をし、ス
ミヤを除去した後、CrO3、H2SO4及びNaFのス
ミヤ処理液で処理した。この多層配線板はホツト
オイルテストで75サイクルもつた。Example 2 In Example 1, after drilling holes for through holes, 900 g of CrO 3 /liquid was treated at 40°C for 15 minutes to remove smear, and then treated with a smear treatment liquid of CrO 3 , H 2 SO 4 and NaF. Processed. This multilayer wiring board lasted 75 cycles in a hot oil test.
発明の効果
本発明は以上に述べた如く、スミヤ処理液とし
てCrO3、H2SO4及びNaFの混合液を用いること
により、スミヤ処理と接着剤の表面粗化が行われ
るので、内層回路をスルーホールとの接続性が高
まり、また外層回路の付着力が増加し、多層配線
板の信頼性が増加した。Effects of the Invention As described above, the present invention uses a mixed solution of CrO 3 , H 2 SO 4 and NaF as a smearing solution to perform smearing and roughen the surface of the adhesive. Connectivity with through-holes has improved, and the adhesion of outer layer circuits has also increased, increasing the reliability of multilayer wiring boards.
第１図は本発明の断面図、第２図は内層回路板
の断面図、第３図はスミヤが残置されている断面
図、第４図はスミヤ処理を行つた断面図である。
図面において、１：絶縁板、２：接着剤、１
０：内層回路板、６：絶縁層、８：スミヤ、１
２：接着剤、１３：レジスト、１４：外層回路、
２０：多層配線板。
FIG. 1 is a sectional view of the present invention, FIG. 2 is a sectional view of the inner layer circuit board, FIG. 3 is a sectional view with smear remaining, and FIG. 4 is a sectional view after smear treatment. In the drawings, 1: insulating plate, 2: adhesive, 1
0: Inner layer circuit board, 6: Insulating layer, 8: Smear, 1
2: adhesive, 13: resist, 14: outer layer circuit,
20: Multilayer wiring board.
Claims (1)
塗布し、無電解銅めつきを行い内層回路を形成し
て内層回路板となし、この内層回路板の上に絶縁
層、接着剤層を順次積層した後、回路板を貫通す
る穴明けを行い、外層めつきレジストを塗布した
後、CrO3、H2SO4及びNaFからなるスミヤ処理
液でスミヤ処理を行い、無電解めつきを行つてス
ルーホールと外層回路を形成することを特徴とす
る多層配線板の製造方法。 ２ スミヤ処理液としてCrO3を用い、次に
CrO3、H2SO4及びNaF溶液でスミヤ処理を行う
特許請求の範囲第１項記載の多層配線板の製造方
法。 ３ スミヤ処理液の濃度がCrO330〜60g／、
H2SO4250〜450ml／及びNaF20〜40g／であ
る特許請求の範囲第１項記載の多層配線板の製造
方法。 ４ スミヤ処理液のCrO3濃度が800〜1100g／
である特許請求の範囲第２項記載の多層配線板の
製造方法。[Claims] 1. A plating resist is applied to an insulating board coated with an adhesive, electroless copper plating is performed to form an inner layer circuit board, and an insulating layer is formed on the inner layer circuit board. After sequentially laminating adhesive layers, drilling a hole through the circuit board and applying an outer plating resist, smearing with a smearing solution consisting of CrO 3 , H 2 SO 4 and NaF, A method for manufacturing a multilayer wiring board, characterized by forming through holes and outer layer circuits by electrolytic plating. 2 Using CrO 3 as the smearing solution, then
2. The method of manufacturing a multilayer wiring board according to claim 1, wherein smearing is performed using CrO 3 , H 2 SO 4 and NaF solutions. 3 The concentration of the smear treatment liquid is CrO 3 30-60g/,
The method for producing a multilayer wiring board according to claim 1, wherein the amount of H 2 SO 4 is 250 to 450 ml/and NaF is 20 to 40 g/. 4 The CrO3 concentration of the smear treatment liquid is 800 to 1100g/
A method for manufacturing a multilayer wiring board according to claim 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26794585A JPH0239109B2 (en) | 1985-11-28 | 1985-11-28 | TASOHAISENBANNOSEIZOHOHO |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26794585A JPH0239109B2 (en) | 1985-11-28 | 1985-11-28 | TASOHAISENBANNOSEIZOHOHO |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62128196A JPS62128196A (en) | 1987-06-10 |
| JPH0239109B2 true JPH0239109B2 (en) | 1990-09-04 |
Family
ID=17451784
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26794585A Expired - Lifetime JPH0239109B2 (en) | 1985-11-28 | 1985-11-28 | TASOHAISENBANNOSEIZOHOHO |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0239109B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02234492A (en) * | 1989-03-07 | 1990-09-17 | Fujitsu Ltd | Manufacture of printed board |
-
1985
- 1985-11-28 JP JP26794585A patent/JPH0239109B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62128196A (en) | 1987-06-10 |
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