JPH0239110B2 - TASOHAISENBANNOSEIZOHOHO - Google Patents
TASOHAISENBANNOSEIZOHOHOInfo
- Publication number
- JPH0239110B2 JPH0239110B2 JP1849986A JP1849986A JPH0239110B2 JP H0239110 B2 JPH0239110 B2 JP H0239110B2 JP 1849986 A JP1849986 A JP 1849986A JP 1849986 A JP1849986 A JP 1849986A JP H0239110 B2 JPH0239110 B2 JP H0239110B2
- Authority
- JP
- Japan
- Prior art keywords
- inner layer
- plating
- smear
- board
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010410 layer Substances 0.000 claims description 36
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 20
- 238000007747 plating Methods 0.000 claims description 19
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- 239000000243 solution Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 7
- 239000000853 adhesive Substances 0.000 claims description 6
- 230000001070 adhesive effect Effects 0.000 claims description 6
- 238000007772 electroless plating Methods 0.000 claims description 5
- 229940117975 chromium trioxide Drugs 0.000 claims description 4
- WGLPBDUCMAPZCE-UHFFFAOYSA-N chromium trioxide Inorganic materials O=[Cr](=O)=O WGLPBDUCMAPZCE-UHFFFAOYSA-N 0.000 claims description 4
- GAMDZJFZMJECOS-UHFFFAOYSA-N chromium(6+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Cr+6] GAMDZJFZMJECOS-UHFFFAOYSA-N 0.000 claims description 4
- 239000002253 acid Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 239000012790 adhesive layer Substances 0.000 claims description 2
- CMMUKUYEPRGBFB-UHFFFAOYSA-L dichromic acid Chemical compound O[Cr](=O)(=O)O[Cr](O)(=O)=O CMMUKUYEPRGBFB-UHFFFAOYSA-L 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 239000012266 salt solution Substances 0.000 claims 1
- 239000011889 copper foil Substances 0.000 description 10
- 239000003054 catalyst Substances 0.000 description 4
- SOCTUWSJJQCPFX-UHFFFAOYSA-N dichromate(2-) Chemical compound [O-][Cr](=O)(=O)O[Cr]([O-])(=O)=O SOCTUWSJJQCPFX-UHFFFAOYSA-N 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000005553 drilling Methods 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 241000218645 Cedrus Species 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910052573 porcelain Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は印刷配線板に関し、特には多層印刷配
線板の改良に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to printed wiring boards, and more particularly to improvements in multilayer printed wiring boards.
従来の技術
従来の多層印刷配線板は、両面に配線パターン
を有する内層基板と銅貼り積層板とをプリプレグ
を間に入れて重ね合わせた積層プレスを行い、積
層後穴明け加工を行い、全面に化学銅めつきと電
気銅めつきを施し、その後エツチングレジストを
塗布し、不用の銅箔をエツチングして製造してい
る。Conventional technology Conventional multilayer printed wiring boards are made by stacking an inner layer board with wiring patterns on both sides and a copper-clad laminate board with prepreg interposed between them, then drilling holes after the stacking process is completed. It is manufactured by applying chemical copper plating and electrolytic copper plating, then applying etching resist, and etching the unnecessary copper foil.
発明が解決しようとする問題点
従来の多層印刷配線板は、電気銅めつきで銅層
を形成し、ついでエツチング処理して回路を形成
するために銅が無駄に使用している。このため外
層回路を形成する以外の箇所に、めつきレジスト
を塗布し、スルーホールと外層回路とを同時に無
電解めつきで形成する方法を試みた。Problems to be Solved by the Invention In conventional multilayer printed wiring boards, copper is wasted because a copper layer is formed by electroplating and then etched to form a circuit. For this reason, we attempted a method in which a plating resist was applied to areas other than those where the outer layer circuit was to be formed, and the through holes and the outer layer circuit were simultaneously formed by electroless plating.
多層印刷配線板を製造する上で最も重要なこと
はスルーホールの信頼性である。その中でもスル
ーホール内の内層銅箔とスルーホールめつき銅と
の導通信頼性である。 The most important thing in manufacturing multilayer printed wiring boards is the reliability of through holes. Among them, the reliability of conduction between the inner layer copper foil in the through hole and the through hole plated copper is important.
スルーホールの信頼性に影響を与える要因とし
て、スミヤ除去処理の問題がある。配線板にスル
ーホール用の穴明けをドリルを用いて行うが、こ
の穴明け７時の発熱で絶縁樹脂が溶融し、内層銅
箔４の切断面に樹脂が付着８（スミヤという）
し、このスミヤ８が残留すると内層銅箔４とスル
ーホール銅との導電性を損ね、冷熱サイクルが加
わると断線事故が発生し易い。このためスミヤ８
の除去処理が行つている。 One of the factors that affects the reliability of through-holes is the problem of smear removal processing. A drill is used to drill holes for through-holes in the wiring board, but the heat generated at the time of drilling 7 melts the insulating resin, and the resin adheres to the cut surface of the inner layer copper foil 8 (called smearing).
However, if this smear 8 remains, it impairs the conductivity between the inner layer copper foil 4 and the through-hole copper, and when a heating/cooling cycle is applied, a disconnection accident is likely to occur. For this reason, Sumiya 8
The removal process is in progress.
スミヤ８処理は、スミヤ処理液に浸漬して行う
が、このとき、内層銅箔４６溶解してエツチング
が行われ、穴７の表面から内部に後退するエツチ
ドバツク９現象が生じ、スルーホールめつきを形
成する際の障害になる。従つてエツチドバツク９
の量が少なくかつスミヤ８が完全に除去しうる条
件が求められている。 The smear 8 process is performed by immersing the inner layer copper foil 46 in a smear processing solution. At this time, the inner layer copper foil 46 is dissolved and etched, and an etched back 9 phenomenon occurs in which the inner layer copper foil 46 recedes from the surface of the hole 7 to the inside, which prevents through-hole plating. It becomes an obstacle when forming. Therefore, etched back 9
There is a need for conditions in which the amount of smear 8 is small and the smear 8 can be completely removed.
問題点を解決するための手段
本発明は、接着剤を塗布した絶縁板にめつきレ
ジストを塗布し、無電解めつきを行つて内層回路
を形成し、内層回路板を製造する。この内層回路
板の表面に絶縁層を接着剤層を順次積層する。こ
の後スルーホール用の穴明けを行い、この穴明け
後に三酸化クロム水溶液のスミヤ処理液を用いて
スミヤ処理を行い、穴内にシーダーを付着し、外
層パターン用めつきレジストを塗布し、硼弗化水
素酸と重クロム酸塩とからなるスミヤ処理液でス
ミヤ除去処理と接着剤粗化を同時に行い、無電解
銅めつきを行うことによりスルーホールと外層回
路を形成して多層配線板を製造するものである。Means for Solving the Problems In the present invention, a plating resist is applied to an insulating board coated with an adhesive, and electroless plating is performed to form an inner layer circuit, thereby manufacturing an inner layer circuit board. An insulating layer and an adhesive layer are sequentially laminated on the surface of this inner layer circuit board. After this, holes for through-holes are drilled, and after this hole-drilling, smearing is performed using a smearing solution of chromium trioxide aqueous solution, cedar is attached to the inside of the hole, plating resist for the outer layer pattern is applied, and the porcelain A smear treatment liquid consisting of hydrochloric acid and dichromate is used to simultaneously remove smear and roughen the adhesive, and electroless copper plating is performed to form through holes and outer layer circuits to produce multilayer wiring boards. It is something to do.
実施例
めつき触媒入り絶縁基体１にめつき触媒入り接
接着剤２を塗布した1.1mm厚のガラス基板エポキ
シ樹脂板の所定箇所にめつきレジストインクをス
クリーン印刷して30μm厚のめつきレジスト層３
を形成し、その後無電解めつき液に浸漬し30μm
厚の内層両面銅箔４を形成した内層基板１０を製
造する。Example A 30 μm thick plating resist layer is created by screen-printing plating resist ink on predetermined locations on a 1.1 mm thick glass substrate epoxy resin plate in which an insulating substrate 1 containing a plating catalyst is coated with an adhesive 2 containing a plating catalyst. 3
and then immersed in electroless plating solution to a thickness of 30 μm.
An inner layer substrate 10 on which a thick inner layer double-sided copper foil 4 is formed is manufactured.
この内層基板１０の表面にめつき触媒入りエポ
キシ樹脂系インクをスクリーン印刷法で150μm厚
の絶縁層６を形成し、160℃、70分間乾燥硬化し、
さらにめつき触媒入り接着剤１２をカーテンコー
タ法で30μm厚塗布し、160℃、90分間加熱硬化す
る。 An insulating layer 6 with a thickness of 150 μm was formed on the surface of this inner layer substrate 10 using a plating catalyst-containing epoxy resin ink using a screen printing method, and dried and cured at 160° C. for 70 minutes.
Further, a plating catalyst-containing adhesive 12 is applied to a thickness of 30 μm using a curtain coater method, and cured by heating at 160° C. for 90 minutes.
この後ドリルでスルーホールの穴明け７加工を
行い、三酸化クロム800−1100g／からなる水
溶液で40℃、５分間のスミヤ除去処理を行う。 After this, through-holes are drilled 7 using a drill, and smear removal treatment is performed at 40°C for 5 minutes with an aqueous solution containing 800-1100 g of chromium trioxide.
次に外層回路を形成するためのめつきレジスト
層１３を形成し、ついで硼弗化水素酸600〜
700g／、重クロム酸塩15〜25g／を混合した
スミヤ処理液で再度スミヤ除去処理（40℃、20
分）を行い、洗浄後無電解めつき液に浸漬して
30μm厚のスルーホールめつき及び外層銅箔回路
１４を形成し４層の多層配線板２０を製造する。 Next, a plating resist layer 13 for forming an outer layer circuit is formed, and then borohydrofluoric acid 600~
Smear removal treatment was performed again using a smear treatment solution containing 700 g/dichromate and 15 to 25 g/dichromate (40℃, 20
minutes), and after cleaning, immerse it in electroless plating solution.
A 4-layer multilayer wiring board 20 is manufactured by plating through holes with a thickness of 30 μm and forming an outer layer copper foil circuit 14.
この多層配印刷線板２０を用いホツトオイルテ
スト（260℃、10秒）を行つた結果、スルーホー
ル抵抗が10％を超えるサイクル数が55であつた。
かつ、内層銅とスルーホールめつき銅との接続性
は良好であつた。 A hot oil test (260° C., 10 seconds) was conducted using this multilayer printed wiring board 20, and as a result, the number of cycles in which the through-hole resistance exceeded 10% was 55.
Moreover, the connectivity between the inner layer copper and the through-hole plated copper was good.
発明の効果
本発明は以上に述べた如く、スミヤ処理液とし
て三酸化クロム処理液で処理し、次いで硼弗化水
素酸と重クロム酸塩の混合液を用いてスミヤ除去
処理を行つた結果、内層銅箔とスルーホールめつ
きとの接続信頼性が向上した。Effects of the Invention As described above, the present invention uses a chromium trioxide treatment solution as a smear treatment solution, and then performs smear removal treatment using a mixed solution of borofluoric acid and dichromate. The connection reliability between the inner layer copper foil and through-hole plating has been improved.
第１図は本発明の断面図、第２図は内層回路板
の断面図、第３図はスミヤが残留している断面
図、第４図はスミヤ除去した断面図。
図面において、１：絶縁板、２：接着剤、４：
内層回路、８：スミヤ、１０：内層回路板、２
０：多層配線板。
FIG. 1 is a sectional view of the present invention, FIG. 2 is a sectional view of an inner layer circuit board, FIG. 3 is a sectional view with smear remaining, and FIG. 4 is a sectional view with smear removed. In the drawings, 1: insulating plate, 2: adhesive, 4:
Inner layer circuit, 8: Smear, 10: Inner layer circuit board, 2
0: Multilayer wiring board.
Claims (1)
パターン形成し、無電解銅めつきを行つて内層回
路を形成して内層回路板となし、この内層回路板
の上に絶縁層、接着剤層を順次積層した後、回路
板を貫通する穴明け加工を行い、スミヤ処理液と
して三酸化クロムの処理液を用い、外層回路用め
つきレジストを塗布し、ついで硼弗化水素酸と重
クロム酸塩溶液でスミヤ処理を行い、無電解めつ
きを行つてスルーホールと外層回路を形成するこ
とを特徴とする多層配線板の製造方法。1 A pattern is formed using a plating resist on an insulating board coated with an adhesive, and an inner layer circuit is formed by electroless copper plating to form an inner layer circuit board.On top of this inner layer circuit board, an insulating layer and an adhesive layer are formed. After sequentially laminating the circuit boards, a hole is drilled through the circuit board, a chromium trioxide treatment solution is used as a smear treatment solution, a plating resist for the outer layer circuit is applied, and then borofluoric acid and dichromic acid are applied. A method for manufacturing a multilayer wiring board, characterized by performing smearing with a salt solution and performing electroless plating to form through holes and outer layer circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1849986A JPH0239110B2 (en) | 1986-01-30 | 1986-01-30 | TASOHAISENBANNOSEIZOHOHO |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1849986A JPH0239110B2 (en) | 1986-01-30 | 1986-01-30 | TASOHAISENBANNOSEIZOHOHO |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62176193A JPS62176193A (en) | 1987-08-01 |
| JPH0239110B2 true JPH0239110B2 (en) | 1990-09-04 |
Family
ID=11973313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1849986A Expired - Lifetime JPH0239110B2 (en) | 1986-01-30 | 1986-01-30 | TASOHAISENBANNOSEIZOHOHO |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0239110B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2579960B2 (en) * | 1987-10-13 | 1997-02-12 | 日立化成工業株式会社 | Manufacturing method of multilayer printed wiring board |
-
1986
- 1986-01-30 JP JP1849986A patent/JPH0239110B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62176193A (en) | 1987-08-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4770900A (en) | Process and laminate for the manufacture of through-hole plated electric printed-circuit boards | |
| US5444189A (en) | Printed wiring board and production thereof | |
| JPH0239110B2 (en) | TASOHAISENBANNOSEIZOHOHO | |
| JPH0239111B2 (en) | TASOHAISENBANNOSEIZOHOHO | |
| JPH0239109B2 (en) | TASOHAISENBANNOSEIZOHOHO | |
| JPH0239113B2 (en) | TASOHAISENBANNOSEIZOHOHO | |
| JPS648478B2 (en) | ||
| JPS62122196A (en) | Manufacture of multilayer wiring board | |
| JP2603097B2 (en) | Manufacturing method of printed wiring board | |
| JPS62266894A (en) | Manufacture of printed wiring board | |
| JPS584999A (en) | Manufacturing method for printed wiring boards | |
| JPS61239698A (en) | Multilayer printed wiring board | |
| JP2000151073A (en) | Manufacturing wiring board | |
| JPH03108794A (en) | Manufacture of printed wiring board | |
| JPH02238696A (en) | Method of improving adhesion between copper foil and resin | |
| JPS62268197A (en) | Manufacture of printed wiring board | |
| JPH0449795B2 (en) | ||
| JPS61121391A (en) | Printed wiring board | |
| JPS5884495A (en) | Method of producing metal core printed circuit board | |
| JPS61140197A (en) | Repair for multilayer printed wiring board | |
| JPH0239115B2 (en) | TASOHAISENBANNOSEIZOHOHO | |
| JPS62259497A (en) | Manufacture of printed circuit board | |
| JPS6178196A (en) | Manufacture of printed circuit board | |
| JPH0219997B2 (en) | ||
| JPS60107893A (en) | Method of producing printed circuit board |