JPH0234171B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention proposes a semiconductor device, particularly a MIS type (insulated gate type) field effect semiconductor device (hereinafter referred to as μ channel MIS.FET) having a microchannel type, and a semiconductor device in which a capacitor is connected to the MIS type field effect semiconductor device. be.

The present invention provides a convex first region that constitutes a capacitor by providing a conductor or a semiconductor having vertical side surfaces on an insulating film on a semiconductor substrate or an insulating film on a semiconductor layer on the substrate. Then, by using the step of the corner of the convex portion of the first region, a cross section is formed whose height is made to roughly match that of the first region, and whose width is made to roughly match the thickness of the coating to be formed at the corner. A MIS.FET is constructed by using a vertical, almost triangular layer as a gate electrode, and further providing a second region of the same conductivity type as the first region below the other end of this layer as a drain or source. It is something. Furthermore, it is characterized in that a capacitor is provided in the first region or within the first region at the same time.

Conventionally, the structure of a MIS.FET and a capacitor connected in series thereto is as shown in FIG.
and a drain or source 14 that is effectively a drain or source opposite to the source or drain 13 and constitutes the lower electrode of the capacitor.
Further, the lead 9, the capacitor insulator 15, and the counter electrode 7 were provided.

Conventionally, MIS.FETs have always had a pair of source and drain regions 13 and 14 formed on the same plane on a semiconductor substrate under both ends of a gate insulator. Further, this gate electrode 6 was provided not only on the gate insulator 11 but also over the upper surface of the counter electrode 7 of the capacitor. This provides self-alignment with one end of the source or drain 13 below one end 16 of the gate electrode, one end 18 of the drain or source 14 above the apparent gate electrode, and the other end 17 of the gate electrode This is a process in which polycrystalline silicon coatings 7 and 6 are made large to compensate for variations in mask alignment accuracy. However, even in such a case, the channel length is
It is impossible to reduce the channel length to less than 1 μm due to restrictions in the photoetching process, and in particular, due to the unevenness at the step portion 18, it is impossible to shorten the channel length because pattern breakage and the like occur. The present invention actively utilizes this step to the contrary.
A gate electrode of MIS.FET is provided, and this electrode is formed without extending above the opposing electrode of the capacitor.

In the present invention, the width corresponding to the channel length of the layer functioning as a gate electrode can be extremely small, 0.1 to 1μ, and the thickness is 0.5 to 1μ, which is thick and has a vertical, almost triangular shape. It has a longitudinally longer cross-sectional structure than the electrode.

In addition, since it is long in the vertical direction, its strength is not sufficient as it is. To compensate for this intensity, a first region is therefore provided along this layer. In addition, this first region is configured as part or all of the source or drain of the MIS.FET, and a capacitor made of a conductor, an insulator, and a conductor stacked inside this region is provided in series with the source or drain. It is characterized by

Therefore, the purpose of the semiconductor device of the present invention is to achieve high density for configuring its elements by proactively providing the elements in the height direction, rather than reducing the area in the lateral direction by scaling as in the past.

Examples of the present invention will be described below with reference to the drawings.

Example 1 The manufacturing process of this example is shown in Fig. 2.
N-channel MIS.FET that uses multiple carriers
This is an example of forming a capacitor.

Semiconductor substrate, for example silicon single crystal semiconductor 10
0, P type 10-500Ωmm was selected. A silicon nitride film with a thickness of 50 to 300 Å was formed on the substrate by a plasma nitriding method in which a reactive gas made by activating ammonia by induction energy was reacted at 800 to 1200°C.
The film having a masking effect against the oxidizing gas may be a multilayer film of silicon oxide, polycrystalline silicon, and silicon nitride. Thereafter, as shown in FIG. 2A, the silicon nitride was removed using a first photomask to use a selective oxidation method, and the area was made P, and a field insulator 2 was buried to a thickness of 0.5 to 2μ. Formed.

Furthermore, under this silicon nitride film 4, there is a thickness of 50 to 5000 Å.
The layer 20 was formed by doping As to a depth of 1000 Å or less by ion implantation and converting the vicinity of the interface to N.

This ion implantation damages not only the substrate but also silicon nitride, and since silicon nitride cannot be removed like silicon oxide by mere thermal annealing, induction energy is applied to forcibly remove the damage from silicon nitride. Alternatively, hydrogenation and nitridation of nitrogen dangling bonds were performed for 10 to 30 minutes. As a result, we were able to obtain an interface level of 10 ¹⁰ mm ^-2 , the same as before ion implantation.

Remove this silicon nitride film or replace it with another insulating film such as silicon nitride or tantalum oxide with a thickness of 100 to 500 Å.
The gate insulating film 11 and the capacitor dielectric 15 were formed to have a thickness of . Next, after thoroughly cleaning the surface of the insulating film, a low pressure vapor phase method (LPCVD) is applied onto the substrate.
A silicon semiconductor doped with an impurity of one conductivity type, for example, an N-type impurity, was formed to a thickness of 0.5 to 2.5 .mu.m by a method (method).

Furthermore, by using known photolithography, the edges around that side were selectively removed (anisotropic etching was performed) so that vertical edge sides were created without being side-edged, leaving the first region 3. . For example, a fluorine-based gas (e.g. _NF3 or
CF ₄ ) was applied perpendicularly to the substrate from above at a pressure of 0.001 to 0.01 torr for etching. As a result, I was able to cleanly cut the periphery of the board at an angle of 85 to 90 degrees perpendicular to the substrate surface. In this embodiment, the width of this first region is 3 to 200 microns. A portion thereof is formed over the field insulator 2, so that the capacitance of the capacitor 25 is large as in this embodiment, and the parasitic capacitance between the region 14 and the substrate 1 is made small. After this, a silicon oxide film 19 is formed on the top and side surfaces of this first region.
was formed to a thickness of 500 to 5000 Å. This silicon oxide film is oxidized using a high-pressure oxidation method using wet oxygen at 900-1100℃ and pressurized to 5-10 atm, or 0.001
It was formed by reducing the pressure to ~1 torr and generating plasma using high-frequency induction energy.

This coating 4 may be made of other insulating film such as alumina which is a metal oxide, and this first region is also not made of silicon doped with impurities, but is a multilayer of intrinsic or intrinsic and P ⁺ or N ⁺ type semiconductors. The membrane may also be a metal or a metal compound, in particular MO, W or a silicide thereof (Mo ₂ Si, W ₂ Si).

Next, openings 41 and 42 were formed using a photomask by a known plasma etching method using CF ₄ gas. Next, a conductor or semiconductor film 5 was formed on the upper surface by, for example, a low pressure CVD method to a thickness of 0.1 to 1 μm. In this coating 5, it is extremely important that the upper and side surfaces of the first region 3 forming the convex portion are formed to have a uniform thickness and a predetermined thickness. In this way, the thickness direction of the side periphery of the first region 3 is the same as the thickness of the coating 5, so the apparent thickness of that region from above the substrate is 2 to 5 times the thickness. It became possible to make the

For example, N ⁺ type silicon is 0.10~1.5μ, especially 0.3~0.7μ.
It was formed to a thickness of . The concentration and conductivity type of impurities added to this film generally depend on the degree of conductivity of this electrode 6 and the opening 4 between the film and the semiconductor substrate 1.
It is determined by the selection of ohmic contact type or PN junction type in 1 and the selection of whether the semiconductor substrate under this under-film gate insulator 11 is of depletion type or enhancement type.

In an N-channel type MIS.FET, for example, if the substrate 1 is P ^- type and the N-type layer 20 at the interface is made P to make it an enhancement type, then the coating 5 has B.
P ⁺ silicon may be used by adding it to a concentration of 10 ¹⁸ to 10 ²¹ cm ^-3 . In addition, in order to make ohmic contact between this film and the N-type first region 3 provided on the semiconductor substrate, in this embodiment, a region which is later formed by ion implantation and serves as a source or drain is used. a second region 13 whose end is approximately aligned with the end of the gate electrode and its lead 9;
Finally, the impurity necessary to make only the gate electrode part P ⁺ was added with ^an impurity at a concentration 5 to 50 times higher to cancel it out. Conversely, impurities are added to this film 5 to make it P ⁺ type, and the region that will become the lead 9 has a concentration of 5 to 100 times that.
N ⁺ may be formed in a subsequent step. Also the second
If the depletion type is used in which the region 13 and the gate electrode 6 are of the same conductivity type, the coating 5 may be N ⁺ and the openings 41 and 42 may be in ohmic contact.

In addition, when this coating 5 is made of a compound or mixture of silicon such as W ₂ Si, Mo ₂ Si, tungsten, molybdenum, etc., the coating is formed by LPCVD, electron beam evaporation, or reactive sputtering to a thickness of 0.3 to 1.5μ, especially
It is sufficient to form a layer with a thickness of 0.5 to 0.7μ.

Thus, Figure 2B was obtained.

Next, as shown in FIG. 2C, a photoresist (for example, OMR-83 manufactured by Tokyo Ohka) was coated on the upper surface of the area to be left as part of the film, and after exposure, photoetching was performed. Regarding this etching, it is important to use an anisotropic etching method with very little side etching and taper etching, or with less smudges, rather than the conventional etching method using a solution. Specifically, reactive gases for etching, such as nitrogen fluoride (NF ₃ ) and CF ₄ , are chemically activated using microwaves using 2.45 GHz, and the degree of vacuum is further reduced to 0.1 to 0.001 torr, especially 0.005 to 0.01. In an effort to completely eliminate side etching, a fluorine shower produced as plasma in a vacuum atmosphere of torr was flowed vertically from the top surface of the substrate.

As a result, when the flat portion of the coating 5 on which no photoresist is formed is completely removed, the first
The coating 8 around the side, which is the corner part of the area 3, is
It was possible to leave a vertical approximately triangular layer 6 around the sides. In addition, it was possible to configure and provide the counter electrode 3 of the capacitor on the insulating film 4. Further, in this embodiment, the contact 41 and its lead 9 in the portion that will become the second region can be left as an electrode lead 9 of N ⁺ type. Furthermore, the gate electrode 6 does not extend over the upper surface of the convex first region 3, and its width is not determined by photolithography, but is determined by the thickness of the side surface of the coating 5 and the degree of anisotropic etching. It has the characteristic that the channel length can be determined by the following.
This vertical almost triangular layer 6 has a width of 0.05~
The thickness is typically 1.0μ, typically 0.1 to 0.5μ, and the height is typically 0.3 to 2.5μ, typically 0.4 to 0.8μ. In particular, this width is a function of the film thickness of the coating 5 and the etching time and intensity when side etching is performed by plasma etching, but it is possible to obtain a very short channel of 0.05 to 1.0μ without using advanced technology such as electron beam exposure. (hereinafter referred to as a microchannel).

In FIG. 2C, the vertical approximately triangular layer 6 has a width of 0.1 to 1 μm, but the layer can be extended over the field insulator according to design needs, and its lead width It goes without saying that it may be provided with a width of 1 to 10μ and connected to the electrode leads of other MIS.FETs provided on the same board, or electrically connected to other electrode leads 9. . Furthermore, a metal having a masking effect may be formed on the upper surfaces of the electrodes 7 and leads 9, and the semiconductor underneath may be of N ⁺ type, and P ⁺ type impurities may be diffused into the gate electrode 6. In this case, in order to make the PN junction formed in the semiconductor layer essentially an ohmic contact, the PN junction is formed under the metal film above by lateral diffusion to the bottom of the lead extending from this electrode. This effectively eliminated the PN junction.

Next, as shown in FIG. 2D, arsenic, which is an N-type impurity, is implanted using an ion implantation method at an acceleration voltage of 30 KeV to form a second region 13 serving as a source or drain with an impurity concentration of about 10 ^{to 20} . It was formed on the upper part of the substrate, with the end approximately matching the position of the end of the vertical, substantially triangular layer 6. In addition, this region and the lead 9 were brought into ohmic contact.

Then, the first and second regions 14 and 13 could be formed into a μMIS.FET whose both ends substantially coincided with each other under both ends of the vertical, substantially triangular layer 6.

In addition, in order to bring the electrode or lead 9 into ohmic contact with the second region 13 acting as a source or drain, a further impurity diffusion layer is formed under the electrode to a depth of 50 to 2000 Å, and furthermore, the capacitor is Dielectric film 15 under the first region 3 which is the counter electrode
A depletion layer determined by the charge of the capacitor is provided below, and a drain or source 14 can be formed below these.

As is clear from the above embodiments, the present invention provides a vertical, approximately triangular layer 6 with a height (thickness) larger than the width.
is substantially larger, and its width is 0.1 to 1μ
It is possible to make it as small as 1Tr/cell by connecting capacitors in series.
Dymic RAM memory cells could be easily obtained.

Furthermore, since the layer 6 that becomes the gate electrode is thick, it becomes geometrically weak.
In addition, since unevenness tends to become severe, it was possible to electrically isolate it with the insulating film 4 and mechanically reinforce it by placing it on the convex first region. It is a feature.

As is clear in Figure 2D, 13.1
4 and the second region 13 are separated from each other by a vertical approximately triangular layer 6, one of which is used as a source, the other as a drain, and the layer 6 is used as a gate electrode, an extremely short channel (μ channel) type MIS. FET can be made. In addition, by using the first region 3 constituting the source or drain as one counter electrode and providing the electrode 14 under the insulating film 15, a capacitor 15 is connected in series to this MIS.FET.
A feature of the present invention is that a memory cell of 1 Tr/cell is provided.

Furthermore, lead 1 in the direction perpendicular to these leads 9 and 5
When the interlayer insulator 25 of 0 was formed of a polyimide-based insulator such as PIQ, the metal on the upper surface of the interlayer insulator 25 could be selectively oxidized by photolithography.

The present invention provides a μ channel MIS.
Another feature is that it can also be used as a 4.

Figure 2 E is a vertical cross-sectional view of MIS.FET6 in Figure 2 D.
and capacitor 15, and the memory cells are symbolized by corresponding numbers.

In the embodiment of the present invention, the conductivity type is that the substrate is P ^- type, the channel region 12 is N type, the first and second regions 13,
This is a μMIS.FET using so-called multiple carriers in which the gate electrode 14 is of N ⁺ type and the gate electrode 16 is of P ⁺ type.

However, the gate electrode is the same as the source and drain.
It may also be an N ⁺ type MIS.FET.

It can also be used as an enhancement type or depletion type MIS.FET using bulk minority carriers with P type in the channel region, N ⁺ type in the first and second regions, and P ⁺ or N ⁺ gate electrode. good.

Figure 1 shows a 1Tr/cell dynamic RAM memory formed on a substrate using one MIS.FET and one capacitor, but other MIS.FETs are placed on the same substrate in other parts separated by field insulators. The so-called
The present invention can be further promoted by using LSI or VLST.

Example 2 FIG. 3 shows another embodiment of the invention.

That is, a semiconductor substrate 1 having a conductivity type of P ^- type was subjected to plasma nitridation at 800 to 1200° C. to form a silicon nitride film with a thickness of 50 to 250 Å on the surface. Further, the nitride film was selectively removed with a buffer etchant by photolithography using a first photomask. Further, only the removed area was heated and oxidized at 600 to 1100°C in water vapor pressurized to 5 to 15 atmospheres, and a field insulating film 2 was buried to a thickness of 0.3 to 2 μm. . Further, the upper part of the field insulator may be removed at the same time as the nitride serving as a mask using a 30 to 50% buffered etchant to make the upper surface flat.

After this, in FIG. 3A, a first layer is placed on the semiconductor substrate 1 over the field insulator 2 on the right side.
Region 3 was formed.

This first region is made of tantalum oxide, silicon nitride, titanium oxide or the like, with a semiconductor layer 30 doped with a highly concentrated impurity of N ⁺ type conductivity to a thickness of 0.05 to 0.2 in the lower part, and further laminated on the upper surface thereof. A ferroelectric film 31 was formed, and a counter electrode 32 made of a conductor or semiconductor was formed on the upper surface thereof.

The height of this first region 3 is the same as in Example 1.
The size was 0.5 to 2.5μ, and the total area was determined based on the capacity required in the design. The present invention is characterized in that the area of contact with the semiconductor substrate 1 is small in order to eliminate parasitic capacitance with the substrate, and a capacitor is provided across the field insulator. In addition, this embodiment differs from the first embodiment in that the dielectric 31, electrode 30, and counter electrode 32 of the capacitor all constitute the first region.

In order to provide a capacitor, the first region may be a semiconductor layer, and a silicon oxide or silicon nitride insulating film may be formed by adding oxygen or nitrogen at a high concentration to a predetermined portion from the upper surface of the semiconductor layer.

In FIG. 3B, the upper surfaces of semiconductor substrate 1 and first region 3 were further oxidized or nitrided in the same manner as in Example 1 to form insulating film 4. Of course, this insulating film 4 may be formed by a vapor phase method or a vacuum evaporation method. Furthermore, if the first region 3 is a semiconductor or conductor of a different type from the substrate, it will be an oxide or nitride of the semiconductor or conductor, and it goes without saying that the first region 3 will be an insulating film of a different type from the insulating film on the surface of the substrate.

Furthermore, in FIG. 3B, similarly to Example 1, openings 41 and 42 were formed using a third photomask, and a coating 5 for forming a vertical, substantially triangular layer 6 was formed thereon. Thereafter, as shown in FIG. 3C, a second region 13 serving as a source or a drain is inserted into the upper part of the lower substrate by penetrating this film 5 by ion implantation using the side peripheral part 8 of this film 5. Formed by injection. This region had the same conductivity type as layer 30. Next, using anodic oxidation or a selective oxidation method, the other parts except for the electrodes/leads 9 and 45 were selectively oxidized using a fourth photomask and a photoresist to form an insulator 44 such as silicon oxide. At this time, vertical, substantially triangular layers 6, 8' are formed around the side of the first region 3. This layer 6 was then made to function as a gate electrode, and the other layer 8' was again oxidized and eliminated by the fifth photolithography technique. In the mask process, the leads 9 and contacts 45 can be made at the same time as the gate electrode 6 and can be connected to the gates, sources, and drains of other MIS.FETs on the same substrate.

As shown in FIG. 3C, in order to more precisely match the lower ends of the field insulating film 2 and the vertical approximately triangular layer 6, the second region 13 and the lower side of the first region 3 are The diffusion layer 14 may be formed by heat treatment. and each area 13
and a μ-channel MIS.FET in which 14 or 3 is a source and a drain or a drain or a source, and a vertical approximately triangular layer 6 is a gate electrode.
I was able to make it.

In FIG. 3D, the third lead 1 is removed using a photomask using the interlayer insulator 36.
0 is set.

This MIS.FET had an N ⁺ 13-P (channel forming region under the gate electrode) -N ⁺ 14 or 30 structure using minority carriers in the substrate. However, as in Example 1, multiple carriers of the substrate are also used.
It may be N ⁺ 13-N (channel formation region under gate electrode 6)-N ⁺ (14 or 30). Alternatively, a C/MIS.FET structure may be used in which a plurality of C/MIS.FETs are provided relative to each other.

Furthermore, since the leads 5 and 9 were provided on the field insulator 2, it was extremely easy to integrate a plurality of MIS.FETs.

Assuming that FIG. 3E is an electrical equivalent circuit of FIG. 3D, the electrode 6 is of N ⁺ type, and the capacitor 31 is partially formed inside the first region, and is connected to the lower electrode. 30 upper counter electrode 32 dielectric 31, furthermore, this lower electrode is μ channel MIS.FET.
By using both sources and drains, it was possible to create high-density memory cells (1Tr/cell). Further, when mask aligning the first region using a photomask, most of the first region can be provided over the upper surface of the field insulator 2. Therefore, the width of the region where the diffusion layer 14 exists which can be substantially formed under the first region 3 is set to 0.3 to 3 μm.
It can be made extremely narrow. Therefore, the parasitic capacitance between the layer 14 and the substrate could be extremely reduced.

Furthermore, the gate electrode 6 and the source or drain can be fabricated by using the electrodes and leads 5 and 9 without requiring any special process. Being able to perform photo etching,
It is characterized in that two-layer wiring can be implemented in the X and Y directions, and only seven types of masks are required.

Example 3 FIG. 4A shows another embodiment of the invention.

FIG. 4A shows Embodiment 2 with even more layers. That is, a second region 13 and a pair of first regions 3, 3' are provided symmetrically thereto. The first region is provided partially over the field insulator 2, and the μ-channel MIS.FET is configured as a source or drain 13, gates 6, 6', drains or sources 14, 14, ′
A lower electrode 30, 30' of the capacitor, a dielectric 31, 31', and an upper counter electrode 32, 32' of the capacitor are provided through the capacitor. In the drawing, reference numerals 13 and 9 indicate bit lines, which are part of a memory system having a structure in which two 1Tr/cells are paired with lead lines 6 and 6'.
With such a structure, the second region can be shared, and the dielectrics 31 and 31' are made of a material with a high dielectric constant different from the gate insulating film, such as tantalum oxide,
It has the special feature of being able to use barium titanate, etc. In this embodiment, the outer periphery of the gate electrodes 6, 6' is insulated by the oxide insulator 24, which has a thickness of 0.01 to 0.3 μm, and the outer periphery of the gate electrode 6, 6' is insulated by an interlayer insulator 36 such as polyimide. was formed, and a third conductor layer 9 was formed on the upper surface thereof.

Example 4 This example is shown in longitudinal section in FIG. 4B.

As is clear from the drawing, the first region 3 is provided in a convex manner on the surface of the semiconductor substrate in close contact with the surface of the semiconductor substrate, an insulating film is provided around the side thereof and at the corner of the substrate, and gate electrodes 6, 6 are provided. ' form a pair. A part of the gate electrode made of silicon is oxidized to form a silicon oxide 24, and a second region of the same conductivity type as the first region 3 is formed by ion implantation.
The areas 13 and 13' are symmetrically provided. In this way, μ-channel MIS.FETs were provided in a structure that formed two pairs.

Next, since the contact openings 41 and 41' provided in a part of this first region are provided in the same manner as in the first embodiment, the dielectric lower electrode 30 is It was formed to have a thickness of 1μ. Furthermore, the surface of this tantalum is oxidized by a precise anodization method to form a dielectric film 31.
It was formed to a thickness of 100 to 500 Å. Thereafter, a counter electrode 32 made of metal or semiconductor is provided on this surface, and this is photoetched, and then this electrode 32 is etched and the lower electrode is again formed of porous tantalum oxide by anodization. An insulating film 39 was used.

Thus the upper electrode 32,3 of the capacitor
2', dielectrics 31, 31' and lower electrode 30,
30' could have approximately the same shape.
In addition, this capacitor can be provided over the field insulating film or the insulating film 24 on the gate electrode, and if necessary, it can be provided over the first region 3. At this time, this region, the gate electrode Since the electrode is convex, it is difficult to apply photo-etching techniques, but in the embodiment of the present invention, the upper electrode 32 is formed with rough photo-etching precision, and the dielectric is formed in a self-aligned manner using the upper electrode 32. Making the lower electrode and the lower electrode into the same shape by anodizing was extremely effective in reducing the size, increasing density, and improving reliability.

In this embodiment as well, similar to Embodiment 3, a high dielectric constant material such as tantalum oxide can be used as the dielectric material, and the bit line is the region 3 and the word line is the 1Tr which forms a pair with the gate electrodes 6 and 6'. /cell could be configured as part of the memory system.

All of the above embodiments are aimed at creating a 1Tr/cell RAN. However, in all of the processes of the present invention, μ-channel MIS.FETs such as amplifiers and inverters can be formed on other parts of the same substrate without adding any photomasks. This made it extremely convenient for creating memory systems or logic systems.

Also, the lower electrode, upper electrode and first electrode of the capacitor
All of the regions may be formed as a silicon family made of the same main component as the substrate to improve reliability. Further, in the fourth embodiment, a multilayer lead made of Al or the like may be formed on the upper side with an interlayer insulator interposed therebetween.

In the present invention, a floating gate type nonvolatile memory may be constructed by electrically floating the gate electrode.

In the above four embodiments, the material constituting the first region or the material constituting the vertical approximately triangular layer 6 has the same main component as the substrate doped with impurities having conductivity type of P ⁺ or N ⁺ type. Materials such as silicon are mainly described.

However, they may be mixtures or compounds of silicon with Mo and W (Mo ₂ Si, W ₂ Si), and may also be made of multilayer structures of intrinsic, P ⁺ type or N ⁺ semiconductors, as well as materials such as silicon. It goes without saying that it may have a multilayer structure of a semiconductor and Mo, W, platinum, or a compound thereof.

In the present invention, the semiconductor substrate is mainly described as a single crystal. However, it goes without saying that it may be a compound semiconductor such as GaAs or InP, or a polycrystalline, amorphous, or semi-amorphous semiconductor.

As is clear from the above embodiments, the present invention does not have a conventional structure in which a pair of sources and drains are separated from each other by a gate electrode, but rather the side portion thereof is closer to the first region that can constitute the source or drain. In this way, the gate electrode was mechanically reinforced, and its source or drain was provided on the surface of the semiconductor substrate. In addition, the other source and drain have a structure provided on the upper part of the semiconductor approximately in line with one end of the gate, and their structural features include a frequency response speed of 0.1 to 1μ and a frequency response speed of 1 to 10G.
Ultra short channel (μ channel) MIS with Hz.
A major feature is that the FET can be implemented without using techniques such as electron beam exposure as an absolute requirement.

[Brief explanation of drawings]

FIG. 1 shows a longitudinal cross-sectional view of a conventionally known MIS.FET. FIGS. 2 and 3 are longitudinal sectional views showing the manufacturing process and structure of an embodiment of the present invention. FIGS. 4A and 4B are longitudinal sectional views of another embodiment of the present invention in which a pair of memories of 1 Tr/cell are provided.

Claims (1)

[Claims] 1. A step of forming a convex first region selectively comprising a conductor or a semiconductor in part or in whole on one surface of a semiconductor substrate or an insulating film on the surface; forming an insulating film on a side surface and a top surface; selectively removing the insulating film to expose the first region; and covering the first region and the insulating film with a film made of a conductor or semiconductor. By selectively removing the film by anisotropic etching, a vertically shaped approximately forming a triangular gate electrode and simultaneously forming an electrode lead in contact with the conductor or semiconductor in the first region; 1. A method for manufacturing a semiconductor device, comprising the step of forming a region.