JPH0237107B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention proposes a semiconductor device, particularly a MIS type (insulated gate type) field effect semiconductor device (hereinafter referred to as μ channel MIS.FET) having a micro channel type.

The present invention selectively provides a first region made of a semiconductor or conductor of the same or different conductivity on the surface of a semiconductor substrate of one conductivity type, and utilizes a step at a corner of a convex portion of the first region. and its height as the first
It has a gate length (width of the triangle) of 1μ or less with a vertical, almost triangular cross section whose width roughly matches the thickness of the coating to be formed at the corner, and whose width is approximately equal to the thickness of the coating formed at the corner. Another object of the present invention is to provide an insulated gate field effect semiconductor device having a gate electrode with a larger height (thickness).

In the present invention, this first region or an impurity region provided in the same shape on the upper part of the substrate in contact with the first region is used as a region constituting a source or drain, and a vertical approximately triangular layer is used as a gate electrode. A MIS.FET is constructed by providing a second region of the same conductivity type as the first region as a drain or source at the lower end of the layer.

Conventionally, the structure of a MIS.FET and a capacitor connected in series thereto is as shown in FIG.
and a drain or source 14 that is effectively a drain or source opposite to the source or drain 13 and constitutes the lower electrode of the capacitor.
In addition, the lead 9, capacitor insulator 15, and counter electrode 7 were provided.

Conventionally, MIS.FETs have always had a pair of source and drain regions 13 and 14 formed on the same plane on a semiconductor substrate under both ends of a gate insulator. Furthermore, this gate electrode 6 was provided not only on the gate insulator 11 but also over the upper surface of the counter electrode 7 of the capacitor. This is one end of the gate electrode.
Self-alignment is provided with one end of the source or drain 13 below 6 and one end 18 of the drain or source 14 on the other end of the apparent gate electrode, and the other end 17 of the gate electrode is made larger than 18 to improve mask alignment accuracy. Poly (process using polycrystalline silicon coatings 7 and 6) to compensate for variations in
It is. However, even in such a case, it is impossible to reduce the channel length to 1μ or less due to the photoetching process, and in particular, due to the unevenness at the step part 18, it is impossible to shorten the channel length because pattern breakage may occur. It was possible. The present invention actively utilizes this level difference to create a MIS.FET.
A gate electrode is provided, and this electrode is formed without extending over the opposing electrode of the capacitor.

In the present invention, the width corresponding to the channel length of the layer functioning as a gate electrode can be extremely small, 0.1 to 1μ, and the thickness is 0.5 to 1μ, which is thick and has a vertical, almost triangular shape. It has a longitudinally longer cross-sectional structure than the electrode.

In addition, since it is long in the vertical direction, its strength is not sufficient as it is. To compensate for this intensity, a first region is therefore provided along this layer. In addition, this first region is configured as part or all of the source or drain of the MIS.FET, and is characterized in that it is provided as the source or drain.

Therefore, the purpose of the semiconductor device of the present invention is to achieve high density for configuring its elements by proactively providing the elements in the height direction, rather than reducing the area in the lateral direction by scaling as in the past.

Examples of the present invention will be described below with reference to the drawings.

Example 1 The manufacturing process of this example is shown in Fig. 2.
N-channel MIS.FET that uses multiple carriers
This is an example of forming a capacitor.

Semiconductor substrate, for example silicon single crystal semiconductor 10
0, P type 10 to 500Ωcm was selected. Silicon nitride with a thickness of 50 to 300 Å was formed on the substrate by a plasma nitriding method in which a reactive gas made by activating ammonia by induction energy was reacted at 800 to 1200°C. The coating having a masking effect on the oxidizable substrate may be a multilayer film of silicon oxide, polycrystalline silicon, and silicon nitride.
Thereafter, as shown in FIG. 2A, the silicon nitride was removed using a first photomask to use a selective oxidation method, and after that area was made P, a field insulator 2 was buried to a thickness of 0.5 to 2μ. Formed.

Furthermore, under this silicon nitride film 4, there is a thickness of 50 to 5000 Å.
The layer 20 was formed by doping As to a depth of 1000 Å or less by ion implantation and converting the vicinity of the interface to N.

This ion implantation damages not only the substrate but also silicon nitride, and since silicon nitride cannot be removed like silicon oxide by mere thermal annealing, induction energy is applied to forcibly remove the damage from silicon nitride. Alternatively, hydrogenation and nitridation of nitrogen dangling bonds were performed for 10 to 30 minutes. As a result, we were able to obtain an interface level of 10 ¹⁰ cm ^-2 , the same as before ion implantation.

This silicon nitride film or this film was removed and another insulating film such as silicon nitride or tantalum oxide was formed to a thickness of 100 to 500 Å to form the gate insulating film 11 and the dielectric 15 of the capacitor. Next, after thoroughly cleaning the surface of the insulating film, a low pressure vapor phase method (LPCVD) is applied onto the substrate.
A silicon semiconductor doped with an impurity of one conductivity type, for example, an N-type impurity, was formed to a thickness of 0.5 to 2.5 .mu.m by a method (method).

Furthermore, by using known photolithography, the edges around that side were selectively removed (anisotropic etching was performed) while being careful not to side-etch and to expose the vertical edge side surface, leaving the first region 3. . For example, fluorine-based gas (e.g. NF ₃ or CF ₄ ) excited by 2.45 GHz microwave.
was applied perpendicularly to the substrate from above at a pressure of 0.001 to 0.01 torr for etching. As a result, I was able to cleanly cut the periphery of the board at an angle of 85 to 90 degrees perpendicular to the substrate surface. In this embodiment, the width of this first region is 3 to 200 microns. A part of the capacitor 15 is formed over the field insulator 2 to increase the capacitance of the capacitor 15 and reduce the parasitic capacitance between the region 14 and the substrate 1 as in this embodiment. After this, a silicon oxide film 19 is applied to the top and side surfaces of this first region to
It was formed to a thickness of 5000 Å. This silicon oxide film was formed by a high-pressure oxidation method in which wet oxygen is oxidized at 900-1100° C. and pressurized to 5-10 atm, or by reducing the pressure to 0.001-1 torr and generating plasma using high-frequency induction energy.

This coating 4 may be made of other insulating film such as alumina which is a metal oxide, and this first region is also not made of silicon doped with impurities, but is a multilayer of intrinsic or intrinsic and P ⁺ or N ⁺ type semiconductors. The membrane may also be a metal or a metal compound, in particular Mo, W or a silicide thereof (Mo ₂ Si, W ₂ Si).

Next, openings 41 and 42 were formed using a photomask by a known plasma etching method using CF ₄ gas. Next, a conductor or semiconductor film 5 was formed on the upper surface by, for example, a low pressure CVD method to a thickness of 0.1 to 1 μm. In this coating 5, it is extremely important that the upper and side surfaces of the first region 3 constituting the convex portion are formed to have a uniform thickness and a predetermined thickness. In this way, the thickness direction of the side periphery of the first region 3 is the same as the thickness of the coating 5, so the apparent thickness of that region from above the substrate is 2 to 5 times the thickness. It became possible to make the

For example, N ⁺ type silicon is 0.10~1.5μ, especially 0.3~0.7μ.
It was formed to a thickness of . The concentration and conductivity type of impurities added to this film generally depend on the degree of conductivity of this electrode 6 and the opening 4 between the film and the semiconductor substrate 1.
It is determined by the selection of ohmic contact type or PN junction type in 1 and the selection of whether the semiconductor substrate under the gate insulator 11 under this film is of depletion type or enhancement type.

In the case of N-channel MIS.FET, for example, substrate 1
is P ^- type and the N-type layer 20 at the interface is made P to make it an enhancement type, then the coating 5 has B of 10 ¹⁸
P ⁺ type silicon may be used by adding it to a concentration of ~10 ²¹ cm ^-3 . In addition, in order to make ohmic contact between this film and the N-type first region 3 provided on the semiconductor substrate, in this embodiment, a region which is later formed by ion implantation and serves as a source or drain is used. First, the second region 13 whose end is roughly aligned with the end of the gate electrode and its lead 9 are made N ⁺ , and finally, the impurity necessary to make only the gate electrode part P ⁺ is added to 5. It was formed by adding impurities at ~50 times the concentration to compensate.

Conversely, an impurity may be added to this film 5 to make it P ⁺ type, and the region that will become the lead 9 may be formed with N ⁺ at a concentration 5 to 100 times higher in a subsequent step.
Further, if the second region 13 and the gate electrode 6 are of the same conductivity type and are of a depletion type, the coating 5 may be of N ⁺ type and the openings 41 and 42 may be in ohmic contact.

In addition, when this coating 5 is made of a compound or mixture of silicon such as W ₂ Si, Mo ₂ Si, tungsten, molybdenum, etc., the coating is formed by LPCVD, electron beam evaporation, or reactive sputtering method to a thickness of 0.3 to 1.5μ, especially It is sufficient to form a layer with a thickness of 0.5 to 0.7μ.

Thus, Figure 2B was obtained.

Next, as shown in FIG. 2C, a photoresist (for example, OMR-83 manufactured by Tokyo Ohka) was coated on the upper surface of the area to be left as part of the film, and after exposure, photoetching was performed. For this etching, it is important to use an etching method with very little side etching and taper etching or which is not clean, rather than the conventional anisotropic etching method using a solution.
Specifically, reactive gases for etching, such as nitrogen fluoride ( _NF3 ) and _CF4 , are chemically activated using microwaves using 2.45GHz, and the degree of vacuum is further reduced to 0.1 to 0.001 torr, especially 0.005 to 0.01. In an effort to completely eliminate side etching, a fluorine shower produced as plasma in a vacuum atmosphere of torr was flowed vertically from the top surface of the substrate.

As a result, when the planar portion of the coating 5 on which no photoresist is formed is completely removed, the coating 8 around the side, which is the corner portion of the first region 3, remains in a vertical, almost triangular shape around the side. could be left as layer 6. In addition, it was possible to configure and provide the counter electrode 3 of the capacitor on the insulating film 4. Further, in this embodiment, the contact 41 and its lead 9 in the second region are
It was possible to leave it as an electrode lead 9 in N ⁺ type. Further, the gate electrode 6 is located in the convex first region 3.
It is characterized in that it does not exist over the upper surface, and its width can be determined not by the width determined by photolithography but by the thickness of the side surface of the coating 5 and the degree of anisotropic etching. . This vertical, almost triangular layer 6 has a width of 0.05 to 1.0μ, typically 0.1 to 0.5μ, and a height of 0.3 to 2.5μ, typically 0.4 to 0.8μ. . In particular, this width is a function of the thickness of the coating 5 and the etching time and intensity when side etching is performed by plasma etching, but it can be made from 0.05 to 0.05 without using advanced techniques such as electron beam exposure.
It was possible to provide a very short channel of 1.0μ (hereinafter referred to as a microchannel).

In FIG. 2C, the vertical approximately triangular layer 6 has a width of 0.1 to 1 μm, but the layer can be extended over the field insulator according to design needs, and its lead width It goes without saying that it may be provided with a width of 1 to 10μ and connected to the electrode leads of other MIS.FETs provided on the same board, or electrically connected to other electrode leads 9. . Furthermore, a metal having a masking effect may be formed on the upper surfaces of the electrodes 7 and leads 9, and the semiconductor underneath may be of N ⁺ type, and P ⁺ type impurities may be diffused into the gate electrode 6 portion. However, in this case, in order to make the PN junction formed in the semiconductor layer essentially an ohmic contact, lateral diffusion is performed to the bottom of the lead extending from this electrode, and the PN junction is formed under the metal film above it. The PN bond was virtually eliminated.

Next, as shown in FIG. 2D, arsenic, which is an N-type impurity, is implanted using an ion implantation method at an acceleration voltage of 30 KeV to form a second region 13 serving as a source or drain with an impurity concentration of about 10 ^{to 20} . The end portion was formed on the upper part of the substrate so that the end portion approximately coincided with the position of the bottom end portion of the vertical, substantially triangular layer 6. In addition, this region and the lead 9 were brought into ohmic contact.

Then, the first and second regions 14 and 13 could be formed into a μMIS.FET whose both ends substantially coincided with each other under both ends of the vertical, substantially triangular layer 6.

In addition, in order to bring the electrode or lead 9 into ohmic contact with the second region 13 acting as a source or drain, a further impurity diffusion layer is formed under the electrode to a depth of 50 to 2000 Å, and furthermore, the capacitor is Dielectric film 1 under the first region 3 which is the counter electrode
A depletion layer determined by the charge of the capacitor is provided below the depletion layer 5, and an impurity layer 14 that forms the drain or source 14 and becomes the electrode of the capacitor can be formed below these layers.

As is clear from the above embodiments, the present invention provides a vertical, approximately triangular layer 6 with a height (thickness) larger than the width.
is substantially larger, and its width is 0.1 to 1μ
By connecting capacitors in series, we were able to obtain a 1Tr/cell dynamic RAM memory cell.

Furthermore, since the layer 6 that becomes the gate electrode is thick, it becomes geometrically weak.
In addition, since unevenness tends to become severe, it was possible to electrically isolate it with the insulating film 4 and mechanically reinforce it by placing it on the convex first region. It is a feature.

As is clear in Figure 2D,
14 and second region 13 are separated from each other by a vertical approximately triangular layer 6, one of which is used as a source, the other as a drain, and the layer 6 is used as a gate electrode, an extremely short channel (μ channel) type MIS. FET can be made. In addition, the first region 3 constituting the source or drain is used as one counter electrode, and the insulating film 1
By further providing an electrode 14 below 5, a capacitor 15 is connected in series to this MIS.FET.
A feature of the present invention is that 1Tr/cell memory cells are provided.

Furthermore, lead 1 in the direction perpendicular to these leads 9 and 5
When the interlayer insulator 25 was formed from a polyimide-based insulator such as PIQ, the metal on the upper surface of the interlayer insulator 25 could be selectively oxidized using photolithography.

In the present invention, one source or drain 14 of the μ-channel MIS.FET 6 having a frequency response speed of 1 to 10 GHz is connected to the lower electrode 14 of the capacitor.
Another feature is that it can be used for both purposes.

Figure 2 E is a vertical cross-sectional view of MIS.FET6 in Figure 2 D.
and capacitor 15, and the memory cells are symbolized by corresponding numbers.

In the embodiment of the present invention, the conductivity type is that the substrate is P ^- type, the channel region 12 is N type, the first and second regions 13,
This is a μMIS.FET using so-called multiple carriers in which the gate electrode 14 is of N ⁺ type and the gate electrode 16 is of P ⁺ type.

However, the gate electrode is the same as the source and drain.
It may also be an N ⁺ type MIS.FET.

It can also be used as an enhancement type or depletion type MIS.FET using bulk minority carriers with P type in the channel region, N ⁺ type in the first and second regions, and P ⁺ or N ⁺ gate electrode. good.

Figure 1 shows a 1Tr/cell dynamic RAM memory formed on a substrate using one MIS.FET and one capacitor, but other MIS.FETs are placed on the same substrate in other parts separated by field insulators. The so-called
The present invention can be further promoted by using LSI or VLSI.

Example 2 FIG. 3 shows another embodiment of the invention.

That is, a semiconductor substrate 1 having a conductivity type of P ^- type was subjected to plasma nitridation at 800 to 1200° C. to form a silicon nitride film with a thickness of 50 to 250 Å on the surface. Further, the nitride film was selectively removed with a buffer etchant by photolithography using a first photomask. Further, only the removed area was heated and oxidized at 600 to 1100°C in water vapor pressurized to 5 to 15 atmospheres, and the field insulator 2 was buried to a thickness of 0.3 to 2 μm to form. . Further, the upper part of the field insulator may be removed at the same time as the nitride serving as a mask using a 30 to 50% buffered etchant to make the upper surface flat.

After this, in FIG. 3A, a first layer is placed on the semiconductor substrate 1 over the field insulator 2 on the right side.
Region 3 was formed.

This first region is made of tantalum oxide, silicon nitride, or titanium oxide, which is further laminated on the upper surface of the semiconductor layer 30 doped with a highly concentrated impurity of N ⁺ type conductivity to a thickness of 0.05 to 0.2μ. Alternatively, a ferroelectric film 31 is formed, and a counter electrode 32 made of a conductor or semiconductor is formed on the upper surface thereof.

The height of this first region 3 is the same as in Example 1.
The size was 0.5 to 2.5μ, and the total area was determined based on the capacity required in the design. The present invention is characterized in that the area of contact with the semiconductor substrate 1 is small in order to eliminate parasitic capacitance with the substrate, and a capacitor is provided across the field insulator. In addition, this embodiment differs from the first embodiment in that the dielectric 31, electrode 30, and counter electrode 32 of the capacitor all constitute the first region.

In order to provide a capacitor, the first region may be a semiconductor layer, and a silicon oxide or silicon nitride insulating film may be formed by adding oxygen or nitrogen at a high concentration to a predetermined portion from the upper surface of the semiconductor layer.

In FIG. 3B, the upper surfaces of semiconductor substrate 1 and first region 3 were further oxidized or nitrided in the same manner as in Example 1 to form insulating film 4. Of course, this insulating film 4 may be formed by a vapor phase method or a vacuum evaporation method. Furthermore, if the first region 3 is a semiconductor or conductor of a different type from the substrate, it will be an oxide or nitride of the semiconductor or conductor, and it goes without saying that the first region 3 will be an insulating film of a different type from the insulating film on the surface of the substrate.

Furthermore, in FIG. 3B, openings 41 and 42 were formed using a third photomask in the same manner as in Example 1, and a coating 5 for forming a vertical, approximately triangular layer 6 was formed thereon. . Thereafter, as shown in FIG. 3C, a second region 13 serving as a source or a drain is inserted into the upper part of the lower substrate by penetrating this film 5 by ion implantation using the side peripheral part 8 of this film 5. Formed by injection. This area is layer 30
It has the same conductivity type as .

Next, using anodic oxidation or a selective oxidation method, the other parts except for the electrodes/leads 9 and 45 were selectively oxidized using a fourth photomask and a photoresist to form an insulator 44 such as silicon oxide. At this time, around the side of the first region 3, a vertical approximately triangular layer 6,
8' is formed. This layer 6 functions as a gate electrode, and when an oxide insulator of the material constituting this gate electrode is provided surrounding the outer periphery, another layer 8' is formed using a fifth photolithography technique. It was oxidized again and disappeared. In the mask process, the leads 9 and contacts 45 are formed at the same time as the gate electrode 6, so that they can be connected to the gates, sources, and drains of other MIS.FETs on the same substrate.

As shown in FIG. 3C, in order to more precisely match the lower ends of the field insulator 2 and the vertical approximately triangular layer 6, a diffusion layer is formed under the second region 13 and the first region 3. 14 may be formed by heat treatment. and respective areas 13 and 1
4 or 3 as a source and a drain or a drain or source, and a vertical approximately triangular layer 6
I was able to create a μ-channel MIS.FET with .

In FIG. 3D, the third lead 1 is removed using a photomask using the interlayer insulator 36.
0 is set.

This MIS.FET had a structure of N ⁺ 13-P (channel forming region under the gate electrode)-N ⁺ 14 or 30) using minority carriers in the substrate. However, it may also be N ⁺ 13-N (channel forming region under the gate electrode 6) -N ⁺ (14 or 30) using a plurality of carriers on the substrate as in the first embodiment.

Alternatively, a C/MIS.FET structure may be used in which a plurality of C/MIS.FETs are provided relative to each other.

Furthermore, since the leads 5 and 9 were provided on the field insulator 2, it was extremely easy to integrate a plurality of MIS.FETs.

Assuming that FIG. 3E is an electrical equivalent circuit of FIG. 3D, the electrode 6 is of N ⁺ type, and the capacitor 31 is partially formed inside the first region, and is connected to the lower electrode. 30 upper counter electrode 32 dielectric 31, furthermore, this lower electrode is μ channel MIS.FET.
By using both sources and drains, it was possible to create high-density memory cells (1Tr/cell).

Further, when mask aligning the first region using a photomask, most of the first region can be provided over the upper surface of the field insulator 2. Therefore, the width of the region where the diffusion layer 14 exists, which can be substantially formed under the first region 3, can be made extremely narrow to 0.3 to 3 μm. Therefore, the parasitic capacitance between the layer 14 and the substrate could be extremely reduced. Furthermore, the gate electrode 6 and the source or drain can be fabricated using the electrodes and leads 5 and 9 without requiring any special process. Ability to perform photo etching, 2
It is characterized in that layer wiring can be performed in the X and Y directions, and only seven types of masks are required.

Example 3 FIG. 4A shows another embodiment of the invention.

FIG. 4A shows Embodiment 2 with even more layers. That is, a second region 13 and a pair of first regions 3, 3' are provided symmetrically thereto. The first region is provided partially over the field insulator 2, and the μ-channel MIS.FET is configured as a source or drain 13, gates 6, 6', drains or sources 14, 14, ′
A lower electrode 30, 30' of the capacitor, a dielectric 31, 31', and an upper counter electrode 32, 32' of the capacitor are provided through the capacitor. In the drawing, reference numerals 13 and 9 are bit lines, which are part of a memory system having a structure in which two 1Tr/cells are paired with lead lines 6 and 6'.
With such a structure, the second region can be shared, and a material with a high dielectric constant different from the dielectric material 31, 31' gate insulating film can be used, such as tantalum oxide, barium titanate, etc. . In this embodiment, the gate electrode 6,
The outer periphery of 6' is insulated by the oxide insulator 24, which has a thickness of 0.01 to 0.3μ, and an interlayer insulator 36 such as polyimide is formed on the outside, and a third layer is formed on the top surface of the interlayer insulator 36. A conductive layer 9 was formed. This insulator 24 prevented ions such as chlorine remaining in the polyimide from coming into direct contact with the gate electrode and causing a corrosion reaction, which was effective in improving reliability.

Example 4 This example is shown in longitudinal section in FIG. 4B.

As is clear from the drawing, a first region 3 is provided in a convex manner on the surface of the semiconductor substrate in close contact with the semiconductor substrate, an insulating film is provided around that side and at the corner of the substrate, and a gate electrode 6, 6' are formed as a pair. A portion of this gate electrode made of silicon was oxidized to provide silicon oxide 24, and second regions 13 and 13' having the same conductivity type as the first region 3 were symmetrically provided by ion implantation.
In this way, the μ-channel MIS.FETs were arranged in two pairs.

Here, the first regions 3, 3' are μ channel MIS.
It functions as the source or drain region of the FET or its electrode, and the gate electrodes 6, 6'
It has the function of supplementing the physical strength of

Next, since the contact openings 41 and 41' provided in a part of this first region are provided in the same manner as in the first embodiment, the dielectric lower electrode 30 is It was formed to have a thickness of 1μ. Furthermore, the surface of this tantalum is oxidized by a precise anodization method to form a dielectric film 31.
It was formed to a thickness of 100 to 500 Å. Thereafter, a counter electrode 32 made of metal or semiconductor is provided on this surface, and after photo-etching, this electrode 32 is etched and the lower electrode is again formed of porous tantalum oxide by anodization to insulate it. The film was designated as 39. Thus the upper electrode 32 of the capacitor,
32', dielectrics 31, 31' and lower electrode 3
0.30' could be made to have approximately the same shape. In addition, this capacitor can be provided over the field insulating film or the insulating film 24 on the gate electrode, and if necessary, the capacitor can be provided over the first region 3.
It was installed above the At this time, the gate electrode had a convex shape in this region, making it difficult to apply the photoetching technique, but in the embodiment of the present invention, the upper electrode 32 was formed with rough photoetching accuracy.
Using the electrode 32 as a mask, the dielectric material and the lower electrode in the area not covered by the electrode 32 are insulated by anodization, and the insulators 34, 39 are insulated.
Making the same shape in a self-aligned manner was extremely effective in reducing size, increasing density, and improving reliability.

In this embodiment as well, similar to Embodiment 3, a high dielectric constant material such as tantalum oxide can be used as the dielectric material, and the bit line is the region 3 and the word line is the 1Tr which forms a pair with the gate electrodes 6 and 6'. /cell could be configured as part of the memory system.

All of the above embodiments are aimed at producing a 1Tr/cell RAM. However, in all of the processes of the present invention, μ-channel MIS.FETs such as amplifiers and inverters can be formed on other parts of the same substrate without adding any photomasks. This made it extremely convenient for creating memory systems or logic systems.

Also, the lower electrode, upper electrode and first electrode of the capacitor
All of the regions may be formed as a silicon family made of the same main component as the substrate to improve reliability. Further, in the fourth embodiment, a multilayer lead made of Al or the like may be formed on the upper side with an interlayer insulator interposed therebetween.

In the present invention, a vertical, substantially triangular gate electrode may be surrounded by an oxide insulator of the material constituting this electrode, and a floating gate nonvolatile memory may be configured as an electrically floating structure.

In the above four embodiments, the material constituting the first region and the material constituting the vertical approximately triangular layer 6 are the same as the substrate doped with impurities having conductivity type of P ⁺ or N ⁺ type. Component materials such as silicon are mainly described.

However, they may also be mixtures or compounds of silicon and Mo, W (Mo ₂ Si, W ₂ Si),
It goes without saying that it may also have a multilayer structure of an intrinsic, P ⁺ type or N ⁺ type semiconductor, or a multilayer structure of a semiconductor such as silicon and Mo, W, platinum or a compound thereof.

Further, in the present invention, the semiconductor substrate is mainly described as a single crystal. However, it goes without saying that it may be a compound semiconductor such as GaAs or InP, or a polycrystalline, amorphous, or semi-amorphous semiconductor.

As is clear from the above embodiments, the present invention does not have a conventional structure in which a pair of sources and drains are separated from each other by a gate electrode, but rather the side portion thereof is closer to the first region that can constitute the source or drain. In this way, the gate electrode was mechanically reinforced, and its source or drain was provided on the surface of the semiconductor substrate. In addition, the other drain and source have a structure in which they are provided as a convex first region on the upper part of the semiconductor, roughly coinciding with one end of the gate, and further have an ultra-short channel (μ A major feature is that MIS.FET can be implemented without using techniques such as electron beam exposure as an absolute requirement.

[Brief explanation of drawings]

FIG. 1 shows a longitudinal cross-sectional view of a conventionally known MIS.FET. FIGS. 2 and 3 are longitudinal sectional views showing the manufacturing process and structure of an embodiment of the present invention. FIGS. 4A and 4B are longitudinal sectional views of another embodiment of the present invention in which a pair of memories of 1 Tr/cell are provided.

Claims (1)

[Claims] 1. A convex first region made of a conductor or semiconductor provided on a semiconductor substrate, and does not extend above the substrate surface and the first region, and is composed of the first region and the substrate surface. a vertical, approximately triangular gate electrode formed on an insulating film at a corner of the gate electrode, and a second gate electrode, which serves as a source or drain, provided in the substrate, approximately coinciding with an end of the gate electrode; 1. A semiconductor device comprising: a first region, wherein the first region is a bit line.