JPH0239115B2 - TASOHAISENBANNOSEIZOHOHO - Google Patents
TASOHAISENBANNOSEIZOHOHOInfo
- Publication number
- JPH0239115B2 JPH0239115B2 JP4934086A JP4934086A JPH0239115B2 JP H0239115 B2 JPH0239115 B2 JP H0239115B2 JP 4934086 A JP4934086 A JP 4934086A JP 4934086 A JP4934086 A JP 4934086A JP H0239115 B2 JPH0239115 B2 JP H0239115B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- plating
- wiring board
- inner layer
- multilayer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010410 layer Substances 0.000 claims description 44
- 238000007747 plating Methods 0.000 claims description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 13
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 239000010949 copper Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 11
- 229920005989 resin Polymers 0.000 claims description 8
- 239000011347 resin Substances 0.000 claims description 8
- 239000003054 catalyst Substances 0.000 claims description 7
- 239000007788 liquid Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000012790 adhesive layer Substances 0.000 claims description 5
- 238000005553 drilling Methods 0.000 claims description 4
- 238000007772 electroless plating Methods 0.000 claims description 4
- 238000007788 roughening Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本発明は多層配線板の製造方法に関する。
従来の技術
従来の多層配線板は、両面に配線パターンを形
成した内層配線板と、銅張り積層板をプリプレグ
を介在して積層した後、孔明けを行い、全面に化
学めつき及び電気めつきを施した後、エツチング
処理して不用の銅箔を除去し外層回路を形成して
製造している。
また、アデイデイブ法による多層配線板は、め
つき触媒入り接着剤を表面に塗布した絶縁板を用
い、この絶縁板にめつきレジスト層を形成し、無
電解銅めつき液に浸漬して内層配線板を作り、こ
の内層回路の銅表面を粗面化処理し、さらに絶縁
層、接着剤層を順次形成した後、スルホール用の
孔明けを行い、外層のめつきレジスト層を形成
し、無電解銅めつきによる外層回路及びスルホー
ルを形成して多層配線板が製造されている。
発明が解決しようとする問題点
多層配線板を製造する工程において、内層回路
の銅表面と、この上に印刷法で厚付塗布する絶縁
樹脂層の層間密着性を向上させるために、銅表面
を化学薬品にて粗面化処理を行つている。この処
理を行つた後、銅表面に粘度が200〜500psの絶縁
樹脂を印刷塗布しているが、銅表面の凹凸部の全
てに絶縁樹脂が埋め込まれず、部分的にマイクロ
ボイドとなつた空洞が形成され、この空洞部が残
置されている箇所が、後工程の孔明けでスルホー
ルとなつた場合に、無電解めつき工程で、内層銅
の粗面化した面と絶縁樹脂との界面にめつき液が
浸透し、密着性を疎外し、製品の耐熱性が低下す
るという問題があつた。
問題点を解決するための手段
本発明は、内層回路板の内層銅を粗面化した
後、プライマー処理し、絶縁樹脂層、接着剤層を
順次形成し、孔明けを行い、めつきレジスト層を
形成し、無電解めつきで外層回路とスルホールを
形成する工程において、前記のプライマー及び絶
縁樹脂中にめつき触媒を添加してなる多層配線板
の製造方法である。
実施例
本発明の多層配線板の製造方法を図面に基づき
説明すると、ガラスエポキシ樹脂絶縁板1に触媒
入り接着剤2が塗布された基板の両面にめつきレ
ジスト層3を形成する。この後無電解めつきを行
い内層回路4を形成した内層配線板10を製造す
る。
この内層配線板10の内層回路4の表面を粗化
液で処理して凹凸部5を形成し、表1又は表2に
示す調合のプライマー処理液を用い、10cm/min
の速度で基板を浸漬する。浸漬後160℃30分間の
乾燥を行いプライマー層11を形成する。なお、
このプライマー処理液中にめつき触媒を添加す
る。
The present invention relates to a method for manufacturing a multilayer wiring board. Conventional technology A conventional multilayer wiring board is made by laminating an inner wiring board with wiring patterns on both sides and a copper-clad laminate with prepreg interposed therebetween, then drilling holes and chemically plating and electroplating the entire surface. After that, an etching process is performed to remove unnecessary copper foil and form an outer layer circuit. In addition, multilayer wiring boards produced using the Addi-Dave method use an insulating plate whose surface is coated with an adhesive containing a plating catalyst, a plating resist layer is formed on this insulating plate, and the inner layer wiring is immersed in an electroless copper plating solution. After making a board, roughening the copper surface of this inner layer circuit, and sequentially forming an insulating layer and an adhesive layer, holes are drilled for through holes, and a plating resist layer for the outer layer is formed. Multilayer wiring boards are manufactured by forming outer layer circuits and through holes by copper plating. Problems to be Solved by the Invention In the process of manufacturing multilayer wiring boards, the copper surface is The surface is roughened using chemicals. After this treatment, an insulating resin with a viscosity of 200 to 500 ps is printed and coated on the copper surface, but the insulating resin is not filled in all the uneven parts of the copper surface, and there are some cavities that become microvoids. If the holes formed and where these cavities remain become through-holes in the subsequent drilling process, the interface between the roughened surface of the inner layer copper and the insulating resin will be etched in the electroless plating process. There was a problem in that the coating liquid penetrated, impairing adhesion and reducing the heat resistance of the product. Means for Solving the Problems The present invention roughens the surface of the inner layer copper of the inner layer circuit board, then performs primer treatment, sequentially forms an insulating resin layer and an adhesive layer, makes holes, and then forms a plating resist layer. In this method, a plating catalyst is added to the primer and insulating resin in the step of forming an outer layer circuit and through-holes by electroless plating. EXAMPLE The method for manufacturing a multilayer wiring board according to the present invention will be described with reference to the drawings. A plating resist layer 3 is formed on both sides of a glass epoxy resin insulating board 1 coated with a catalyst-containing adhesive 2. Thereafter, electroless plating is performed to manufacture the inner layer wiring board 10 on which the inner layer circuit 4 is formed. The surface of the inner layer circuit 4 of this inner layer wiring board 10 is treated with a roughening liquid to form uneven portions 5, and then the surface of the inner layer circuit 4 of the inner layer wiring board 10 is treated with a roughening liquid at a rate of 10 cm/min using a primer treatment liquid having the composition shown in Table 1 or Table 2.
Immerse the substrate at a speed of After dipping, drying is performed at 160° C. for 30 minutes to form a primer layer 11. In addition,
A plating catalyst is added to this primer treatment solution.
【表】【table】
【表】【table】
【表】
この後、絶縁層用樹脂100部に痴しパラジウム
等のめつき触媒を3〜15部添加したものを印刷
し、絶縁層13を形成し、さらに接着剤層15を
形成し、無電解めつきを施して、外層回路20と
スルホール22を設けた多層配線板30を製造す
る。
この多層配線板30のスルホール22の断面を
電子顕微鏡で観察を行い、層間にめつき液の浸透
がないことを確認したところ表3のような評価結
果が得られた。[Table] After this, a mixture of 100 parts of the resin for the insulating layer and 3 to 15 parts of a plating catalyst such as diluted palladium is printed to form the insulating layer 13, and then an adhesive layer 15 is formed. A multilayer wiring board 30 provided with an outer layer circuit 20 and through holes 22 is manufactured by electrolytic plating. The cross section of the through hole 22 of this multilayer wiring board 30 was observed with an electron microscope to confirm that there was no penetration of the plating liquid between the layers, and the evaluation results shown in Table 3 were obtained.
【表】
なお、絶縁層13の厚みが薄いときには、スル
ホール内のめつき析出性が良好であるが、厚みが
厚くなるとめつきの形状が不揃いになるので、こ
のときには孔内にシーダー処理を行うことによつ
てスルーホール銅の表面が平滑になる。
発明の効果
本発明は内層回路の銅表面を粗面化した後、エ
ポキシ系絶縁層と親和性が優れたプライマー処理
を行い、特にはエポキシ系ノボラツク系のプライ
マー処理を行うことにより層間の密着性が向上
し、プライマー処理液及び絶縁層内にめつき触媒
を添加することによりスルホール内のめつきが均
一な厚上のめつき層をうることができるようにな
り、高品質の多層配線板がえられた。[Table] Note that when the thickness of the insulating layer 13 is thin, the plating precipitation inside the through hole is good, but when the thickness is thick, the shape of the plating becomes irregular, so in this case, seeder treatment should be performed inside the hole. This makes the surface of the through-hole copper smooth. Effects of the Invention The present invention roughens the copper surface of the inner layer circuit, and then performs a primer treatment that has excellent affinity with the epoxy insulating layer, and in particular, performs a primer treatment with an epoxy novolac type to improve the adhesion between the layers. By adding a plating catalyst to the primer treatment solution and the insulating layer, it is now possible to obtain a thick and uniform plating layer within the through-holes, resulting in high-quality multilayer wiring boards. I got it.
第1図は本発明の断面図、第2図は内層配線板
の断面図である。
図面において、4:内層銅箔、5:凹凸部、1
0:内層回路板、11:プライマー層、13:絶
縁層、15:接着剤層、18:めつきレジスト、
20:外層回路、22:スルホール、30:多層
配線板。
FIG. 1 is a sectional view of the present invention, and FIG. 2 is a sectional view of an inner layer wiring board. In the drawings, 4: inner layer copper foil, 5: uneven portion, 1
0: Inner layer circuit board, 11: Primer layer, 13: Insulating layer, 15: Adhesive layer, 18: Plating resist,
20: outer layer circuit, 22: through hole, 30: multilayer wiring board.
Claims (1)
の上にプライマー層を形成し、さらに絶縁樹脂
層、接着剤層を順次積層形成し、孔明け加工処理
を行い、外層のめつきレジスト層を形成した後、
スルホール及び外層回路を無電解めつきにより形
成する際、前記プライマ液と絶縁樹脂とにめつき
触媒を添加することを特徴とする多層配線板の製
造方法。 2 孔明け加工をした後、孔内にシーダー処理を
行う特許請求の範囲第1項記載の多層配線板の製
造方法。[Claims] 1. The inner layer copper surface of the inner layer circuit board is roughened, a primer layer is formed thereon, an insulating resin layer and an adhesive layer are sequentially laminated, and a hole drilling process is performed. , after forming the outer plating resist layer,
A method for manufacturing a multilayer wiring board, comprising adding a plating catalyst to the primer liquid and insulating resin when forming through holes and outer layer circuits by electroless plating. 2. The method of manufacturing a multilayer wiring board according to claim 1, wherein after the hole drilling process, a seeder treatment is performed in the hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4934086A JPH0239115B2 (en) | 1986-03-06 | 1986-03-06 | TASOHAISENBANNOSEIZOHOHO |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4934086A JPH0239115B2 (en) | 1986-03-06 | 1986-03-06 | TASOHAISENBANNOSEIZOHOHO |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62206898A JPS62206898A (en) | 1987-09-11 |
| JPH0239115B2 true JPH0239115B2 (en) | 1990-09-04 |
Family
ID=12828268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4934086A Expired - Lifetime JPH0239115B2 (en) | 1986-03-06 | 1986-03-06 | TASOHAISENBANNOSEIZOHOHO |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0239115B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2579960B2 (en) * | 1987-10-13 | 1997-02-12 | 日立化成工業株式会社 | Manufacturing method of multilayer printed wiring board |
-
1986
- 1986-03-06 JP JP4934086A patent/JPH0239115B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62206898A (en) | 1987-09-11 |
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