JPH0691187B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0691187B2 JPH0691187B2 JP62268481A JP26848187A JPH0691187B2 JP H0691187 B2 JPH0691187 B2 JP H0691187B2 JP 62268481 A JP62268481 A JP 62268481A JP 26848187 A JP26848187 A JP 26848187A JP H0691187 B2 JPH0691187 B2 JP H0691187B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate potential
- semiconductor device
- terminal
- channel mos
- mos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/211—Design considerations for internal polarisation
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特にダイナミックランダム
・アクセス・メモリに関する。The present invention relates to a semiconductor device, and more particularly to a dynamic random access memory.
従来、64kビット・ダイナミック・ランダム・アクセス
・メモリ（DRAM）以降、DRAMは１電源型となったため、
基板電位発生回路内蔵型となっていた。又、空ピンを直
接基板パッドに接続したものもあった。Conventionally, since the 64-kbit dynamic random access memory (DRAM) and later, the DRAM has become a single power supply type,
It had a built-in substrate potential generation circuit. Also, there are some in which empty pins are directly connected to the substrate pads.
第３図に従来の64kDRAMの平面模式図を示す。この従来
例では外部端子V3が空ピンとなっている。FIG. 3 shows a schematic plan view of a conventional 64kDRAM. In this conventional example, the external terminal V 3 is an empty pin.
上述した従来の半導体装置は基板電位発生回路内蔵型と
なっていて、基板電位（VBB）は電源電圧（VCC），サイ
クルタイム，各種ファンクションに依存して変化する
が、基板電位の状態を外部から観測する手段を備えてい
ないので、電源電圧や基板電位のマージンをパッケージ
に実装後にテストできないという欠点がある。The above-described conventional semiconductor device has a built-in substrate potential generation circuit, and the substrate potential (V BB ) changes depending on the power supply voltage (V CC ), the cycle time, and various functions. Since there is no means for observing from the outside, there is a drawback that the margins of the power supply voltage and the substrate potential cannot be tested after mounting on the package.
又、空ピンを直接・基板パッドに接続したものでは、メ
モリ・ボードの接続まちがいで、空ピンに接続した場
合、通常用いられる正電圧印加によってデバイスが破壊
されたり、誤動作するという欠点がある。Further, if the empty pin is directly connected to the substrate pad, the connection of the memory board is incorrect.
本発明の半導体装置は、外部端子と、ドレインを前記外
部端子に接続しゲートに基板電位が供給される第１のＮ
チャネルMOSトラジスタと、ゲートおよびソースを接地
端子に接続しドレインを前記第１のＮチャネルMOSトラ
ンジスタのソースに接続した第２のＮチャネルMOSトラ
ンジスタとからなる一方向性の基板電位検出端子を備え
ているというものである。A semiconductor device according to the present invention includes an external terminal, a first N-type drain connected to the external terminal, and a substrate potential supplied to the gate.
A unidirectional substrate potential detection terminal including a channel MOS transistor and a second N-channel MOS transistor having a gate and a source connected to the ground terminal and a drain connected to the source of the first N-channel MOS transistor. It is that there is.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の平面模式図、第２図はこの
実施例の基板電位検出端子の回路図である。FIG. 1 is a schematic plan view of an embodiment of the present invention, and FIG. 2 is a circuit diagram of a substrate potential detection terminal of this embodiment.
この実施例は、外部端子V3′と、ドレインを外部端子
V3′に接続しゲートに基板電位VBBが供給される第１の
ＮチャネルMOSトランジスタQ1と、ゲートおよびソース
を接地端子V2に接続しドレインを第１のＮチャネルMOS
トランジスタQ1のソースに接続した第２のＮチャネルMO
Sトランジスタとからなる一方向性の基板電位検出端子
を備えている。すなわち、ゲートに基板電位VBBを入力
し、ソースと接地電位の間にダイオード動作をするMOS
トランジスタ（第２のＮチャネルMOSトランジスタ）か
らなる電流制御手段１を挿入し、外部端子V3′をドレイ
ンに接続するトランジタQ1（第１のＮチャネルMOSトラ
ンジスタ）を導入する。このような回路がチップ上に形
成されているものとする。そこでV3′に正電位を印加す
ると、電流が流れず開放の状態を作り出せる。従って誤
ってV3′に正電位を加えることがあっても半導体装置が
破壊されることはない。又、V3′に（基板電位）−（Q1
のしきい電圧）を印加すると、電流が流れるので、電流
が流れはじめる時のV3′電圧と電流の値を知れば、基板
電位が定量的に把握できる。In this embodiment, the external terminal V 3 ′ and the drain are connected to the external terminal.
A first N-channel MOS transistor Q 1 which is connected to V 3 ′ and whose substrate potential V BB is supplied to the gate, and a first N-channel MOS transistor whose gate and source are connected to the ground terminal V 2 and whose drain is the first N-channel MOS transistor.
Second N-channel MO connected to the source of transistor Q 1
A unidirectional substrate potential detection terminal including an S transistor is provided. That is, a MOS that operates as a diode between the source and the ground potential by inputting the substrate potential V BB to the gate
The current control means 1 consisting of a transistor (second N-channel MOS transistor) is inserted, and a transistor Q 1 (first N-channel MOS transistor) connecting the external terminal V 3 ′ to the drain is introduced. It is assumed that such a circuit is formed on the chip. If a positive potential is applied to V 3 ′, no current will flow and an open state can be created. Therefore erroneous never semiconductor device is destroyed even if the addition of a positive potential to the V 3 'to. In addition, V 3 ′ is (substrate potential) − (Q 1
When a threshold voltage) is applied, a current flows. Therefore, the substrate potential can be quantitatively grasped by knowing the V 3 ′ voltage and the current value when the current starts flowing.
以上説明したように本発明の半導体装置は、一方向性の
基板電位検出端子を外部端子として有しているので、容
易に基板電位を外部から測定できて便利である。又、誤
って、この端子に正電圧を印加しても半導体装置が破壊
されることもない。As described above, since the semiconductor device of the present invention has the unidirectional substrate potential detection terminal as an external terminal, the substrate potential can be easily measured from the outside, which is convenient. Moreover, even if a positive voltage is applied to this terminal by mistake, the semiconductor device is not destroyed.
第１図は本発明の一実施例の平面模式図、第２図は基板
電位検出端子の回路図、第３図は従来例の平面模式図で
ある。 １……電流制御手段、V1……電源端子、V2……接地端
子、V3……空ピン、V3′……基板電位検出端子、Φ１〜
Φ14……信号端子。FIG. 1 is a schematic plan view of an embodiment of the present invention, FIG. 2 is a circuit diagram of a substrate potential detection terminal, and FIG. 3 is a schematic plan view of a conventional example. 1 ... current control means, V 1 ... power supply terminal, V 2 ... ground terminal, V 3 ... empty pin, V 3 '... substrate potential detection terminal, Φ 1 ~
Φ 14 …… Signal terminal.
Claims (1)
続しゲートに基板電位が供給される第１のＮチャネルMO
Sトランジスタと、ゲートおよびソースを接地端子に接
続しドレインを前記第１のＮチャネルMOSトランジスタ
のソースに接続した第２のＮチャネルMOSトランジスタ
とからなる一方向性の基板電位検出端子を備えているこ
とを特徴とする半導体装置。1. A first N-channel MO having an external terminal, a drain connected to the external terminal, and a substrate potential supplied to the gate.
A unidirectional substrate potential detection terminal including an S transistor and a second N-channel MOS transistor having a gate and a source connected to the ground terminal and a drain connected to the source of the first N-channel MOS transistor is provided. A semiconductor device characterized by the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62268481A JPH0691187B2 (en) | 1987-10-23 | 1987-10-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62268481A JPH0691187B2 (en) | 1987-10-23 | 1987-10-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01110757A JPH01110757A (en) | 1989-04-27 |
| JPH0691187B2 true JPH0691187B2 (en) | 1994-11-14 |
Family
ID=17459092
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62268481A Expired - Fee Related JPH0691187B2 (en) | 1987-10-23 | 1987-10-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0691187B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1218715A (en) * | 1982-08-19 | 1987-03-03 | Richard D. Buckley | Cellulose-free transformer coil structure and method |
-
1987
- 1987-10-23 JP JP62268481A patent/JPH0691187B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01110757A (en) | 1989-04-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |