JPH07101709B2 - Capacity control device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a capacitance control device for controlling capacitance by connecting capacitance to sources or drains of P and N channel transistors that form a switch circuit. .

[Conventional technology]

FIG. 6 is a plan view showing a mask pattern of a conventional capacitance control device, in which 1 is an inverter, 2 is a P-channel transistor, 3 is an N-channel transistor,
4 is capacity, 5 is negative voltage power supply line (aluminum (Al) wiring), 6 is positive voltage power supply line (Al) wiring, 7 is input / output line, 8
Indicates a gate control line (polysilicon) as a gate electrode, and the capacitor 4 constituted by the polysilicon 9 and the Al electrode 10 comes into contact with and separates from it.

11A and 11B are transistor electrode regions, 12 is an N region, and 13 is a P region.
The region is shown and is connected to the negative voltage power supply line 5 and the positive voltage power supply line 6.

Reference numeral 14 is a contact portion between the polysilicon 8 and the Al wiring (wiring shown by a solid line), polysilicon 9 and the Al wiring 5, 15 is a contact portion connecting the transistor electrode regions 11A and 11B and the Al wiring, 16, 17, 18 , 19 is the source of the transistor electrode region 11B,
The P and N electrodes corresponding to the drain are shown.

FIG. 7 is a sectional view showing a portion of the P and N channel transistors of the capacitance control device shown in FIG.

Next, the operation will be described.

The capacitance 4 connected to the switch circuit composed of the P-channel transistor 2 and the N-channel transistor 3 is brought into contact with or separated from the input / output line 7 by the signal of the gate control line 8. At this time, the capacitance change seen from the input / output line 7 is the parasitic capacitance of the P and N channel transistors 2 and 3 which the transistor electrode region 11B connected to the capacitance 4 has with respect to the N region 12 or P region 13, It becomes the value which added capacity 4 and.

Further, the resistance value of the switch circuit when conducting is inversely proportional to the gate widths of the P and N channel transistors 2 and 3.

The gate width is, for example, the length across the transistor electrode region 11B in the vertical direction in FIG.

As a similar invention, there is a variable capacity control device (Japanese Patent Application No. 61-168742) previously proposed by the present applicant.

[Problems to be solved by the invention]

Since the conventional capacitance control device is configured as described above, the parasitic capacitance of the switch circuit is large and it becomes impossible to set a minute capacitance.

In order to reduce the parasitic capacitance of the switch circuit, P, N
If you reduce the size of the channel transistors 2 and 3,
There has been a problem that the resistance value of the switch circuit when conducting is increased.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a capacitance control device capable of reducing the parasitic capacitance of a switch circuit and reducing the resistance value when the switch circuit is conducting. To do.

[Means for solving problems]

In the capacitance control device according to the present invention, the source and the drain are alternately arranged, and the P and N channel transistors are configured by a plurality of transistor portions in which the same gate electrode is branched between the source and the drain. .

[Action]

The capacitance control device according to the present invention connects and separates the minute capacitance by the switch circuit having a low resistance according to the signal of the gate electrode.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, the same parts as those in FIG. 6 are designated by the same reference numerals, and the P and N electrodes 16 and 18 connected to the gate control line 8 of the N region 12 and P region 13 are connected to the capacitor 4. The P and N electrodes 17 and 19 are arranged so as to sandwich them.

FIG. 2 is an equivalent circuit of FIG. 1, and 4A indicates a combined capacitance of the capacitance 4 and the parasitic capacitance.

Next, the operation will be described.

P and N channel transistors 2 and 3 that form a switch circuit
The P and N electrodes 17 and 19 are P and N electrodes 1 with the gate electrode sandwiched on both sides.
Since 6 and 18 are arranged, a transistor structure is formed in both directions. That is, the P and N electrodes 17 and 19 also serve as the sources or drains of the two transistor portions, and if the P and N electrodes 16 and 18 at both ends are connected, the drive capability of the P and N channel transistors 2 and 3 is doubled. To do.

In the capacitance control device of the present invention, when the conduction resistance is halved with respect to the conventional switch circuit, the width of the gate electrode may be the same as the conventional width, and the parasitic capacitances of the P, N electrodes 17, 19 are different. Absent. Further, when the switch circuits have the same conduction resistance, the width of the gate electrode may be halved, and the parasitic capacitance is halved.

Therefore, the conduction resistance and parasitic capacitance of the switch circuit can be reduced, and the setting of the minute capacitance controlled by the switch circuit becomes easy.

In the above embodiment, the P, N electrodes 17, which are connected to the capacitor 4,
Although 19 is shared by the two transistor portions, the P and N electrodes 17 and 19 may be connected to the gate control line 8 and shared as shown in FIG. In this case, the parasitic capacitance floating in the gate control line 8 can be reduced.

Further, as shown in FIG. 4 (an equivalent circuit is shown in FIG. 5), if the capacitor 4 is connected between the source and the drain, when the switch circuit is on, the source and drain have P and N regions. 1
The parasitic capacitance 20 included in the capacitors 2 and 13 is connected, and when the switch circuit is off, the capacitors 4 and 20 are connected in series, and an effect that a capacitance smaller than the parasitic capacitance 20 can be controlled is achieved.

Further, although the P and N channel transistors 2 and 3 are each composed of two transistor portions, the same effect can be obtained even if they are composed of three or more transistor portions.

〔The invention's effect〕

As described above, according to the present invention, since the parasitic capacitance P of the switch circuit on the side of the minute capacitance connection is surrounded by the N-channel transistor, the parasitic capacitance can be reduced, and
By connecting the capacitors in parallel to the switch circuit, it is possible to control a smaller capacity than the capacity on the minute capacity connection side.

[Brief description of drawings]

1 is a mask pattern diagram of a capacity control device according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of the capacity control device shown in FIG. 1, and FIGS. 3 and 4 are other embodiments of the present invention. FIG. 5 is a mask pattern diagram of a capacity control device showing an example, FIG. 5 is an equivalent circuit diagram of the capacity control device shown in FIG. 4, FIG. 6 is a mask pattern diagram of a conventional capacity control device, and FIG. 7 is FIG. FIG. 6 is a cross-sectional view showing a portion of P and N channel transistors of the capacitance control device shown. In the figure, 1 is an inverter, 2 is a P-channel transistor, 3 is an N-channel transistor, 4 is a capacitor, and 4A.
Is a composite capacity, 5 is a negative voltage power supply line, 6 is a positive voltage power supply line, 7
Is an input / output line, 8 is a gate control line, 9 is polysilicon, 10
Is an aluminum electrode, 11A and 11B are transistor electrode regions, 12 is an N region, 13 is a P region, 14 and 15 are contact portions, 1
Reference numerals 6, 17, 18, 19 indicate P and N electrodes, 20 indicates parasitic capacitance, and solid lines indicate aluminum lines. In the drawings, the same reference numerals indicate the same or corresponding parts.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 27/088

Claims (1)

[Claims] 1. A capacitance control device having a configuration in which the sources and drains of P-channel transistors and N-channel transistors that form a switch circuit are connected, and a capacitance including a parasitic capacitance of the switch circuit is connected to the source or the drain, The sources and the drains are alternately arranged, and the P and N channel transistors are formed by a plurality of transistor portions in which the same gate electrode is branched between the sources and the drains, and the capacitance is the source. And a capacitance control device connected between the drain and the drain.