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JPS5931226B2 - semiconductor equipment - Google Patents
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JPS5931226B2 - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS5931226B2
JPS5931226B2 JP49045228A JP4522874A JPS5931226B2 JP S5931226 B2 JPS5931226 B2 JP S5931226B2 JP 49045228 A JP49045228 A JP 49045228A JP 4522874 A JP4522874 A JP 4522874A JP S5931226 B2 JPS5931226 B2 JP S5931226B2
Authority
JP
Japan
Prior art keywords
silicon
silicon layer
sapphire substrate
semiconductor device
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP49045228A
Other languages
Japanese (ja)
Other versions
JPS50141283A (en
Inventor
邦幸 浜野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP49045228A priority Critical patent/JPS5931226B2/en
Publication of JPS50141283A publication Critical patent/JPS50141283A/ja
Publication of JPS5931226B2 publication Critical patent/JPS5931226B2/en
Expired legal-status Critical Current

Links

Description

【発明の詳細な説明】 本発明はサフアイヤ基板等の絶縁物基板上に単結晶シリ
コンを成長させてその単結晶シリコン中に素子を形成す
る所謂SOS(シリコンオン サファイア)型半導体装
置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a so-called SOS (silicon on sapphire) type semiconductor device in which single crystal silicon is grown on an insulating substrate such as a sapphire substrate and elements are formed in the single crystal silicon. .

従来、505基板を用いた半導体装置を作成する場合シ
リコンをサファイア基板上に成長せしめた後に、ドナー
、アクセプタなどの不純物をシリコン中に拡散するプロ
セスが何回か行われるが、その場合拡散時の高温のため
にサファイア基板中のアルミニウムも又シリコン中に拡
散してしまいシリコンの特性、特に電気伝導度及び伝導
型をも変えてしまうことが生じる事があつた。そのため
にシリコン中に拡散するドナー及びアクセプタの不純物
をシリコン表面からサファイアまで達せしめるための条
件が著るしく制限されたものになり素子製作上非常な困
難を供つていた。従つて本発明の目的は上記の欠点を除
去した505型半導体装置を提供することである。
Conventionally, when creating a semiconductor device using a 505 substrate, after silicon is grown on a sapphire substrate, a process of diffusing impurities such as donors and acceptors into the silicon is performed several times. Due to the high temperature, the aluminum in the sapphire substrate also diffuses into the silicon, which can change the properties of the silicon, especially its electrical conductivity and conductivity type. Therefore, the conditions for allowing the donor and acceptor impurities diffused into the silicon to reach the sapphire from the silicon surface are severely restricted, creating great difficulties in device fabrication. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a 505 type semiconductor device which eliminates the above-mentioned drawbacks.

この発明の半導体装置はサファイア基板等の絶縁物基板
とその絶縁物基板の上に成長されたシリコン等の半導体
層とこれら絶縁物基板と半導体層との間に形成されたイ
オン打込みによつて形成された例えば二酸化シリコン膜
等の酸化物層を有することを特徴とする。この発明の半
導体装置によればサファイア基板とシリコン層の間に存
在する二酸化シリコン膜が高温プロセス時にサファイア
基板からシリコン内に拡散して来るアルミニウムに対し
て障壁となりアルミニウムがシリコン中に拡散するのを
抑える。
The semiconductor device of the present invention is formed by implanting an insulating substrate such as a sapphire substrate, a semiconductor layer such as silicon grown on the insulating substrate, and a layer formed between the insulating substrate and the semiconductor layer. It is characterized by having an oxide layer such as a silicon dioxide film. According to the semiconductor device of the present invention, the silicon dioxide film existing between the sapphire substrate and the silicon layer acts as a barrier to aluminum diffusing into the silicon from the sapphire substrate during high-temperature processes, thereby preventing aluminum from diffusing into the silicon. suppress.

従つてシリコンの特性はアルミニウムによつて変化する
ことがなく、又その故にシリコン表面からドナーやアク
セプタ型の不純物を拡散させる時に温度は高温にでき、
時間もドナー及びアクセプタ不純物がサファイア基板に
到達するのに充分の時間をとる事が可能となる大きな利
点を有する。次にこの発明の上述の特徴をよりよく理解
するために図を用いて説明しよう。第1図を参照すれば
従来の505型半導体装置はMOS型素子を例にとると
a図に示すようにサファイア基板101の上にシリコン
層102を成長させ、それを選択的に残した後二酸化シ
リコン膜103をマスクとしてソース領域104とドレ
イン領域105に熱拡散に依り不純物を選択的に拡散せ
しめる工程を得てb図に示すようにサファイア基板10
1とシリコン層102そのシリコン層の中に作られたソ
ース領域104、ドレイン領域105、ゲート膜となる
二酸化シリコン膜106、シリコン層102の他の部分
を被う二酸化シリコン膜IOT、IOT’、及び金属配
線108、109、110から成る構造をとる。
Therefore, the properties of silicon are not changed by aluminum, and therefore the temperature can be increased to diffuse donor and acceptor type impurities from the silicon surface.
Time also has the great advantage of allowing sufficient time for the donor and acceptor impurities to reach the sapphire substrate. Next, in order to better understand the above-mentioned features of this invention, the following will explain them using figures. Referring to FIG. 1, a conventional 505 type semiconductor device, taking a MOS type element as an example, grows a silicon layer 102 on a sapphire substrate 101 as shown in FIG. A step of selectively diffusing impurities into the source region 104 and drain region 105 by thermal diffusion using the silicon film 103 as a mask is performed, and as shown in FIG.
1, a silicon layer 102, a source region 104, a drain region 105, a silicon dioxide film 106 that becomes a gate film, a silicon dioxide film IOT, IOT', and a silicon dioxide film covering other parts of the silicon layer 102. It has a structure consisting of metal wirings 108, 109, and 110.

この従来のSOS型半導体装置に於いてはa図に示すよ
うにソース領域104、及びドレイン領域105に不純
物を拡散する時にサフアイア基板101からもアルミが
シリコン層102内に拡散してくる。
In this conventional SOS type semiconductor device, when impurities are diffused into the source region 104 and drain region 105, aluminum also diffuses into the silicon layer 102 from the sapphire substrate 101, as shown in FIG.

このためにシリコン層102はサフアイア基板101に
近い部分から強いP型になる傾向が生じる。このために
SOS型半導体装置に組み込まれている素子がn−チヤ
ンネルMOSトランジスタである場合はこのシリコン層
102内に拡散したアルミのためにスレーシヨールド電
圧、ソース104とドレイン105間の耐圧等のトラン
ジスタの特性が大きく変動してしまい信頼性が著るしく
損われるという欠点が生じたり、又、MOSトランジス
タがP−チヤンネルの場合にはシリコン層102のサフ
アイア基板101に近い部分がP型に反転してしまうと
ソース104とドレイン105は常に電気的に導通の状
態となりトランジスタ作用を全く果さないという致命的
な欠陥を示すという大きな欠点があつた。第2図を参照
すれば本発明のSOS型半導体装置は、先づa図に示す
如くサフアイア基板201の上にシリコン層202を成
長させた後そのシリコン202内でサフアイア基板20
1に近い領域203に酸素イオンを打ち込む。
For this reason, the silicon layer 102 tends to become strongly P-type from the portion close to the sapphire substrate 101. For this reason, if the element incorporated in the SOS type semiconductor device is an n-channel MOS transistor, the threshold voltage, the withstand voltage between the source 104 and the drain 105, etc. There is a drawback that the characteristics vary greatly and the reliability is significantly impaired.Also, when the MOS transistor is a P-channel, the part of the silicon layer 102 near the sapphire substrate 101 is inverted to the P type. In the end, the source 104 and drain 105 were always electrically conductive, resulting in a fatal defect in that they did not function as a transistor at all. Referring to FIG. 2, the SOS type semiconductor device of the present invention first grows a silicon layer 202 on a sapphire substrate 201 as shown in FIG.
Oxygen ions are implanted into a region 203 close to 1.

この時の打ち込むエネルギーは成長されたシリコン層2
02の厚さに依つて異なるが、その厚さが1μ程度のも
のであれば150Kev位が適当である。次にb図に示
す如く酸素を打ち込まれたSOS基板を熱することによ
りサフアイア基板201とシリコン層202の間に、酸
化シリコン膜204を形成する。この時打ち込まれた酸
素は高いエネルギーのために一部酸化シリコンを形成し
ている上にシリコン層の203の領域に高濃度で分布さ
せられているために高温度の熱処理は必要とされずたか
だか900℃以下の温度で充分である。従つて酸化シリ
コン膜204が形成される時にはサフアイア基板201
からのアルミニウムのシリコン層202への拡散は無視
される。その後c図に示せ如くにシリコン層202を選
択的に残した後二酸化シリコン膜205をマスクにして
不純物をソース領域206及びドレイン領域207に拡
散する。この際シリコン層202とサフアイア基板20
1の間には酸化シリコン膜204が介在しているためサ
フアイア基板201からシリコン層202へのアルミニ
ウムの拡散が抑えられる。従つてd図に示される如きサ
フアイア基板201、シリコン層202、シリコン層2
02とサフアイア基板201の間に介在する酸化膜層2
04、ソース領域206、ドレイン領域207、ゲート
膜208、ゲート膜以外のシリコン層202表面を被う
二酸化シリコン膜209,209′及び金属配線210
,211,212からなる本発明の第1の実施例のSO
S型半導体装置をえる。この発明の第1の実施例のSO
S型半導体装置によればサフアイア基板201とシリコ
ン層202の間に酸化膜204が介在しサフアイア基板
201からのアルミニウムのシリコン層202への拡散
がないためにシリコン層202の電気的伝導度や不純物
濃度は変化せず従つてスレーシヨルド電圧、ソース20
6とドレイン207の間の耐圧等の諸諸の電気的特性を
安定に保つことが可能になるという大きな利点をもつよ
うになる。
The energy implanted at this time is the grown silicon layer 2.
Although it varies depending on the thickness of 02, if the thickness is about 1μ, about 150Kev is appropriate. Next, as shown in Figure b, by heating the SOS substrate into which oxygen has been implanted, a silicon oxide film 204 is formed between the sapphire substrate 201 and the silicon layer 202. The oxygen implanted at this time partially forms silicon oxide due to its high energy, and is distributed at a high concentration in the region 203 of the silicon layer, so high temperature heat treatment is not required at most. A temperature below 900°C is sufficient. Therefore, when the silicon oxide film 204 is formed, the sapphire substrate 201
The diffusion of aluminum into the silicon layer 202 is ignored. Thereafter, as shown in Fig. c, after selectively leaving the silicon layer 202, impurities are diffused into the source region 206 and drain region 207 using the silicon dioxide film 205 as a mask. At this time, the silicon layer 202 and the sapphire substrate 20
Since the silicon oxide film 204 is interposed between the sapphire substrate 201 and the silicon layer 202, diffusion of aluminum from the sapphire substrate 201 to the silicon layer 202 is suppressed. Therefore, a sapphire substrate 201, a silicon layer 202, a silicon layer 2 as shown in FIG.
Oxide film layer 2 interposed between 02 and sapphire substrate 201
04, source region 206, drain region 207, gate film 208, silicon dioxide film 209, 209' covering the surface of silicon layer 202 other than the gate film, and metal wiring 210
, 211, 212 of the first embodiment of the present invention.
Get an S-type semiconductor device. SO of the first embodiment of this invention
According to the S-type semiconductor device, since the oxide film 204 is interposed between the sapphire substrate 201 and the silicon layer 202, and there is no diffusion of aluminum from the sapphire substrate 201 into the silicon layer 202, the electrical conductivity of the silicon layer 202 and impurities are reduced. The concentration does not change and therefore the threshold voltage, source 20
This has the great advantage that various electrical characteristics such as withstand voltage between the drain 207 and the drain 207 can be kept stable.

第3図を参照すれば本発明の第2の実施例のSOS型半
導体装置は先ずa図の如くサフアイア基板301の上に
シリコン層302を成長させた後選沢的にシリコン層3
02表面を二酸化シリコン膜303,303′で被覆し
た後酸素イオンをシリコン層302の一部304に打ち
込む。
Referring to FIG. 3, in the SOS type semiconductor device according to the second embodiment of the present invention, a silicon layer 302 is first grown on a sapphire substrate 301 as shown in FIG.
After the surface of silicon dioxide 302 is covered with silicon dioxide films 303 and 303', oxygen ions are implanted into a portion 304 of the silicon layer 302.

その後b図に示す如くシリコン層302を選択的に残し
、酸素が打ち込まれたシリコン層304の上を二酸化シ
リコン膜305で被つた後、ソース領域306ドレイン
領域307に不純物を拡散すると同時にサフアイア基板
301とシリコン層302の間に酸化膜308を形成せ
しめる。次にMOS型素子を組み込んだ通常のSOS型
半導体装置と同様の作り方によつてc図に示されるサブ
↑イア基板301とその上に成長されたシリコン層30
2と、ソース領域306ドレイン領域307と、サフア
イア基板301とシリコン層302の間に介在する酸化
シリコン膜308とゲート膜309、ゲート部分以外の
シリコン層302の表面を被う二酸化シリコン膜310
,310′と金属配線311,312,313から成る
構造をとる。この第2の実施例によればサフアイア基板
301とシリコン層302の間に介在する酸化膜308
はゲート膜309の下の1部分のみであるから、a図に
於いて酸素イオンをシリコン層の304の部分に打ち込
んだ際に乱れたシリコン層302の結晶構造は、b図の
プロセスに於いて近くにサフアイア基板301の結晶格
子が存在するために容易に回復し従つてより性能の良い
SOS型半導体装置がえられるという利点を有する。
Thereafter, as shown in Figure b, the silicon layer 302 is selectively left and the silicon layer 304 into which oxygen has been implanted is covered with a silicon dioxide film 305, and impurities are diffused into the source region 306 and drain region 307, and at the same time the sapphire substrate 301 is An oxide film 308 is formed between the silicon layer 302 and the silicon layer 302. Next, a sub-↑ia substrate 301 and a silicon layer 30 grown thereon as shown in Fig. c are prepared in the same manner as a normal SOS type semiconductor device incorporating a MOS type element.
2, a source region 306, a drain region 307, a silicon oxide film 308 and a gate film 309 interposed between the sapphire substrate 301 and the silicon layer 302, and a silicon dioxide film 310 covering the surface of the silicon layer 302 other than the gate portion.
, 310' and metal wirings 311, 312, 313. According to this second embodiment, the oxide film 308 interposed between the sapphire substrate 301 and the silicon layer 302
is only a portion below the gate film 309, so the crystal structure of the silicon layer 302 that is disturbed when oxygen ions are implanted into the silicon layer 304 in FIG. Since the crystal lattice of the sapphire substrate 301 exists nearby, it has the advantage that recovery is easy and an SOS type semiconductor device with better performance can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のSOS型半導体装置を説明するための断
面図、第2図は本発明の第1の実施例を説明するための
断面図、第3図は本発明の第2の実施例を説明するため
の断面図である。 101,201,301はサフアイア基板、102,2
02,302はシリコン層、103,104,104′
,205,209,209′,303,303′,30
5,306,306′は二酸化シリコン膜、104,2
06,306はソース領域、105,207,307は
ドレイン例域、106,208,309はゲート膜、2
04,308は酸化シリコン膜、108,109,11
0,210,211,212,311,312,313
は金属配線。
FIG. 1 is a sectional view for explaining a conventional SOS type semiconductor device, FIG. 2 is a sectional view for explaining a first embodiment of the present invention, and FIG. 3 is a second embodiment of the present invention. FIG. 2 is a sectional view for explaining. 101, 201, 301 are sapphire substrates, 102, 2
02, 302 are silicon layers, 103, 104, 104'
, 205, 209, 209', 303, 303', 30
5, 306, 306' are silicon dioxide films, 104, 2
06, 306 are source regions, 105, 207, 307 are drain regions, 106, 208, 309 are gate films, 2
04, 308 is a silicon oxide film, 108, 109, 11
0,210,211,212,311,312,313
is metal wiring.

Claims (1)

【特許請求の範囲】[Claims] 1 上に設ける半導体層に対して導電型決定不純物とな
る元素をその構成成分として含有している性質の単結晶
絶縁基板と、該単結晶絶縁基板上に形成された半導体の
酸化物層と、該酸化物層上に存在する単結晶半導体層と
を含み、該単結晶半導体層内に素子もしくは素子の一部
が形成されていることを特徴とする半導体装置。
1. A single-crystal insulating substrate having a property that contains as a constituent element an element that serves as a conductivity type-determining impurity for a semiconductor layer provided thereon, and a semiconductor oxide layer formed on the single-crystal insulating substrate; A semiconductor device comprising: a single crystal semiconductor layer existing on the oxide layer; and an element or a part of the element is formed within the single crystal semiconductor layer.
JP49045228A 1974-04-22 1974-04-22 semiconductor equipment Expired JPS5931226B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP49045228A JPS5931226B2 (en) 1974-04-22 1974-04-22 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP49045228A JPS5931226B2 (en) 1974-04-22 1974-04-22 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS50141283A JPS50141283A (en) 1975-11-13
JPS5931226B2 true JPS5931226B2 (en) 1984-07-31

Family

ID=12713393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP49045228A Expired JPS5931226B2 (en) 1974-04-22 1974-04-22 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS5931226B2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51121270A (en) * 1975-04-17 1976-10-23 Seiko Epson Corp Semiconductor device
JPS52115667A (en) * 1976-03-25 1977-09-28 Agency Of Ind Science & Technol Semiconductor device
JPS5317068A (en) * 1976-07-30 1978-02-16 Fujitsu Ltd Semiconductor device and its production
JPS5843570A (en) * 1981-09-09 1983-03-14 Toshiba Corp Semiconductor device and manufacture thereof
JPS5884422A (en) * 1981-11-13 1983-05-20 Oki Electric Ind Co Ltd Manufacture of semiconductor device
JPS6169145A (en) * 1984-09-12 1986-04-09 Toshiba Corp Manufacture of semiconductor substrate

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5438452B2 (en) * 1972-06-09 1979-11-21

Also Published As

Publication number Publication date
JPS50141283A (en) 1975-11-13

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