JPS6224891B2 - - Google Patents
Info
- Publication number
- JPS6224891B2 JPS6224891B2 JP51139983A JP13998376A JPS6224891B2 JP S6224891 B2 JPS6224891 B2 JP S6224891B2 JP 51139983 A JP51139983 A JP 51139983A JP 13998376 A JP13998376 A JP 13998376A JP S6224891 B2 JPS6224891 B2 JP S6224891B2
- Authority
- JP
- Japan
- Prior art keywords
- relay
- circuit
- input signal
- output
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Relay Circuits (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】
本発明はリレーを用いて信号の保持を計るリレ
ーラツチ回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a relay latch circuit that uses a relay to hold a signal.
今まで用いられているラツチ回路、記憶回路
は、フリツプフロツプを用いていた。このため、
大きな雑音が入ると、誤動作を起すため、種々の
誤動作対策が必要であつた。 The latch circuits and memory circuits used so far have used flip-flops. For this reason,
When large noises enter, malfunctions occur, so various countermeasures against malfunctions are required.
本発明は以上のような従来の欠点を除去しよう
とするものである。 The present invention seeks to eliminate the above-mentioned drawbacks of the prior art.
すなわち、本発明は、リレーの動作時間以上の
パルスを入れることによつて、初めて動作し、ま
た、リレーの復帰時間以上にパルスを入れたとき
にリセツトされるリレーラツチ回路とし、大きな
ノイズに対しても誤動作することのないようにし
たところに特徴をもつものである。 That is, the present invention is a relay latch circuit that operates for the first time by applying a pulse longer than the relay's operating time, and is reset when a pulse is applied longer than the relay's return time, and is resistant to large noises. It is also characterized by the fact that it does not malfunction.
以下、本発明を実施例の図面により説明する。 The present invention will be explained below with reference to drawings of embodiments.
図面において、論理積回路１の入力Ｂはリセツ
ト入力であり、リセツトする時以外は論理“１”
状態である。論理回路２の入力Ａは、セツト入力
であり、セツトする時以外は論理“０”である。 In the drawing, input B of the AND circuit 1 is a reset input, and the logic is "1" except when resetting.
state. Input A of logic circuit 2 is a set input, and is at logic "0" except when setting.
リレー接点４，５はリレーコイル３で動作し、
また復帰するものであり、動作時間をt3、復帰時
間をt4とし、セツト入力信号Ａのパルス幅をt1、
リセツト入力信号Ｂのパルス幅をt2とする。 Relay contacts 4 and 5 are operated by relay coil 3,
In addition, the operation time is t3 , the return time is t4 , and the pulse width of the set input signal A is t1 ,
Let the pulse width of reset input signal B be t2 .
t1t3なるセツト入力信号Ａが論理和回路２に
入力されると、その出力Ｅとリレーコイル３によ
つてリレー接点４，５はt3後に接点を閉じる。リ
レー接点４の一方は電源電圧ＶEに接続されてい
るので、リレー接点４が動作すると同時に論理積
回路１の出力Ｄは論理“１”になり、論理和回路
２の出力Ｅはセツト入力信号Ａが無くなつた状態
でも論理“１”状態を持続し、したがつてリレー
６はラツチし続け、記憶状態を保つ。 When a set input signal A of t 1 t 3 is input to the OR circuit 2, the output E and the relay coil 3 cause the relay contacts 4 and 5 to close after t 3 . Since one side of the relay contact 4 is connected to the power supply voltage VE , the output D of the AND circuit 1 becomes logic "1" at the same time as the relay contact 4 operates, and the output E of the OR circuit 2 becomes the set input signal. Even when A is gone, the logic "1" state remains, so the relay 6 continues to latch and maintains the memorized state.
次にt2≧t4なるリセツト入力信号Ｂを論理積回
路１に入れると、その論理積回路１の出力Ｄは論
理“０”となり、リレー接点４，５はt4後に復帰
する。リレー接点４が復帰すると、そのリレー接
点４より入力されている論理積回路１の入力信号
Ｃは論理“０”となり、リセツト入力信号Ｂが無
くなつても出力Ｄは論理“０”である。 Next, when a reset input signal B with t 2 ≧t 4 is input to the AND circuit 1, the output D of the AND circuit 1 becomes logic "0", and the relay contacts 4 and 5 are restored after t 4 . When the relay contact 4 returns, the input signal C of the AND circuit 1 inputted from the relay contact 4 becomes logic "0", and even if the reset input signal B disappears, the output D remains logic "0".
また、リレー接点５は、論理回路の電源電圧以
外の電圧を得たい時に使用できるようにしたもの
である。 Further, the relay contact 5 can be used when it is desired to obtain a voltage other than the power supply voltage of the logic circuit.
以上のように本発明のリレーラツチ回路は構成
されるため、リレーの動作時間、復帰時間が数ｍ
〜数十ｍsecと長いのでデユテイサイクルの長い
ノイズに対しても誤動作せず、自己帰還をかけて
いるため動作が確実となり、従来のフリツプフロ
ツプ回路のような他の記憶回路に比べて回路が簡
単でコストの点でも有利とすることができるなど
の数多くの利点をもち、工業的価値の大なるもの
である。 Since the relay latch circuit of the present invention is configured as described above, the operating time and return time of the relay are several meters.
Since it is long (~several tens of milliseconds), it does not malfunction even in the presence of noise with a long duty cycle, and since it uses self-feedback, it operates reliably, and the circuit is simpler than other memory circuits such as conventional flip-flop circuits. It has many advantages such as being advantageous in terms of cost and is of great industrial value.
図面は本発明のリレーラツチ回路の一実施例を
示す電気的回路図である。
１……論理積回路、２……論理和回路、３……
リレーコイル、４，５……リレー接点、６……リ
レー。
The drawing is an electrical circuit diagram showing one embodiment of the relay latch circuit of the present invention. 1...AND circuit, 2...OR circuit, 3...
Relay coil, 4, 5...Relay contact, 6...Relay.
Claims (1)
ツト入力信号が印加される論理積回路と、この論
理積回路の出力とセツト入力信号とが印加される
論理和回路と、この論理和回路の出力により励磁
されるリレーコイルと、このリレーコイルによつ
て動作されるリレー接点と、このリレー接点を介
して上記論理積回路の他の入力端子に電圧を印加
する電源とを具備し、上記リレーのリレー動作時
間より長いセツト入力信号で上記リレーを閉成
し、上記リレーの復記時間より長いリセツト入力
信号で上記リレーを開成することを特徴とするリ
レーラツチ回路。1. An AND circuit that has two input terminals and to which a reset input signal is applied, an OR circuit to which the output of this AND circuit and a set input signal are applied, and The relay includes a relay coil that is excited by the output, a relay contact that is operated by the relay coil, and a power source that applies voltage to another input terminal of the AND circuit through the relay contact. A relay latch circuit characterized in that the relay is closed by a set input signal longer than the relay operating time, and the relay is opened by a reset input signal longer than the repeating time of the relay.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13998376A JPS5363967A (en) | 1976-11-19 | 1976-11-19 | Relay ratch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13998376A JPS5363967A (en) | 1976-11-19 | 1976-11-19 | Relay ratch circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5363967A JPS5363967A (en) | 1978-06-07 |
| JPS6224891B2 true JPS6224891B2 (en) | 1987-05-30 |
Family
ID=15258201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13998376A Granted JPS5363967A (en) | 1976-11-19 | 1976-11-19 | Relay ratch circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5363967A (en) |
-
1976
- 1976-11-19 JP JP13998376A patent/JPS5363967A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5363967A (en) | 1978-06-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2739964B2 (en) | Clock switching circuit | |
| JPS6224891B2 (en) | ||
| GB772965A (en) | Shifting registers | |
| JPS5816076Y2 (en) | Pulse Shingou Henkansouchi | |
| JP3670067B2 (en) | Integrated circuit device | |
| JP2844883B2 (en) | Switch control circuit | |
| US2920193A (en) | Precise analogue store and impedance transformer | |
| US3393351A (en) | Relay flip-flop utilizing two relays | |
| US3118070A (en) | Electrical control circuits | |
| JPS6367300B2 (en) | ||
| JPH027586U (en) | ||
| US2848674A (en) | Drift-free magnetic amplifier circuit system | |
| US3182229A (en) | Relay actuating saturable inductor | |
| JPS5939100U (en) | Safety operation circuit using Matsuto switch | |
| JPS5948401B2 (en) | Sequence control device | |
| SU1046870A1 (en) | Stabilized d.c.vobtage/d.c. voltage converter | |
| GB1192783A (en) | A Levelmeter having a Wide-Band Input Amplifier | |
| RU1810924C (en) | Device for monitoring differential protective circuits | |
| JPS6218094B2 (en) | ||
| GB901215A (en) | Improvements in or relating to a fail safe electrical circuit | |
| JPS5823132A (en) | Method of self-holding relay | |
| JPH0690184B2 (en) | Input state memory circuit using relay | |
| JPS5880231A (en) | Pulse operation type relay drive circuit | |
| JPS5951179B2 (en) | semiconductor latching relay | |
| JPH01235119A (en) | Driving circuit for latching relay |