JPS6252475B2 - - Google Patents

Description

[Detailed Description of the Invention] Semiconductor memories can be configured as large-scale integrated circuits (LSI) due to the fact that stored information can be retrieved easily and quickly as electrical signals and with the development of integrated circuit (IC) technology. Due to its improved bit density and reliability, it has recently been used as a high-speed memory device for electronic computers.

However, unlike magnetic memories, semiconductor memories have a problem of so-called volatility, in which the stored contents disappear when the supply of bias current is cut off.

In order to obtain a semiconductor memory that does not have this drawback, research has been carried out on the memory function of semiconductor glasses such as chalcogenide glasses, but this research has not yet entered the practical stage at the time of the original filing of the present application.

On the other hand, as a non-volatile semiconductor memory,
In the field of silicon semiconductor ICs, an MNOS field effect transistor has been developed that has a structure of metal (M), silicon nitride (N), oxide film (O), and silicon (S). ₂ ) must be made so thin that carriers on the surface of the semiconductor substrate can tunnel through, so pinholes are likely to occur, and since the storage mechanism is based on trap levels, there is a risk of poor productivity and reproducibility. Similarly, at the time of the original application relating to the present application, it had not been put to practical use in electronic computers.

On the other hand, as a field of semiconductor memory other than these, there is a read-only memory (ROM) which takes advantage of the high bit density and high speed of semiconductor memory to read fixed storage contents. There are two ways to configure this ROM, one of which is to add fixed information to the crow mask used for photo-etching when making an IC. Another method is to create an IC uniformly regardless of the content to be stored, and then electrically write information in accordance with the content to be stored.

As for the latter method, three methods are known. The first method is to fuse the wiring with a current pulse, the second method is to use the memory characteristics of alumina traps, and the third method is to blow the wires by cutting the drain of the MOS transistor when no channel current is flowing. Then, carriers of the same conductivity type as the semiconductor substrate are injected into the oxide film due to avalanche breakdown of the junction between the semiconductor substrates, and this carrier charges the polycrystalline silicon layer embedded in the oxide film, thereby providing information. This is the method of writing.

Since the present invention is an improvement on the third method among these three methods, this conventional third method will first be explained in more detail with reference to FIG.

As shown in FIG. 1A, a semiconductor substrate 1 includes a drain region 2 and a source region 3 having a conductivity type opposite to that of the semiconductor substrate 1 and having a high impurity concentration.
Gate silicon oxide film 4, silicon oxide film 4,
A field effect transistor 7 is formed by a silicon polycrystalline layer 6 buried between 5 and 5. In this field effect transistor 7, when the drain voltage is increased, a depletion layer 8 spreads from the drain 2 into the substrate 1, but especially in a portion 9 below the polycrystalline layer 6, as shown in FIG. As shown in FIG. 2, the electric field is concentrated, and therefore becomes higher in electric field than other parts of the depletion layer 8, and finally reaches the critical electric field for avalanche breakdown. At this time, electron-hole pairs 10 and 11 of electrons 10 and holes 11 are generated in this portion 9 as shown in FIG. It is accelerated in the direction of the oxide film 4 as shown by 12, thereby obtaining high energy and being injected into the oxide film 4. The electrons 10 thus injected pass through the oxide film 4 and reach the silicon polycrystalline layer 6, charging it negatively. On the other hand, holes 11 are transported to drain region 2 as shown by arrow 13 by the electric field.

By obtaining the charged state of the silicon polycrystalline layer 6 in this way, information can be written.
The written information can be erased by irradiating the field effect transistor with ultraviolet light or X-rays.

However, a channel is induced between the drain and source of the transistor to which writing has been performed, resulting in a depletion type. It is necessary to use a unit cell that is

The present invention takes the above-mentioned points into consideration. For example, even when the package is incorporated into a device, it is possible to write information as it is, and it is also possible to change the gate threshold voltage to the enhancement side after writing. It is an object of the present invention to provide a method for writing to a nonvolatile field effect transistor, which can also realize a simplified array configuration.

In order to achieve this object, the present invention provides a method for injecting carriers in a semiconductor substrate into an insulating film in a field effect transistor in which at least two or more types of junctions are formed in a semiconductor substrate. Among these plurality of junctions, only the junction for obtaining the desired charged state is selected, and the obtained carrier is injected by selectively causing avalanche breakdown only in the selected junction. In this way, writing can be performed on the enhancement side.

FIG. 2 shows a first example of a device structure that can be used in a preferred embodiment of the present invention. The storage field effect transistor 45 of this embodiment has a source region (second region) 26 and a drain region (fourth region) 25 of a conductivity type opposite to that of the semiconductor substrate (first region) 24. , gate insulating film 2 on substrate 24
2 and the insulating film 27 which is continuous therebetween.
A gate electrode 28 is embedded therein.

In this embodiment, a region (third region) 46 having a conductivity type different from that of the source region 26 and having a high concentration of impurities is formed in the source region 26 . On the other hand, the impurity concentration of the source region 26 is desirably selected to be a low value because it is effective if the depletion layer 47, which is thicker than the gate insulating film 22, spreads between the region 26 and the source region 26.

In such a configuration, there are essentially multiple connections that can cause avalanche yield. First, if avalanche breakdown occurs in the region near the substrate surface under the gate electrode 28 at the junction between the drain region 25 and the substrate 24, carriers from the substrate 24 are injected from that region into the insulating film 22, and this causes the first Gate electrode 28 is charged to a first charging state. In this charging state, the surface of the region 26 under the first gate electrode 28 has changed in a direction in which an inversion channel is difficult to be induced, and as will be described later, a second gate electrode is formed on the first gate electrode via an insulating film. When a gate electrode is provided, the threshold voltage of the field effect transistor whose source and drain are the surfaces of the region 46 and the region 24, respectively, as seen from the second gate electrode, changes more toward the enhancement side.

On the other hand, if avalanche breakdown occurs in the region 48 under the first gate electrode 28 at the junction of the source region 26 and the region 46 formed therein, the source will be deposited from this region 48 into the insulating film 22. Carriers in the region 26 (the charge of which has a sign opposite to that of the carriers injected from the substrate) are injected, thereby charging the first gate electrode 28 to a second charging state different from the first charging state. will be done.

In this charged state, the substrate surface under the first gate electrode 28 has changed in a direction in which an inversion channel is difficult to be induced, and as will be described later, a second gate electrode is placed on the first gate electrode via an insulating film. If you set
Since the gate threshold voltage seen from this second gate electrode has changed to the enhancement side, the threshold voltage when no writing is performed is designed to be enhancement, and the avalanche in this threshold voltage and region 48 occurs. By setting the voltage of the second gate electrode between the gate threshold voltage after breakdown, the transistor at one address in the array configuration can be read out without a complicated unit cell configuration.

Further, as can be inferred from the embodiment shown in FIG. 3, which will be described later, if the drain region 25 is not considered, avalanche breakdown may occur at the junction between the first region 24 and the second region 26, and in such a case, , a mechanism similar to that shown in FIG. 3, which will be described later, occurs.

In this way, conditions that can cause avalanche breakdown can be created from each of the plurality of junctions, but according to the present invention, the main structure of the field effect transistor shown in FIG. Only writing of information due to avalanche breakdown only from the second bonding region 48 is specified. If you do this,
As described above, the substrate surface under the first gate electrode 28 changes in a direction in which an inversion channel is difficult to be induced, and as described later, a second gate electrode is placed on the first gate electrode via an insulating film. , the gate threshold voltage seen from the second gate electrode changes more towards the enhancement side.

Note that in the illustrated configuration, even if the region 46 is formed of a material different from that of the semiconductor substrate 24 and the region 26, such as by a heterojunction, a shotgun junction, or the like, the same effect as described above can be obtained. It's obvious what you can do.

Further, FIG. 3 shows an embodiment in which an emitter junction and a collector junction of a transistor are used as two types of pn junctions.

In Figure 3, the buried electrode (first gate electrode)
28 is an emitter region (third region) 106 and a base region (second region) 1 via a gate insulating film 22.
05 (referred to as emitter junction)
A part 109 of a portion in contact with the semiconductor surface, a base region 105 and a collector region (first region) 102
The buried electrode 28 is disposed so as to cover a part 108 of the first junction (referred to as collector junction) in contact with the semiconductor surface, and the buried electrode 28 is located on the gate insulating film 22.
and is embedded in an insulating film 27 continuous thereto.

Even in such a configuration, avalanche yielding can originally occur at two junctions. That is, the emitter region 106 is reverse biased with respect to the base region 105 and the surface portion 10 of the emitter junction
By causing avalanche breakdown at 9, majority carriers (holes in the npn transistor, electrons in the pnp transistor) in the base region 105 are injected into the insulating film 22 and charge the buried electrode 28. On the other hand, base area 1
05 is reverse biased with respect to the collector region 102 to cause avalanche breakdown at the surface portion of the collector junction, majority carriers in the collector region 102 are injected into the insulating film 22, causing the buried electrode 28 to have the opposite sign to that described above. Charge. As described below, we specify writing by the latter injection to achieve the desired effect.

In the embodiment shown in FIG. 3, at least the emitter region 106, base region 105, and collector region 102 under the buried electrode 28 must be formed in this order so that the impurity concentration becomes smaller.
This is because the depletion layer spreads more toward the base junction in the emitter junction and more toward the collector in the collector junction, and carriers need to be injected from there. However, in parts other than under the buried electrode 28, the impurity concentration may be higher than that of the base region 105, such as the collector contact 107 and the collector buried layer 101, or the part under the base region, such as the buried layer 101, may have a higher impurity concentration than the base region 105. If a region with a high impurity concentration is provided, region 106 can be used as a collector and regions 101 and 102 can be used as emitters. Note that the region 104 is a region for base contact and for channel blocking that may occur on the region 105;
03 is a separation layer, and 100 is a substrate.

When a channel is generated above the region 105, if a second gate electrode is provided on the first gate electrode 28 as described later, the region 105 becomes a channel formation region, one of the regions 106 and 102 becomes a source, and the other becomes a channel formation region. It operates as a memory field effect transistor with a drain. In this case, if the collector junction is selected, avalanche breakdown at that junction will cause a gate threshold voltage change in the enhancement direction.

Similarly, in the embodiment shown in FIG. 2, a channel may be formed on the surface of the region 26, so in this case, the region 26 is used as a channel forming region, and one of the region 46 and the substrate 24 is used as a source. It operates as a field effect transistor with the other being the drain.

Note that although the embodiment shown in FIG. 3 has an isolated transistor structure, there is no isolation layer 103 and collector buried layer 101, and for example, the left half structure in FIG. Even when the collector region 102 is formed from a substrate such that the region 26 serves as a base and the substrate 24 serves as a collector, the function as a memory element can be sufficiently performed.

In the configurations of FIGS. 2 and 3, a second gate electrode may be provided on the insulating film 27 of the transistors 45 and 110, and in this case, in addition to the above-mentioned effects, the second gate electrode also provides The electric field accelerates carriers caused by avalanche breakdown, thereby increasing the writing speed.

Furthermore, as will be described later, in the embodiment shown in FIG. 4, the area of the region 26 facing the first gate electrode 28 is set larger than that of the region 24, which prevents avalanche breakdown between the regions 46 and 26. Therefore, when writing information, the potential of the first gate electrode follows the potential of the region 26, so that writing can be performed efficiently.

Although not specifically mentioned above, when forming a memory unit cell by forming other transistors on the same semiconductor substrate on which the memory field effect transistor according to the present invention is formed, for example, as shown in FIG. The thickness of the gate insulating film 22 of a transistor having a buried first gate electrode 28 as in the embodiment shown in FIG. It is better to increase the thickness of 22. In this way, the breakdown voltage of the drain junction of the other transistors can be made higher than the breakdown voltage of the transistor having the first gate electrode, and a unit cell with stable operation can be obtained.

As a result of an experiment using the field effect transistor 70 shown in FIG. 4 having the structure of the present invention but also having a second gate electrode, the relationship shown in FIG. 5 was obtained.

More specifically, the embodiment shown in FIG. 4 is an embodiment in which region 46 is connected to semiconductor substrate 24;
4 is made of n-type silicon with an impurity concentration of 5×10 ¹³ /cm ³ , the surface impurity concentration near the junction between the source region 26 and the region 46 is about 10 ¹⁶ /cm ³ , and the insulating film (SiO ₂ ) 22 The thickness of 1 ₁ is 1000 Å, the thickness of the insulating film (SiO ₂ ) 27 1 ₂ is 1000 Å, and the channel length L
is 10 μm, and it takes the voltage of the buried gate electrode (Si) to change from 0V to the equivalent of -4V when writing "1" to the substrate 24, and from -4V to equivalent to 0V when writing "0" to the substrate 24. measure time,
The result is expressed as the time t for the terminal voltage V _GS of the second gate electrode 23 (Al) and the source 26 (P).
Figure 5 shows what is expressed as .

In FIG. 5, the symbol I indicates a curve obtained when the drain terminal D and the source terminal S are grounded, a positive bias is applied to the substrate terminal B, and the reverse direction current in the junction between the source region 26 and the region 46 is 100 μA. , and the symbol indicates when the substrate terminal B is grounded, the drain terminal D is given a negative bias, the source terminal S is given a slight negative bias, and the reverse current at the junction between the substrate 24 and the drain region 25 is 10 μA. The resulting curve is shown.

From this measurement result, firstly, the selected information can be stored in a nonvolatile manner, secondly, by providing the second gate electrode 23, the writing time can be significantly speeded up, and thirdly, the writing time The time decreases inversely with the avalanche current during breakdown, and fourth, the field effect transistor is within the enhancement mode gate threshold voltage due to avalanche breakdown between the source region and region 46. It is demonstrated that the threshold voltage can be changed more toward enhancement.

As described above, according to the present invention, it is possible to obtain a semiconductor memory that combines the high speed of reading that semiconductor memory inherently has and the non-volatility of storage that has conventionally been achieved only by magnetic memory. be able to.

Further, such a memory can be easily manufactured at high density using conventional silicon gate technology or molybdenum gate technology without requiring any other special technology.

Furthermore, in the above explanation, the target was digital information whose memory content was "1" or "0".
It is obvious that it can also be used for non-volatile storage of analog information.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a field effect transistor used to explain a conventional information writing method, and FIGS. 2 and 3 are examples of structures of nonvolatile field effect transistors that can be used in each embodiment of the writing method of the present invention. 4 is a configuration diagram of a field effect transistor as an example for obtaining experimental results related to the present invention; FIG. 5 is a characteristic diagram of measurement results using the field effect transistor shown in FIG. 4; It is. In the figure, 22 is a gate insulating film, 23 is a second gate electrode, 24 and 100 are semiconductor substrates, 25 is a drain region, 26 is a source region, 27 is an insulating film, 2
8 is a first gate electrode, 45, 70, 110 are nonvolatile field effect transistors, 46 is a third region,
102 is a collector, 105 is a base, and 106 is an emitter.

Claims (1)

[Claims] 1. A first semiconductor region and a second semiconductor region provided to form a first junction in the surface of the first semiconductor region.
a third region provided to form a second junction in the surface of the second semiconductor region; a surface of the first region near the first junction; an insulating film provided across the region surface and the surface of the third region near the second junction; a first gate electrode provided in the insulating film; an inversion layer on a surface of the second semiconductor region below the first gate electrode and between the first semiconductor region and the third region; A writing method for writing in a state in which a channel is difficult to be induced; selectively causing avalanche breakdown only in the first junction under the first gate electrode among the first and second junctions; and inject carriers having the same polarity as the conduction type of the first region into the first gate electrode, thereby changing the charged state of the first gate electrode in the direction of the same polarity. How to write to non-volatile field effect transistors. 2 a first semiconductor region and a second semiconductor region provided to form a first junction in the surface of the first semiconductor region;
a third region provided to form a second junction in the surface of the second semiconductor region; a surface of the first region near the first junction; an insulating film provided across the region surface and the surface of the third region near the second junction; a first gate electrode provided in the insulating film; A nonvolatile field effect transistor comprising means for reverse biasing a junction, and a second gate electrode provided on the first gate electrode with an insulating film interposed therebetween. A writing method for writing in a state in which an inversion layer channel is difficult to be induced on the surface of the second semiconductor region between the first semiconductor region and the third region; , selectively inducing avalanche breakdown only at the first junction under the first gate electrode, and injecting carriers having the same polarity as the conduction type of the first region into the first gate electrode; A method for writing to a nonvolatile field effect transistor, characterized in that the charged state of the first gate electrode is changed in the direction of the same polarity. 3 a first semiconductor region and a second semiconductor region provided to form a first junction in the surface of the first semiconductor region;
a third region provided to form a second junction in the surface of the second semiconductor region; a surface of the first region near the first junction; an insulating film provided across a region surface and a surface of the third region near the second junction; and a first gate electrode provided in the insulating film; , the first gate electrode is extended over the surface of the first semiconductor region, and a third junction is formed under the first gate electrode on the surface of the semiconductor region, spaced apart from the second semiconductor region. In the non-volatile field effect transistor, the non-volatile field effect transistor is provided with a fourth region to be formed, and means for applying a reverse bias between the third region and the second region 1, under the first gate electrode. and a writing method for writing in a state in which an inversion layer channel is difficult to be induced on the surface of the first semiconductor region between the second and fourth semiconductor regions; the first, second, and third junctions; In the process, avalanche breakdown is selectively induced only at the second junction under the first gate electrode, and carriers having the same polarity as the conduction type of the second semiconductor region are transferred to the first gate electrode. A method for writing to a nonvolatile field effect transistor, characterized by injecting the same polarity into the first gate electrode and changing the charged state of the first gate electrode toward the same polarity. 4 a first semiconductor region and a second semiconductor region provided to form a first junction in the surface of the first semiconductor region;
a third region provided to form a second junction in the surface of the second semiconductor region; a surface of the first region near the first junction; an insulating film provided across the region surface and the surface of the third region near the second junction; a first gate electrode provided in the insulating film; and a second gate electrode provided on the first gate electrode, further extending the first gate electrode over the surface of the first semiconductor region, A fourth region is provided which forms a third junction under the first gate electrode and is spaced apart from the second semiconductor region, and a reverse bias is applied between the third region and the second region 1. In a nonvolatile field effect transistor comprising a means for applying , an inversion layer channel is difficult to be induced on the surface of the first semiconductor region under the first gate electrode and between the second and fourth semiconductor regions. A writing method for writing into a state; selectively inducing avalanche breakdown only in the second junction under the first gate electrode among the first, second, and third junctions; , a nonvolatile device characterized by injecting a carrier having the same polarity as the conductivity type of the second semiconductor region into the first gate electrode, and changing the charged state of the first gate electrode in the direction of the same polarity. How to write to a field effect transistor.