JPS643072B2 - - Google Patents

Description

[Detailed Description of the Invention] Semiconductor memory can be configured as a large-scale integrated circuit (LSI) due to the fact that stored information can be retrieved easily and quickly as an electrical signal, and due to the development of integrated circuit (IC) technology. Due to improved bit density and reliability, it has recently been used as a high-speed memory device for electronic computers.

However, unlike magnetic memories, semiconductor memories have a problem of so-called volatility, in which the stored contents disappear when the supply of bias current is cut off.

In order to obtain a semiconductor memory without this drawback, research has been conducted on the memory function of semiconductor glasses such as chalcogenide glass, but this has not yet entered the practical stage at the time of the original filing of the present application.

On the other hand, as a non-volatile semiconductor memory,
In the field of silicon semiconductor ICs, an MNOS field effect transistor has been developed that has a structure of metal (M), silicon nitride (N), oxide film (O), and silicon (S). ₂ ) must be made so thin that carriers on the surface of the semiconductor substrate can tunnel through, so pinholes are likely to occur, and since the storage mechanism is based on trap levels, there is a risk of poor productivity and reproducibility. Similarly, at the time of the original application relating to the present application, it had not been put to practical use in electronic computers.

On the other hand, as a field of semiconductor memory other than these, there is a read-only memory (ROM) which takes advantage of the high bit density and high speed of semiconductor memory to read fixed storage contents.

There are two ways to configure this ROM, one of which is to add fixed information to the glass mask used for photo-etching when making ICs.

The other method is to create an IC uniformly regardless of the content to be stored, and then write information electrically depending on the content to be stored. There are three further known methods.

The first method is to fuse the wiring with a current pulse, the second method is to use the memory characteristics of alumina traps, and the third method is to melt the junction between the drain of the MOS transistor and the semiconductor substrate when no channel current is flowing. This method uses avalanche breakdown to inject carriers of the same conductivity type as the semiconductor substrate into the oxide film, and this carrier charges the polycrystalline silicon layer embedded in the oxide film to write information. .

Since the present invention is an improvement on the third method among these three methods, this conventional third method will first be explained in more detail with reference to FIG.

As shown in FIG. 1A, a semiconductor substrate 1 includes a drain region 2 and a source region 3 having a conductivity type opposite to that of the semiconductor substrate 1 and having a high impurity concentration.
Gate silicon oxide film 4, silicon oxide film 4,
A field effect transistor 7 is formed by a silicon polycrystalline layer 6 buried between 5 and 5.

In this field effect transistor 7, when the drain voltage is increased, the drain region 2
The depletion layer 8 spreads in the substrate 1 from then on, but the electric field concentrates particularly in the lower part 9 of the polycrystalline layer 6 as shown by the arrow, so that the electric field is higher than in other parts of the depletion layer 8. Eventually, it reaches a critical electric field like an avalanche.

At this time, in this part 9, as shown in FIG.
occurs, and if the substrate 1 is, for example, n-type, electrons 10
is accelerated in the direction of the oxide film 4 as shown by the arrow 12 by the electric field, thereby obtaining high energy and being injected into the oxide film 4. The electrons 10 thus injected pass through the oxide film 4 and reach the silicon polycrystalline layer 6, charging it negatively.
On the other hand, holes 11 are transported to drain region 2 as shown by arrow 13 by the electric field.

By obtaining the charged state of the silicon polycrystalline layer 6 in this way, information can be written, and on the other hand, the written information can be erased by irradiating the field effect transistor with ultraviolet rays or X-rays. .

However, in general, in such semiconductor memories, it has not been possible to specify in which part of the junction between the drain region 2 and the substrate 1 the process of avalanche breakdown and carrier injection mainly occurs, resulting in variations in the write characteristics of individual cells. It was happening.

In view of this point, the present invention makes it possible to specify the part where avalanche breakdown occurs during writing, thereby improving designability. It aims to provide sexual memory.

The basic features of the present invention are a first semiconductor region, drain and source regions formed separately in the first semiconductor region, and at least the first semiconductor region between the drain and source regions. It consists of at least a gate insulating film attached to the surface of the semiconductor region, an insulating film continuous with the gate insulating film, and a first gate electrode embedded between the gate insulating film and the insulating film continuous with the gate insulating film, and writing is performed electrically. I will go to
As an improvement in a nonvolatile memory in which erasing is performed only by irradiation with ultraviolet rays or X-rays, as in the prior art, further: At least a portion of the surface of the first semiconductor region between the source and drain is provided with: A high impurity concentration region is provided that has the same conductivity type as the first semiconductor region and that specifies a carrier injection portion with respect to the first gate electrode or improves carrier injection efficiency. be.

Therefore, in the present invention, in addition to the aforementioned avalanche breakdown, as a new method for injecting carriers in a semiconductor substrate into an insulating film, hot carriers are injected into the pinch-off (high field velocity saturation) region of a channel of a field effect transistor. It is also possible to adopt a method of obtaining and injecting it.

These features of the present invention will become clear from the detailed description below with reference to the accompanying drawings.

First, referring to FIG. 2, an example of a new storage method that can be adopted in the nonvolatile memory of the present invention will be described.
Except that the second gate electrode 23 is provided on the insulating film 27 made of a silicon oxide film, and also in accordance with the spirit of the present invention, a high impurity concentration region is provided at a location specified as described below. It is similar to the field effect transistor shown in FIG. 1, except that it is provided (not shown in the figure).

In this FIG. 2, 22 is a gate insulating film;
4 is a semiconductor substrate, 25 is a drain region, 26 is a source region, 27 is an insulating film continuous to the gate insulating film 22, and 28 is the gate insulating film 22 and the insulating film 27.
A first gate electrode is buried in between, 23 is a second gate electrode provided to be capacitively coupled to the first gate electrode, and 29 is a depletion layer.

By the way, in order to inject carriers in the substrate 24 into the gate insulating film 22 of the field effect transistor 21, it is necessary to give the carriers enough energy to overcome the barrier between the substrate 24 and the insulating film 22. Therefore, in the case of FIG. 2, in order to charge the gate electrode 28 to a predetermined polarity, the field effect transistor 21 is put into a pinch-off state, thereby causing the carrier to become a hot carrier near the drain side of the channel. None, this is injected into the insulating film 22.

To explain this further, in FIG. 2, first, a potential is applied to the gate electrode 23 to generate an electric field as shown by the arrow between it and the buried gate electrode 28, and therefore, based on this electric field, A potential is applied to gate electrode 28.

On the other hand, a channel 30 is induced in the substrate 24,
A pinch-off region 31 is formed near the drain region 25 side of this channel 30 .

Therefore, an electric field as shown by the arrow is generated between the electrode 28 and the substrate 24.

In this state, it is considered that a current continuity relationship almost holds within the channel 30 between the carrier density n _p at the end of the channel 30 on the source region 26 side and the carrier density n _p at the pinch-off region 31. , n _p・V _p = n _p・V _p = I/q, n _p ≫ n _p (where, V _p is the carrier velocity at the side edge of the source region 26, V _p is the carrier velocity at the pinch-off region 31, and I channel current), and therefore it is clear that V _p ≫ V _p .

This means that in the pinch-off region 31, the carriers in the channel 30 have the highest energy among the carriers in the crystal. In this specification, the term "pinch-off region" has the broad meaning of a channel region in which the channel carrier velocity approaches velocity saturation and becomes a so-called "hot" region.

Therefore, compared to the potential of the electrode 28 buried in the insulating film 22, the potential of the region 31 is higher in the case of a p channel and lower in the case of an n channel, even if the absolute value of the drain voltage is large. The carrier that has obtained energy in the pinch-off region 31 is connected to the channel 30 or the pinch-off region 31 on the source side of the pinch-off region 31 and the pinch-off region 31.
The first gate electrode 28 has the same polarity as the carrier of the channel 30 and is injected into the insulating film 22 and accelerated to reach the electrode 28. is charged.

As a result, the gate threshold voltage seen from the second gate of the transistor changes more in the enhancement direction, so the voltage of the second gate electrode is set between the gate threshold voltage before writing and the threshold voltage after writing. By setting , information of a transistor at one address in the array configuration can be read out without a complicated unit cell.

Further, according to the configuration shown in the second figure for realizing the first method, since the electrode 23 is provided, it is possible to apply a potential to the electrode 28 to accelerate the carriers injected from the pinch-off region 31. As a result, the first gate electrode 28 can be sufficiently charged by keeping the carrier injection speed and efficiency high, and a storage field effect transistor with good performance as a storage element can be obtained.

Furthermore, since the number of hot carriers is proportional to the channel current, the larger the channel current, the faster the first gate electrode can be charged. Channel current is also supplied from the source by avalanche breakdown, but since the bias condition of the second gate electrode 23 is such that a large current can flow between the source and drain, it is necessary to flow the current between the source and drain. This also speeds up charging.

FIG. 3 shows a modification of the configuration shown in the second diagram; in this case,
The electrodes 33 embedded in the insulating films 22 and 27 are
It is made to overlap only with other areas except for a part of the channel area. According to this configuration, the second
In addition to having the effect of the illustrated configuration, an electric field 34 is formed directly between the remaining portion of the channel region and the portion of the gate electrode 23 that faces it, so that this electric field causes the pinch-off region 31 to carrier injection efficiency can be further promoted.

Further, in this case, since the channel 35 can be induced by the electric field 34 in the remaining portion of the channel region, by changing and controlling the electric field 34, the field effect transistor 21 can be controlled more reliably than in the configuration shown in FIG. On/off operation can also be controlled.

FIG. 4 shows yet another modification of the configuration shown in FIG. 2, in which the electrode 33 is provided with a through hole 36 across its thickness.

In this way, the electrode 23 and the through hole 36 of the substrate 24
Since an electric field 37 is formed directly between the opposing portions, this electric field 37 induces a channel 38 in the region of the substrate 24 facing the through hole 36, and a pair of pinch-off regions are formed at each end of the channel 38. 39 and 39'. The hot carriers in regions 39 and 39' are therefore directly accelerated by the electric field 37, thereby further enhancing the carrier injection rate and efficiency.

Furthermore, FIG. 5 shows a modification of the configuration shown in FIG. 3, in which the electrode 33 has both the offset structure shown in FIG. 3 and the through hole 36 shown in FIG. If this is done, the same effects as explained with reference to FIGS. 3 and 4 can be obtained.

Although not specifically shown in FIGS. 2 to 5, in the present invention, the potential of the pinch-off region in each of these configurations is set to a potential suitable for reaching the buried first gate electrode. In order to achieve this, the impurity concentration of the substrate in the pinch-off region and its vicinity is made higher than in other parts.

On the other hand, even when using the nonvolatile memory of the present invention, when writing information using avalanche breakdown instead of the above-mentioned hot carrier injection, the potential of the second gate electrode 23 is removed, and the potential of the second gate electrode 23 is removed, e.g. 24 and apply a voltage higher than the breakdown voltage between the drain region 25 and the substrate 24.

Then, an avalanche breakdown occurs between the drain region 25 and the substrate 24, and based on the electric field between the electrode 28 and the breakdown point, carriers of charge in the channel carrier and carriers of charge with the opposite sign to the electrode 28 are transferred to the electrode 28. It is accelerated in the direction of and injected into the insulating film 22.

Also at this time, if a high impurity concentration region is provided in accordance with the spirit of the present invention near the junction between the substrate and the region that is generally reverse biased during writing, as exemplified by the drain region, carrier injection is possible. As a result of the portion being specified to that portion, the reproducibility of writing can be improved.

As described above, according to the present invention, it is possible to obtain a semiconductor memory that combines the high speed of reading that semiconductor memory inherently has and the non-volatility of storage that has conventionally been achieved only by magnetic memory. be able to.

Further, such a memory can be easily manufactured at high density using conventional silicon gate technology or molybdenum gate technology without requiring any other special technology.

Furthermore, since the impurity concentration of the substrate in the pinch-off region and its vicinity is higher than in other parts, it is possible to specify the location where carrier charges are injected into the first gate electrode, improving design efficiency and improving carrier injection efficiency. Improved. Furthermore, even when carrier injection is performed by causing avalanche breakdown, by providing a region with a high impurity concentration near the junction for this purpose, it is possible to similarly enjoy the above-mentioned effects of specifying the carrier injection portion. I can do it.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a field effect transistor used to explain a conventional information writing method, Figures 2 and 3 are
4 and 5 are block diagrams of field effect transistors as embodiments of the present invention, respectively. In the figure, 22 is a gate insulating film, 23 is a second gate electrode, 24 is a semiconductor substrate, 25 is a drain region, 26 is a source region, 27 is an insulating film, 28 is a first gate electrode, 30, 35, 38 is a channel,
31, 39, 39' are pinch-off regions, and 36 is a through hole.

Claims (1)

[Claims] 1. A first semiconductor region, drain and source regions formed separately in the first semiconductor region, and at least the first semiconductor region between the drain and source regions. It consists of a gate insulating film attached to the surface, a continuous insulating film, and a first gate electrode embedded between the gate insulating film and the continuous insulating film, and writing is performed electrically. The non-volatile memory is erased only by irradiation with ultraviolet rays or X-rays; at least a portion of the surface of the first semiconductor region between the source and drain has the same conductivity type as the first semiconductor region; A nonvolatile memory characterized in that a carrier injection portion with respect to the first gate electrode is specified or a high impurity concentration region is provided to improve carrier injection efficiency. 2. The nonvolatile memory according to claim 1, wherein the continuous insulating film has a second gate electrode capacitively coupled to the first gate electrode on its surface.