JPS6360545B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention proposes a semiconductor device, particularly an MIS type (insulated gate type) field effect semiconductor device (hereinafter referred to as MIS/FET), and a semiconductor device to which the same is applied.

The present invention selectively provides a first region made of a semiconductor or conductor of the same or different conductivity type on the surface of a semiconductor substrate of one conductivity type. The purpose is to provide a layer having a triangular cross section as a gate electrode, the height of which is approximately the same as the first region, and the width of which is approximately the same as the thickness of the coating formed at the corner of the layer.

In the present invention, this first region is used as a region constituting a source or drain, the triangular layer is used as a gate electrode, and a second region of the same conductivity type as the first region is provided below the other end of this layer. A MIS/FET can be configured by providing it as a drain or source, and in addition, a capacitor can be provided at the same time on this first region, or a high resistance layer can be provided as a vertical resistor in a part of this first region. It is characterized by

As shown in FIG. 1, a conventional MIS/FET has a gate insulator 11 and a gate electrode 6 on a semiconductor substrate 1.
A pair of impurity regions 13 and 14 were provided with the source and drain spaced apart from each other, and their leads 9 and 10 were provided on the field insulator 2.

Conventionally, a pair of source and drain regions have always been formed on the same plane on a semiconductor substrate under both ends of a gate insulator. Therefore, in this case, IC, LSI
Because of the planar processing, there is no out-of-focus during mask alignment, which is preferable. However, the channel length between the source and drain is determined by the gate electrode width, and the smaller the width, the shorter the channel length. However, due to the photo-etching process, the thickness must be reduced to 1/2 to 1/5 of the width, which increases the sheet resistance of the electrode and reduces the channel length to 1μ or less. It was realistically impossible to do so.

In the present invention, the width corresponding to the channel length of the layer functioning as a gate electrode can be extremely small, 0.1 to 1μ, and the thickness is 0.5 to 1μ, which has a thick triangular shape, compared to conventional gate electrodes. It has a cross-sectional structure that is long in the vertical direction.

In addition, since it is long in the vertical direction, its strength is not sufficient as it is. To compensate for this intensity, a first region is therefore provided along this layer. In addition, this first region can be configured as part or all of the source or drain in MIS/FET, and this region can also be configured as other leads, resistors, capacitors, or sources or drains of other MIS/FETs. Therefore, the semiconductor device of the present invention is characterized in that it is provided in a convex shape closely on the surface of the semiconductor substrate so that the semiconductor device of the present invention can increase the density of its elements by scaling the conventional lateral area. The aim is to achieve this by actively providing the height in the height direction, rather than in the height direction.

Examples of the present invention will be described below with reference to the drawings.

Example 1 Semiconductor substrate, for example silicon single crystal semiconductor 10
0, P type 1 to 5 Ωcm was selected. Thereafter, as shown in FIG. 2A, a field insulator 2 was buried and formed to a thickness of 0.5 to 2 .mu.m using a first photomask (2) using a selective oxidation method. Furthermore, after thoroughly cleaning the surface, a low pressure vapor phase method (LPCVD) was applied on the substrate.
A silicon semiconductor doped with an impurity of one conductivity type, for example, an N ⁺ type impurity, was formed to a thickness of 0.5 to 1.5 μm using a method (method).

Furthermore, the edge around that side was selectively removed using known photolithography (2007) while being careful not to taper-etch the edge to the extent possible, leaving the first region 3. For example, a fluorine-based gas excited by a 2.45 GHz microwave was applied perpendicularly to the substrate from above to perform etching. As a result, I was able to make a clean, almost vertical cut at an angle of 85 to 90 degrees around the side. In this embodiment, the width of this first region is 3 to 200 microns. A part of the capacitor 15 is formed over the field insulator 2 to increase the capacitance of the capacitor 15 and reduce the parasitic capacitance between the region 14 and the substrate 1 as in this embodiment. Thereafter, a silicon nitride film 4 with a thickness of 50 to 200 Å was formed on the first region and the side surfaces as well as on the surface of the semiconductor substrate 1. This silicon nitride film absorbs ammonia gas from 900~
The activated ammonia or its decomposition product nitrogen is removed by high-pressure nitriding method in which the pressure is increased to 5 to 10 atm at 1100℃, or by reducing the pressure to 0.1 to 10 torr and generating plasma using high-frequency induction energy.
It was formed by heating at 1100°C and nitriding it.

This coating 4 may be made of another insulating film such as silicon oxide or metal oxide, and this first region is also not made of impurity-doped silicon but is made of an intrinsic or intrinsic P ⁺ or N ⁺ type semiconductor. It may also be a multilayer film of a metal or a metal compound, especially Mo, W or a silicide thereof (Mo ₂ Si, W ₁ Si, etc.).

Next, a known plasma etching method using CF ₄ gas was used. An opening 41 ( ) was provided. Next, a conductor or semiconductor coating 5 is applied to the upper surface, for example, under reduced pressure.
It was formed to a thickness of 0.1 to 1μ by CVD method. It is extremely important that the coating 5 be formed to have a uniform thickness on the top and side surfaces and a predetermined thickness. In this way, the thickness direction of the side periphery of the first region 3 is the same as the thickness of the coating 5, but
The apparent thickness of that area from above the board is 2 to 5
It is possible to double the thickness, which is an extremely significant feature.

For example, P-type silicon is formed to a thickness of 0.10 to 1.5 microns, particularly 0.5 to 0.7 microns. Furthermore, the concentration of P or N type impurities added to this film depends on the degree of conductivity of this electrode 6, and the opening 4 between the film and the semiconductor substrate 1.
The selection is made based on three factors: whether the ohmic contact at 1 is of the PN junction type or whether the semiconductor substrate under the gate insulator 11 under the film is of the depletion type or the enhancement type.

For example, if the substrate 1 is P type and the interface is to be made more P, the coating 5 may be P ⁺ type and made of silicon. In addition, in order to make ohmic contact between this film and the second region 3 provided on the semiconductor substrate, in this embodiment, N ⁺ is used for the second region 13 and its lead 9, and finally the gate electrode is The impurities necessary to make only the P ⁺ portion were added by adding 5 to 50 times as much P ⁺ impurities to offset them.

Furthermore, this film 5 may be formed without adding impurities, and after step (C), P ⁺ is added only to the gate electrode portion, and N ⁺ is formed in the region that will become the lead 9 in a later step. Further, if the second region 13 and the gate electrode 6 are of the same conductivity type, the coating 5
may be of type N ⁺ .

In addition, when this coating 5 is made of a compound or mixture of silicon and tungsten molybdenum such as W ₂ Si or Mo ₂ Si, the coating is formed by LPCVD, electron beam evaporation, or reactive sputtering to a thickness of 0.3 to 1.5μ, especially 0.5 to
It is sufficient to form a 0.7μ silicon.

Thus, Figure 2B was obtained.

Next, as shown in FIG. 2C, a photoresist (for example, OMR-83 manufactured by Tokyo Ohka) was coated on the upper surface on the area to be left as part of the film, and after exposure, photoetching was performed. For this etching, it is important to use an etching method with very little or no side etching and taper etching, rather than the conventional solution etching method.
Specifically, a reactive gas for etching such as nitrogen fluoride (NE ₃ ),
CE ₄ D is chemically activated and its vacuum level is further increased.
A shower with a vacuum atmosphere of 0.1 to 0.001 torr, particularly 0.05 to 0.01 torr, was flowed vertically from the top surface of the substrate in an effort to eliminate side etching.

As a result, when the flat portion of the coating 5 on which no photoresist is formed is completely removed, the first
The coating 8 around the side of the region 3 can leave the layer 6 in a triangular shape around the side as it is. In addition, a counter electrode 7 could be provided on the insulating film 4 by forming a capacitor consisting of the first region 3, the insulating film 4, and the electrode 7. Furthermore, the contact 4 and its lead 9 in the second area were P-type in this embodiment and could be left as the electrode lead 9.
This triangular layer 6 has a width of 0.05 to 1.0μ, typically 0.1 to 0.5μ, and a height of 0.3 to 1.0μ.
2.5μ, typically 0.4~0.8μ. In particular, this width is a function of the thickness of the coating 5 and the etching time intensity of plasma etching, but it can be etched from 0.05 to 0.05 without using advanced technology such as electron beam exposure.
It was possible to provide a very short channel of 1.0μ.

In this FIG. 2C, the triangular layer 6 has a width of
Although the layer is as thin as 0.1 to 1μ, when it is extended over the field insulator, the lead width can be made as wide as 1 to 3μ, depending on the design needs, so that it can be easily connected to other MIS installed on the same board. - It goes without saying that it may be connected to the electrode lead of the FET or electrically connected to another electrode lead 9. Furthermore, a metal having a masking effect may be formed on the upper surfaces of the electrodes 7 and leads 9, and the semiconductor underneath may be of N ⁺ type and P ⁺ type impurities may be diffused into the gate electrode 6 portion.
However, in this case, it is necessary to cause lateral diffusion to extend below the lead extending from this electrode, to form a PN junction under the metal film above it, and to substantially eliminate the PN junction.

Next, as shown in FIG.
and the first region 3 was formed. Then this first
The second regions 13 and 14 could have one end substantially coincident with both ends of the triangular layer 6.

Further, in order to make ohmic contact between the electrode and lead 9 and the second region 13, a further impurity diffusion layer is formed under the electrode to a depth of 50 to 2000A, and further under the first region 3. Moreover, impurities are diffused in the same phase and in a solid phase to form substantially the same shape in the semiconductor substrate, thereby providing the region 14.

As is clear from the above embodiments, the present invention makes it possible to make the triangular layer 6 substantially larger in height (thickness) than in width, and furthermore, the width can be made as small as 0.1 to 1μ. Ta.

Furthermore, since the layer 6 that becomes the gate electrode is thick, it becomes geometrically weak.
In addition, since the unevenness tends to become severe, it is possible to electrically isolate the unevenness with the insulating film 4 and mechanically reinforce it.

As is clear in Figure 2D, the 13th and 14th
and the second region 13 are separated from each other by a triangular layer 6, one of which is used as a source and the other as a drain,
If layer 6 is used as a gate electrode, an extremely short channel type
You can make MIS/FET. In addition, the capacitor 15 is provided in series with the MIS/FET by using the first region forming the source or drain as one electrode and providing the counter electrode 7 above the insulating film 15. It is a feature. With this structure, the capacitor is the first
It was possible to form the film on the upper surface of the area using six photomasks. In addition, the entire upper surface of the gate electrode 6 can be used as a capacitor for the opposing electrode of this capacitor, and its effective area can be made extremely small. Another feature of the present invention is that the first region provided directly for one of the sources or drains of such an ultra-short channel MIS/FET can be used as the lower electrode of the capacitor.

Figure 2E is a vertical sectional view of MIS in Figure 2D.
FETs and capacitors are symbolized by corresponding numbers.

In the embodiment of the present invention, a so-called bulk fractional carrier was used in which the channel region is P type, the first and second regions are N ⁺ type, and the gate electrode is P ⁺ type. However, an enhancement type or depletion type MIS/FET in which the gate electrode is also of the same N ⁺ type as the source and drain may be used.

In addition, enhancement type or depletion type MIS using bulk majority carriers with N type in the channel region, N ⁺ type in the first and second regions, and P ⁺ or N ⁺ type in the gate electrode.
FET i.e. DIS・FET (DIPLETION LAYER
CONTROLED MIS/FET) (patent application 1982-3250 filed on January 14, 1982).

Figure 1 shows the dynamics of 1Tr/cell with one MIS/FET and one capacitor on the board.
This is what forms the memory cells of RAM.
Other areas that are difficult to install due to field insulators
Multiple MIS/FETs can be installed on the same board.
The present invention can be further promoted by making the FET into a so-called LSI or VLSI.

Embodiment 2 Fig. 3 shows two MIS/FETs of the present invention connected in series, (A) to (C) show the manufacturing process of vertical cross-sectional views, and (C) is a top view of ( D) and its equivalent circuit are shown in (E).

In FIG. 3A, for example, a P ^- type (100) silicon semiconductor substrate 1 is selectively oxidized and buried in the substrate to form a field insulator 2 having a thickness of 0.5 to 2 μm. Furthermore, there is a P ⁺ type channel cut 3 on the bottom side.
It was formed by selectively oxidizing 2 and simultaneously diffusing boron.

Next, in order to fabricate a DIS/FET using a buried channel type multiple carrier, a P-type semiconductor layer 30 is formed on the semiconductor substrate without the field insulator 2, and an N-type semiconductor layer 30 is formed on the upper surface near the semiconductor surface. And so. The thickness of each layer was 0.05 to 0.5μ, particularly 0.1 to 0.2μ.

Further, a first region 3 formed of a semiconductor or a conductor is formed in close contact with the surface of the semiconductor substrate, and has a width of 12 to 20 μm and a height of 0.5 μm.
It was formed in the same manner as in Example 1 by selective etching at ~2μ. In particular, it is advantageous to make this first region the same main component as the N ⁺ type substrate because the first region or the diffusion layer 14 below it can also be used as a source or drain.

At the same time, a semiconductor lead 31 and its electrode 34 were provided in a semiconductor region having the area shown in the drawing in close contact with a portion of the semiconductor layer 29.

Next, as in Example 1, an insulating film was formed on the surface and side surfaces of this semiconductor substrate and the first region. This insulating film may be formed of silicon oxide, silicon nitride, aluminum sulfide, or tantalum oxide by a CVD method.

Here, silicon nitride 4 was formed to a thickness of 50 to 200 Å by thermal nitriding or plasma nitriding as in Example 1.

Further, as in Example 1, two triangular layers 6 and 6' are insulated by an insulator 4 at the corners of the first region and the surface of the semiconductor substrate 1, spaced apart from each other. Established at. At this time, using a photomask, the leads 36, 36' extending from the electrodes 6, 6' onto the field insulator 2, and the interlayer insulator therebetween, are formed on the field insulator 2, as shown in FIG. 3D. It is connected to contacts 38, 38' with leads 40, 40'. Further, these 40, 40' may be connected to the wiring lead 37 between the two layers on the first region.

As shown in FIG. 3D, second impurity regions 13, 13 are formed by ion implantation into the semiconductor substrate at approximately the same positions as the other ends of the two electrodes 6, 6' and below them. Formed into a mold. At this time the first
An N layer 14 is also formed under the area of
As MIS・FET 6 , gate electrode 6, source 14,
A drain 13 was formed. Also other MIS・
A gate electrode 6', source 14, and drain 13' of FET 6 ' were formed.

Furthermore, an interlayer insulator 46 is formed using polyimide or PIQ to a thickness of 0.3 to 2 μm on the upper side, and holes for contacts are formed, and the leads 9 and 3 of the second layer are formed.
7 was formed.

As is clear from the plan view E of FIG. 3D, in the embodiment of the present invention constituting one inverter, the common region 3 between the two transistors protrudes from the semiconductor substrate, and is arranged to lean against it. Two gate electrodes are provided.
Because it protrudes like this, it is extremely easy to make contact in this area, and conventionally MIS/FET
After making the contacts, holes for the contacts were precisely drilled in the common area. However, in the present invention, the portion necessary for the contact is provided in advance on the semiconductor as a first region, and this first region further extends as 47 on the field insulator, so that the contact is formed on the field insulator. You can take 37. Therefore, it is possible to substantially approximate the distance between the two electrodes 6, 6 to 0.5 to 3 .mu., and as a result, it has the great feature that the parasitic capacitance of the diffusion layer 14 can be made extremely small.

Furthermore, as is clear from the examples of the present invention,
Once the position of the end of the first region is determined, the end of the diffusion layer 14 is determined to coincide with the end, and one end of each of the gate electrodes 6, 6' is approximately aligned with both ends of the first region. It can be decided accordingly. Further, the second regions 13, 13' are defined by the side periphery of the field insulator buried in the substrate and the other end of the gate electrodes 6, 6', and have self-alignment of the IC. Therefore, in the present invention, an inverter can be fabricated in a substantially 5μ x 7μ area without using an electron beam exposure device, and an ultra-short channel MIS.
It turned out to be excellent for integrating FETs.

In Fig. 3E, the symbol corresponds to D, which has two MIS/FETs connected in series.

In this example, there are two areas in one area.
Installed MIS/FET. However, it goes without saying that there may be three or more resistors, or a capacitor or a vertical resistor may be provided in combination with the first embodiment or the next third embodiment.

This example uses multiple carriers, the gate electrode is P type, and the source, channel, and drain are
It was set as N ⁺ −N−N ⁺ type. However, instead of such an enhancement type, one MIS FET 6 is an enhancement type with a gate electrode 6 of P ⁺ type,
It goes without saying that the gate electrodes 6 of the other MIS/FETs 6 may be of N ⁺ type depletion type.

In such a case, the leads 36 of the gate electrode 6 can be directly connected to the contacts 34 because they are of the same conductivity type.

Example 3 FIG. 4 shows another embodiment of the invention.

That is, a semiconductor substrate 1 having a conductivity type of P type was subjected to plasma nitridation at 800 to 1200° C. to form a nitride film with a thickness of 50 to 1200 Å on the surface. Further, the nitride film was selectively removed with a buffer etchant by photolithography using a first photomask ( ). Furthermore, only the removed area is heated and oxidized at 600 to 1100℃ in steam pressurized to 5 to 15 atmospheres,
A field insulating film 2 was buried and formed to a thickness of 0.3 to 2 μm. Further, the upper part of the field insulator may be removed at the same time as the nitride serving as a mask is removed using a 30 to 50% buffered etchant to make the upper surface of the field insulator average.

Thereafter, in FIG. 3A, a semiconductor layer 3 was formed on the right side in the same manner as in Example 1.

This semiconductor layer is doped with a high concentration of N ⁺ type conductivity impurity in the thickness of 0.05 to 02 μm at the bottom.
In the center or upper part, an intrinsic semiconductor is formed to a thickness of 0.5 to 2 μm, and in order to improve the resistivity of the vertical resistance in this region, oxygen or nitrogen is added to the intrinsic semiconductor or N-type semiconductor by 0.5 to 2 μm. If a semi-insulating film is made by selectively doping with 50 mol% ion implantation, its resistivity will be 5 to 50 times that of an intrinsic semiconductor.
It was possible to reduce the resistance to 10′Ωcm. This semi-insulating film or intrinsic semiconductor could then be chemically made to act as a vertically stacked resistor, making it ideal for high-density integrated circuits.

In FIG. 3B, the upper surfaces of semiconductor substrate 1 and first region 3 were further oxidized or nitrided in the same manner as in Example 11 to form insulating film 4. Of course, this insulating film 4 may be formed by a vapor phase method or a vacuum evaporation method. Furthermore, if the first region 3 is a semiconductor or a conductor of a different type from the substrate, it goes without saying that the first region 3 becomes an oxide or nitride of the semiconductor or a conductor, and forms a different insulating film on the surface of the substrate.

Furthermore, in FIG. 3B, as in Example 1, openings 41 and 42 are formed using a third photomask (), a coating 8 for forming a triangular layer 6 is formed thereon, and side etching is performed. The protected etching was created using a fourth photomask ().

Further, as shown in FIG. 4C, a diffusion layer 14 under the second region 13 and the first region 3 was formed under both ends of the field insulator 2 and the triangular layer 6 so as to be approximately coincident with each other. Then, an MIS-FET could be manufactured in which the regions 13 and 14 or 3 were used as a source and a drain, or the drain or source, and the triangular layer 6 was used as a gate electrode.

This MIS-FET had a structure of N13, -P (channel forming region under the gate electrode) -N14 or 3 using a fractional carrier of the substrate. However, it may also be N13-N (channel forming region under gate electrode 6)-N (14 or 3) using a plurality of carriers of the substrate.

Furthermore, since the leads 5 and 9 were provided on the field insulator 2, it was extremely easy to integrate a plurality of MIS/FETs.

Assuming that FIG. 4E is an electrical equivalent circuit of FIG. 4D, the electrode 6 is P ⁺ type, the vertical resistor 4 is intrinsic or semi-insulating, and the lower semiconductor layer 44 is N If 45 is a + electrode when it is a ⁺ type,
The layer 14 became a resistor to which a voltage was applied in the forward direction to the PIN structure, and the layer 14 was able to generate the output of the inverter with respect to the electrode 6. Furthermore, two flip-flops of FIG. 4E can be combined to form a static RAM.

Further, when mask aligning the first region using a photomask ( ), most of the region can be provided over the upper surface of the field insulator 2 . Therefore, the width of the region where the diffusion layer 14 exists under the first region 3 can be made extremely narrow to 0.3 to 3 μm. Therefore, the parasitic capacitance between the layer 14 and the substrate could be extremely reduced. Furthermore, the gate electrode 6, the source or the drain, and the electrodes and leads 5 and 9 can be formed without requiring any special process, and the interlayer insulator 3 can be formed on the upper surface of the gate electrode 6, source or drain.
Photo etching using the fifth and sixth photomasks can be performed on 6, and the second layer wiring is
It can be carried out in the Y direction, and the number of masks required is 6.
It is characterized by only one type.

In the above three embodiments, the material constituting the first region and the material constituting the triangular layer 6 are
The materials mainly composed of the same material as the substrate doped with impurities having conductivity type of P ⁺ or N ⁺ type, such as silicon, are mainly described.

However, they may be mixtures or compounds of silicon, Mo, and W (Mo ₂ Si, W ₂ Si), and may also be made of multilayer structures of intrinsic, P-type, or N-type semiconductors, or may be made of semiconductors such as silicon. Needless to say, it may have a multilayer structure of Mo, W, platinum, or a compound thereof.

As is clear from the above embodiments, the present invention does not have a conventional structure in which a pair of sources and drains are separated from each other by a gate electrode, but rather the side portion thereof is closer to the first region that can constitute the source or drain. In this way, the gate electrode was mechanically reinforced, and its source or drain was provided on the surface of the semiconductor substrate. In addition, the other source and drain have a structure in which they are provided on the top of the semiconductor approximately in line with one end of the gate. The major feature is that it can be carried out without using .

[Brief explanation of drawings]

Figure 1 shows a vertical sectional view of a conventionally known MIS/FET. 2, 3, and 4 are vertical sectional views showing the manufacturing process and structure of the embodiment of the present invention.

Claims (1)

[Scope of Claims] 1. A first impurity layer provided on the surface of a semiconductor substrate and having an impurity layer made of the same main component material as the semiconductor and acting as one source or drain, and a high resistance layer provided on the layer. an insulating film is provided in the region, at least a side periphery of the region, and on the surface of the semiconductor substrate, and a conductor or a semiconductor is provided on the insulating film and at a corner between the first region and the semiconductor surface. A resistor and an insulated gate field effect semiconductor device are formed by providing a second region which acts as a drain or a source on the semiconductor substrate and is spaced apart from the first region and substantially coincident with the gate electrode under the gate electrode. An MIS type semiconductor device characterized by being directly connected. 2. The MIS type semiconductor device according to claim 1, wherein the high resistance layer is silicon to which oxygen or nitrogen is added. 3. The MIS type semiconductor device according to claim 1, characterized in that an electrode making ohmic contact is provided on the high resistance layer. 4. A first impurity layer made of the same main component material as the semiconductor and acting as a source or drain on the semiconductor substrate, and a high resistance layer on the layer.
a step of selectively forming a region, a step of forming an insulator on the semiconductor substrate and around the outer periphery of the region, a step of selectively forming an opening for an electrode in the insulator, and the opening and the insulating film. a step of forming a semiconductor or conductor film thereon; a step of selectively removing the film and leaving at least a part of the side periphery of the first region to form a gate electrode; and one end of the gate electrode. 2. A method for manufacturing an MIS type semiconductor device, comprising the steps of: providing a second region acting as a drain or a source on the semiconductor substrate in substantially the same manner.