JPH0671081B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

The present invention relates to a semiconductor device, particularly a MIS type (insulating gate type) field effect semiconductor device (hereinafter referred to as MIS • FET).
And to propose a semiconductor device to which the same is applied. According to the present invention, a first region made of a semiconductor of the same or different conductivity type or a conductor is selectively provided on the surface of a semiconductor substrate of a conductivity type, and the step of the corner portion of the convex portion of the first region is used. Then, a layer having a triangular cross section is provided as a gate electrode, the height of which is approximately the same as that of the first region, and the width of which is approximately the same as the film thickness of the coating film formed at the corner.

According to the present invention, the first region serves as a source or drain region, the triangular layer serves as a gate electrode, and the other end of the layer has the same conductivity type as the first region. The MIS-FET is configured by providing the region 2 as the drain or the source, and additionally, the capacitor is provided on the first region at the same time, or the high resistance layer is provided in the part of the first region with the vertical resistance. It is characterized by being provided as.

As shown in FIG. 1, a conventional MIS • FET has a gate insulator (11), a gate electrode (6), and a pair of impurity regions (13) and (14) on a semiconductor substrate (1).
The source and the drain are provided separately from each other, and the leads (9) and (19) thereof are provided on the field insulator (2).

Conventionally, a pair of source and drain regions have always been formed under the both ends of the gate insulator by forming the same plane on the semiconductor substrate. Therefore, in this case, in the IC and the LSI, there is no focus blur during mask alignment due to the planar processing, which is preferable. However, the channel length between the source and drain is determined by the width of the gate electrode, and the smaller the width, the shorter the channel length. However, due to the photo-etching process, the thickness must be smaller than the width, that is, 1/2 to 1/5, and conversely, the sheet resistance of the electrode increases and the channel length is 1 μm or less. It was impossible in reality.

According to the present invention, the width corresponding to the channel length of the layer functioning as the gate electrode can be made extremely small as 0.1 to 1 μm, and the thickness thereof has a thick triangular shape of 0.5 to 1 μm. It has a cross-sectional structure that is longer in the vertical direction than the gate electrodes up to. In addition, since it is long in the longitudinal direction, its strength is not sufficient as it is. Therefore, a first region is provided along this layer to compensate for this strength. In addition, this first region is configured as a part or all of the source or drain in the MIS • FET, and this region is also used as the source or the drain of another lead, resistor, capacitor or other MIS • FET. It is characterized in that it is provided in a convex shape so as to be in intimate contact with the surface of the semiconductor substrate as much as possible.

For this reason, the semiconductor device of the present invention can be achieved by increasing the density for constructing the elements by positively providing it in the height direction rather than increasing the conventional lateral area by scaling. Has an aim. Examples of the present invention will be described below with reference to the drawings.

[0007]

[Example 1] "Example 1" A semiconductor substrate such as a silicon single crystal semiconductor (100) and a P type of 1 to 5 Ωcm was selected.
After that, as shown in FIG. 2A, the field insulator (2) was buried by the first photomask in a thickness of 0.5 to 2 μm by the selective oxidation method. Further, after the surface is sufficiently cleaned, the low pressure vapor phase method (LPC) is applied on the substrate.
By the VD method), a silicon semiconductor doped with a conductivity type impurity such as an N ⁺ type impurity is formed to a thickness of 0.5 to 1.5 μm.

Further, by well-known photolithography, the first peripheral region (3) was selectively removed by carefully removing it so as not to taper the peripheral edge of the peripheral region as much as possible. For example, a fluorine-based gas excited by a microwave of 2.45 GHz was vertically applied to the substrate from above to perform etching. As a result, the surrounding area is 85
I was able to make a clean cut almost vertically to ~ 90 degrees. In this embodiment, the width of this first region is 3 to 200 μm.
A part of it was formed over the field insulator (2) to increase the capacitance of the capacitor (15) and reduce the parasitic capacitance of the region (14) with the substrate (1) as in this embodiment. After that, a silicon nitride film (4) was formed to a thickness of 50 to 200 Å on the first region and on the side surface thereof and further on the surface of the semiconductor substrate (1). This silicon nitride film contains ammonia gas at 900 to 1100 ° C. for 5 to 10
High pressure nitriding method of pressurizing to atmospheric pressure and nitriding, or 0.1 to 1
The pressure was reduced to 0 torr to generate plasma by high-frequency induction energy, and the activated ammonia or its decomposed product nitrogen was heated at 500 to 1100 ° C. to be nitrided. This coating (4) may be another insulating film, for example silicon oxide, a metal oxide, and also this first region is not an impurity-doped silicon, but an intrinsic or intrinsic and P ⁺ or N ⁺ type. It may be a multi-layered film with a semiconductor, or a metal or a metal compound, especially Mo, W or a silicide thereof (Mo ₂ Si, W ₂ Si, etc.).

Next, a known plasma etching method using CF ₄ gas was used. An opening (41) was provided. Then, a conductor or semiconductor coating (5) is formed on the upper surface thereof, for example, under reduced pressure C.
It was formed to a thickness of 0.1 to 1 μm by the VD method. It is very important that the coating (5) is formed so that the thickness of the top surface and the side surface is uniform and the thickness is predetermined. In this way, the peripheral area of the first region (3) has the same thickness direction as that of the film (5) for the peripheral area, but the apparent thickness of the region from the upper side of the substrate is 2 to 5 times. It is possible to make the thickness of this extremely large feature.

For example, 0.10 to 1.5 μ of P-type silicon,
In particular, it was formed to a thickness of 0.5 to 0.7 μ. Further, the concentration of P or N type impurities added to this coating is such that the conductivity of this electrode (6), and the ohmic contact type or PN junction type at the opening (41) between the coating and the semiconductor substrate (1). And the gate insulator (1
1) It is selected by three factors: whether the lower semiconductor substrate is a depression type or an enhancement type.

For example, when the substrate (1) is P type and its interface is to be made more P, the film (5) may be P ⁺ type and silicon may be used. In addition, in order to make an ohmic contact between this film and the second region (3) provided on the semiconductor substrate, in this embodiment, the second region (13) and its lead (9) are N. ^+, And finally 5 to 50 times more P ⁺ impurities necessary to make P ⁺ only the gate electrode part
The impurities were added to cancel each other out. Further, this film (5) is formed without adding impurities, P ⁺ is added only to the gate electrode portion after the step (C), and N ⁺ is formed in the region to be the lead (9) in the subsequent step. May be. Further, if the second region (13) and the gate electrode (6) have the same conductivity type, the film (5) may be N ⁺ type.

This coating (5) is coated with W ₂ Si, Mo ₂ S
When a compound or mixture of silicon, tungsten, molybdenum, etc., such as i, is formed by LPCVD, electron beam evaporation, or reactive sputtering, 0.3 to 1.5 .mu. Good. Thus, FIG. 2 (B)
Got

Then, as shown in FIG. 2C, a photoresist (for example, OMR-83 manufactured by Tokyo Ohka Co., Ltd.) is coated on a region to be left as a part of the film on the upper surface, and photoetching is performed after exposure. It was With respect to this etching, it is important to use an etching method with very little or no side etching and taper etching, instead of the etching method using a conventionally used solution. Specifically, a reactive gas for etching, such as nitrogen fluoride (NH ₃ ), CF ₄ is chemically activated by a microwave using 2.45 GHz, and the degree of vacuum is 0.1 to 0.001 torr, in particular. 0.05
A shower in an atmosphere of a vacuum of about 0.01 torr was made to flow vertically from the upper surface of the substrate to try to eliminate side etching.

As a result, when the flat surface portion of the coating film (5) where the photoresist is not formed is completely removed, the coating film (8) around the first region (3) is triangular as it is. The layer (6) can be left in shape. In addition, a counter electrode (7) is formed on the insulating film (4) as a first capacitor.
Region (3), the insulating film (4) and the electrode (7). Further, the contact (4) and its lead (9) in the portion to be the second region could be left as the electrode lead (9) in the P type in this embodiment. This triangular layer (6) has a width of 0.05-
1.0μ, typically 0.1-0.5μ, and its height is also 0.3-2.5μ, typically 0.4-0.8
I have μ. In particular, this width is a function of the film thickness of the coating film (5) and the etching time intensity by plasma etching, but without using a high technology such as electron beam exposure, a very short channel of 0.05 to 1.0 μ can be obtained. Could be provided.

In FIG. 2C, the triangular layer (6) has a width of. Although the thickness is 1 to 1 μ, when the layer is extended on the field insulator according to the design need, the lead width is set to be 1 to 3 μ wide and other layers provided on the same substrate. It goes without saying that it may be connected to the electrode lead of the MIS • FET or may be electrically connected to another electrode lead (9). Further, even if a metal having a masking action is formed on the upper surfaces of the electrode (7) and the lead (9) and the semiconductor thereunder is N ⁺ type, P ⁺ type impurities are diffused into the gate electrode (6). Good. However, in this case, it is necessary to laterally diffuse to below the lead extending from this electrode so that the PN junction is formed below the metal film on the upper side of the electrode to substantially eliminate the PN junction.

Next, as shown in FIG. 2D, a second region (13), a triangular layer (6), and
The electrodes, leads (9) and the first region (3) were formed. Then, the first and second regions (13) (14)
Was able to substantially match its ends under the ends of the triangular layer (6). Further, in order to bring the electrode, the lead (9) and the second region (13) into ohmic contact with each other, a diffusion layer of impurities is formed under the electrode to a depth of 50 to 2000Å, and the first region is further formed. Under the region (3), impurities are solid-phase-diffused to form regions (14) having substantially the same shape on the semiconductor substrate.

As is clear from the above examples, in the present invention, the triangular layer (6) has a height (thickness) substantially larger than its width and a width of 0.1 to 1 μm. Made it possible to Furthermore, since the thickness of the layer (6) to be the gate electrode is large, the strength becomes weak geometrically and the unevenness is apt to become severe. Therefore, it is electrically isolated by the insulating film (4). It is characterized by being able to reinforce mechanically.

As is apparent from FIG. 2D, the first
(3) (14) and the second region (13) are separated from each other by a triangular layer (6), one of which is a source, the other is a drain, and the layer (6) is a gate electrode. MIS ・ FET can be made. In addition, the first region constituting the source or drain is used as one electrode, and the insulating film (15) is further provided on the upper side thereof as the counter electrode (7).
It is a feature of the present invention that the capacitor (15) is provided in series with this MIS • FET by providing the above.
With such a structure, the capacitor could be formed on the upper surface of the first region and formed with six photomasks. In addition, the counter electrode of this capacitor can use the entire upper surface of the gate electrode (6) as a capacitor,
The effective area could be made extremely small. Another feature of the present invention is that one of the sources or drains of the ultra-short channel MIS • FETs can be left as it is as the first region provided in series with the lower electrode of the capacitor. FIG. 2E shows the MIS • FET and the capacitor in the vertical cross-sectional view of FIG.

In the embodiment of the present invention, a so-called bulk minority carrier having a P type channel region, N ⁺ type first and second regions and a P ⁺ type gate electrode was used as the conductivity type. However, the gate electrode may be an enhancement type or depletion type MIS • FET in which the source and drain are the same N ⁺ type. In the channel area, N
Type, N ⁺ type in the first and second regions, P ⁺ gate electrode
Or an enhancement type or depletion type M using bulk majority carriers of N ⁺ type
IS-FET, DIS-FET (DIPLETION
LAYER CONTROL MIS ・ FET)
(Japanese Patent Application No. 55-3250, filed on January 14, 1980)
May be

FIG. 1 shows a memory cell of a 1Tr / cell dynamic RAM formed on a substrate by one MIS.FET and one capacitor, but another MIS.FET is formed in another portion separated by a field insulator.
It is possible to further promote the present invention by providing a substrate on the same substrate to form a so-called LSI or VLSI for making a plurality of MIS • FETs.

Example 2 FIG. 3 shows two MIs of the present invention.
The S-FETs are connected in series, and (A) to (C) show the manufacturing process of the longitudinal sectional view, the plan view of (C) is shown in (D), and its equivalent circuit is shown in (E). ing. Figure 3
In (A), for example, a P-type (100) silicon semiconductor substrate (1) was selectively oxidized and embedded in the substrate to form a field insulator (2) with a thickness of 0.5 to 2 μm. Further, a P ⁺ -type channel cut (32) was selectively oxidized on the lower side of the channel, and at the same time, boron was diffused and formed.

Next, a P-type semiconductor layer (30) is formed on the upper surface of the semiconductor substrate on which the field insulator (2) is not provided in order to manufacture a DIS • FET using a buried channel type majority carrier. The vicinity of the semiconductor surface was N type (29). 0.05 to 0.5 μ, respectively, especially 0.1.
The thickness is set to 1 to 0.2 μ.

Further, in close contact with the surface of the semiconductor substrate, the first region (3) and the width of 12 to 20 .mu.
It was formed in the same manner as in Example 1 by selective etching to a height of 0.5 to 2 μm. In particular, if this first region has the same main component as that of the N ⁺ type substrate, the diffusion layer (1
4) can be used as a source or a drain as it is, which is convenient.

At this time, at the same time, a semiconductor lead (31) and its electrode (34) were partially provided in close contact with the semiconductor layer (29) in the semiconductor region having the area shown in the drawing. Next, similarly to Example 1, an insulating film was formed on the surface and the side surface of this semiconductor substrate and the first region. This insulating film may be formed of silicon oxide, silicon nitride, aluminum oxide, or tantalum oxide by the CVD method. Here, the silicon nitride (4) is heated to 50 to 50 by the thermal nitriding or plasma nitriding method as in the first embodiment.
It was formed to a thickness of 200Å. Further, as in the first embodiment, two triangular layers (6) and (6 ') are formed on the periphery of the first region and at the corners of the surface of the semiconductor substrate (1) with an insulator ( It was provided with a structure insulated by 4). At this time, using a photomask, this electrode (6)
As shown in FIG. 3 (D), the leads (36) (3) extending from (6 ') and on the field insulator (2).
6 ') and the inter-layer insulation therewith, and contacts (38) (38') with the leads (40) (40 ') on the upper side thereof.
) Is linked to. Further, these (40) and (40 ') may be connected to the wiring lead (37) between the two layers on the first region.

As shown in FIG. 3D, a second impurity region () is formed in the semiconductor substrate below the electrodes, which substantially coincide with the other ends of the two electrodes (6) and (6 '). 13)
(13 ′) was formed into an N ⁺ type by the ion implantation method. At this time, the N ⁺ layer (14) is also formed under the first region, and the gate electrode (6 ′) is formed as one MIS • FET (6 ) .
A source (14) and a drain (13 ') were formed. Further, an interlayer insulator (46) having a thickness of 0.3 to 2 μm was formed on the upper side by using polyimide or PIQ, and a contact hole was formed to form a second layer lead (9) (37).

As is apparent from the plan view (E) of FIG. 3D, in the embodiment of the present invention which constitutes one inverter, the common region (3) between the two transistors is formed.
Are projected from the semiconductor substrate, and two gate electrodes are provided so as to lean on them. Since the protrusions are formed in this manner, it is extremely easy to make contact in this region, and conventionally, after the MIS • FET was formed, a contact hole was precisely drilled in the common region. However, according to the present invention, since a portion necessary for contact is provided in advance as a first region on the semiconductor, and this first region extends as (47) on the field insulator,
A contact (37) can be made on this field insulator. Therefore, the two electrodes (6) and (6 ′) can be brought close to each other to 0.5 to 3 μ, and as a result, the parasitic capacitance of the diffusion layer (14) can be made extremely small. .

Further, as is apparent from the embodiment of the present invention, when the position of the end of the first region is determined, the end of the diffusion layer (14) is determined so as to coincide with the end, and the gate electrode (6) is also determined. One end of each of (6 ′) is determined so as to substantially coincide with both ends of the first region. Furthermore, the second area (1
3) and (13 ′) are determined by the side periphery of the field insulator embedded in the substrate and the other ends of the gate electrodes (6) and (6 ′) and have IC self-alignment. Therefore, in the present invention, the inverter can be formed in a region of substantially 5 μ × 7 μ without using the electron beam exposure apparatus, which is excellent in the integration of the extremely short channel MIS • FET. There was found. Figure 3 (E) shows two MIS
Symbols correspond to those in which FETs are connected in series (D).

In this embodiment, two MIS • FETs are provided in one area. However, it is needless to say that the number may be three or more, or the capacitor or the vertical resistance may be provided by combining with the first embodiment or the next third embodiment. In this embodiment, majority carriers are used, and the gate electrode is P type, and the source, channel, and drain are N ⁺ -NN-N ⁺ type. However, instead of such an enhancement type, one MIS • FET (6) has a gate electrode (6) of P ⁺ type enhancement type, and the other MIS • FET (6) has a gate electrode (6) of N type. It goes without saying that a ⁺ type depletion type may be used.
In this case, the lead (36) of the gate electrode (6) can be directly connected to the contact (34) because it has the same conductivity type.

[Embodiment 3] FIG. 4 shows another embodiment of the present invention. That is, a semiconductor substrate (1) having a P-type conductivity type
On the other hand, plasma nitriding was applied to the substrate at 800 to 1200 ° C. to form a nitride film having a thickness of 50 to 1200Å on the surface. Further, the nitride film was selectively removed with a buffer etchant by the photolithography technique using the first photomask. Further, only the removed region is 600-11 in water vapor pressurized to 5-15 atm.
It was heated and oxidized at 00 ° C., and the field insulating film (2) was embedded and formed in a thickness of 0.3 to 2 μ. In addition, in order to make the upper surface of this field insulator upper part average, 30 to 5
The nitride that serves as the mask may be chemically removed with 0% buffer etchant at the same time.

Thereafter, in FIG. 3A, a semiconductor layer (3) was formed on the right side of the same as in Example 1. The semiconductor layer has a thickness of 0.05 to 0.2 μ and a high concentration of N
Impurity that becomes ⁺ type conductivity type is doped, and an intrinsic semiconductor is formed in a thickness of 0.5 to 2 μm in the central portion or the upper portion,
Oxygen or nitrogen is added to an intrinsic semiconductor or an N-type semiconductor in an amount of 0.5 to improve the resistivity of the vertical resistance in this region.
.About.50 mol% by ion implantation, the resistivity of the semi-insulating film is 5 to 50% of that of an intrinsic semiconductor.
It could be doubled up to 10 ⁹ Ωcm. Then, this semi-insulating film or the intrinsic semiconductor can be chemically acted as a resistor laminated in the vertical direction, and was most suitable as an integrated circuit of high density.

In FIG. 3B, the upper surfaces of the semiconductor substrate (1) and the first region (3) were further oxidized or nitrided in the same manner as in Example 1 to form an insulating film (4). Of course, this insulating film (4) may be formed by a vapor phase method or a vacuum vapor deposition method. Needless to say, when the first region (3) is a semiconductor or conductor different from that of the substrate, it becomes an oxide or nitride of the same and forms a different insulating film on the substrate surface.

Further, in FIG. 3B, the openings (41) and (42) are formed by using the third photomask as in the first embodiment, and the triangular layer (6) is formed thereon. A film (8) was formed to prevent side etching, and etching was performed using a fourth photomask. Further, as shown in FIG. 4C, the lower sides of the second region (13) and the first region (3) are substantially aligned with both ends of the field insulator (2) and the triangular layer (6). Diffusion layer (1
4) was formed. Then, it was possible to fabricate a MIS • FET in which the respective regions (13) and (14) or (3) were used as a source and a drain or a drain or a source and the triangular layer (6) was used as a gate electrode.

This MIS • FET had the concept of N ⁺ (13) -P (channel forming region under the gate electrode) -N ⁺ (14) or (3) using minority carriers of the substrate.
But also N ⁺ (13) − using the majority carrier of the substrate
N (channel forming region under gate electrode (6)) -N
^It may be ⁺ ((14) or (3)). Further, since the leads (5) and (9) are provided on the field insulator (2), it was extremely easy to integrate a plurality of MIS • FETs.

Assuming that FIG. 4 (E) is an electrical equivalent circuit of FIG. 4 (D), the electrode (6) is P ⁺ type and the vertical resistor (4) is intrinsic or semi-insulating. Further, when the lower semiconductor layer (44) is an N ⁺ type and (45) is used as a + electrode, it becomes a resistor in which a voltage is applied in a forward direction to the PIN structure, and the layer (14) is provided to the electrode (6). Could make the output of the inverter. Further, FIG. 4E can be combined with two flip-flops to form a static RAM.

When mask-aligning the first region with a photomask, most of the region can be provided over the upper surface of the field insulator (2). Therefore, substantially the width of the region where the diffusion layer (14) exists below the first region (3) is. The width can be extremely narrow, 3 to 3 μ.
Therefore, the parasitic capacitance between the layer (14) and the substrate could be extremely reduced. Further, the gate electrode (6) and the source or drain can be formed by electrodes and leads (5) and (9) without requiring a special process, and the upper surface of the gate electrode (6) can be formed on the inter-layer insulator (36) with a fifth layer. The ability to perform photo-etching with the sixth photo mask, 2
It is characterized in that layer wiring can be carried out in the X and Y directions, and that the required number of masks is only six.

In the above three embodiments, the material forming the first region or the material forming the triangular layer (6) is the same as the substrate doped with impurities having the P ⁺ or N ⁺ conductivity type. The material of the main component, for example, silicon is mainly described. However, they may be a mixture of silicon and Mo, W or a compound (Mo ₂ Si, W ₂ Si), and may have an intrinsic P-type or N-type semiconductor in a multi-layer structure, or a semiconductor such as silicon. It goes without saying that a multi-layer structure with Mo, W, platinum or a compound thereof may be provided.

As is apparent from the above embodiments, the present invention does not have the conventional structure having a pair of structures in which the source and the drain are separated from each other by the gate electrode, but the first region which can constitute the source or the drain is provided on the side thereof. The portion has a gate electrode which is mechanically reinforced in such a manner that the source or drain is provided on the surface of the semiconductor substrate. Further, the other source and drain have a structure which is provided on the upper part of the semiconductor so as to substantially coincide with one end of the gate.
-It has a major feature that the FET can be implemented without using a technique such as electron beam exposure.

[Brief description of drawings]

FIG. 1 is a longitudinal sectional view of a conventionally known MIS • FET.

FIG. 2 is a vertical sectional view showing the manufacturing process and structure of the embodiment of the present invention.

FIG. 3 is a vertical cross-sectional view showing the manufacturing process and structure of the embodiment of the present invention.

FIG. 4 is a vertical cross-sectional view showing the manufacturing process and structure of the embodiment of the present invention.

Claims (1)

[Claims] 1. A first region made of a conductor or a semiconductor selectively provided on a surface of a semiconductor substrate to form a protrusion, and a first region on the upper surface of the first region so as to form a capacitor together with the first region. A conductor or semiconductor provided via an insulating film, an insulating film provided on the surface and around the first region, and a corner between the first region and the semiconductor substrate on the insulating film. And a gate electrode made of a conductor or a semiconductor provided in the semiconductor substrate, and a second region that is provided in the semiconductor substrate and is separated from the first region and substantially coincides with one end of the gate electrode and serves as a source or a drain. A semiconductor device comprising: an insulating gate type field effect semiconductor device and a capacitor which are connected in series.