JPH0433141B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for manufacturing a semiconductor device, particularly a MIS type (insulated gate type) field effect semiconductor device (hereinafter referred to as μ channel MIS.FET) having a microchannel type, and a semiconductor device in which a capacitor is connected to the MIS type field effect semiconductor device. There are suggestions.

The present invention selectively provides a convex first region made of a semiconductor or conductor of the same or different conductivity type on the surface of a semiconductor substrate of one conductivity type, and L-shaped corner portions of the first region. Using that step,
A layer having a triangular or vertical square cross section (hereinafter simply referred to as triangular shape) is formed as a gate electrode, the height of which roughly matches the first region, and the width of which roughly matches the coating formed at the corner of the layer. did.

Furthermore, as the next step, the present invention
The region and the impurity region provided in the same shape on the upper part of the substrate in contact with the region are used as the region constituting the source or drain, the triangular layer is used as the gate electrode, and a first electrode is formed under the other end of this layer. A MIS.FET is configured by providing a second region of the same conductivity type as the region as a drain or source,
In addition, a capacitor is provided in the first region or within the first region at the same time.

The structure of a conventional MIS.FET and a capacitor connected in series with it is, as shown in FIG. A drain or source 14 constituting the lower electrode of the capacitor was provided, and its lead 9, a capacitor insulator 15, and a counter electrode 7 were also provided.

In the conventional MIS.FET, a pair of source and drain regions 13 and 14 were always formed on the same plane on a semiconductor substrate under both ends of a gate insulator. Furthermore, this gate electrode 6 was provided not only on the gate insulator 11 but also over the upper surface of the counter electrode 7 of the capacitor. This has self-alignment with one end of the source or drain 13 under one end 16 of the gate electrode and the drain or source 14 under the other end 18 of the gate electrode.
However, the other end 17 of the gate electrode that is actually made
is a polycrystalline silicon film (a process in which a polycrystalline silicon film is used for 7 and 6) which is made larger than 18 to compensate for variations in mask alignment accuracy.

However, in such a case, it is impossible to reduce the channel length to 1 μm or less due to the photo-etching process, and in particular, due to the unevenness in the stepped portion 18, it is difficult to shorten the channel length because pattern breakage may occur. It was possible.

The present invention reversely utilizes this step to create MIS.FET
A gate electrode is provided, and this electrode is formed without extending over the opposing electrode of the capacitor.

In the present invention, the width corresponding to the channel length of the layer functioning as a gate electrode can be made extremely small to 0.1 to 1 μm, and the thickness is 0.5 to 1 μm, which is a thick triangular or vertical square shape. It has a longitudinally longer cross-sectional structure than the gate electrode.

In addition, since it is long in the vertical direction, its strength is not sufficient as it is. To compensate for this strength, a first region is therefore provided along this layer. In addition, the upper part of the semiconductor under this first region is
It is configured as part or all of the source or drain of MIS.FET. A further feature is that an insulator and a conductor (semiconductor) are laminated inside this region, and a capacitor is provided in series with the source or drain.

Therefore, the purpose of the semiconductor device of the present invention is to achieve high density for configuring its elements by proactively providing them in the height direction, instead of reducing the conventional lateral area by scaling. There is.

Examples of the present invention will be described below with reference to the drawings.

Embodiment 1 This embodiment mainly shows an embodiment in which an N-type channel MIS.FET using multiple carriers and a capacitor are formed in series.

Semiconductor substrate, for example silicon single crystal semiconductor 10
0, P type 10 to 500Ωcm was selected. A silicon nitride film with a thickness of 50 to 300 Å was formed on the substrate by a plasma nitriding method in which a reactive gas made by activating ammonia by induced energy was reacted at 800 to 1200°C.
The film having a masking effect against the oxidizing gas may be a multilayer film of silicon oxide, polycrystalline silicon, and silicon nitride.

Thereafter, as shown in FIG. 2A, in order to use a selective oxidation method, the silicon nitride is removed using a first photo mask and the area is made P-type, and then the field insulator 2 is formed to a thickness of 0.5 to 2 μm. It was formed by being buried in

Furthermore, under this silicon nitride film 4, there is a thickness of 50 to 5000 Å.
The layer 20 was formed by doping As to a depth of 1000 Å or less by ion implantation and converting the vicinity of the interface to N.

The silicon nitride film is damaged by this ion implantation, but unlike the silicon oxide film, simply annealing at 700 to 1000°C could not make the interface state sufficiently small to 10 ¹⁰ cm ^-2 or less. For this reason, in the present invention, this substrate is placed in hydrogen, a mixed gas of hydrogen and helium, a mixed gas of hydrogen and nitrogen, or ammonia, and these gases are heated at 100 KHz to
500MHz e.g. 500KHz, 13.56MHz or ~10GHz
For example, the induced energy of 2.45GHz frequency is 200
Add ~2KW and at the same time 800~1200℃ especially 1000~1100
℃ to perform so-called plasma annealing.

This ion implantation damages not only the substrate but also silicon nitride, and since silicon nitride cannot be removed like silicon oxide by mere thermal annealing, inductive energy is applied to forcibly remove the damage. Hydrogenation and nitridation of damaged silicon or nitrogen dangling bonds were performed for 10 to 30 minutes. As a result, we were able to obtain an interface level of 10 ¹⁰ cm ^-2 , the same as before ion implantation.

Remove this silicon nitride film or replace it with another insulating film such as silicon nitride or tantalum oxide with a thickness of 100 to 500 Å.
The gate insulating film 11 and the capacitor dielectric 15 were formed to have a thickness of . Next, after thoroughly cleaning the surface of the insulating film, impurities of one conductivity type, such as N, are added onto the substrate by low pressure vapor phase deposition (LPCVD).
A silicon semiconductor 3 doped with type impurities is
It was formed to a thickness of 0.5 to 2.5 μm.

Furthermore, by known photolithography,
The edge around that side was selectively removed while being careful not to side-etch so that the vertical edge side surface was exposed, and the convex first region 3 was left and formed. For example, a fluorine-based gas (e.g. NF ₃ or CF ₄ ) excited by a 2.45 GHz microwave is vertically applied to the substrate from above at a pressure of 0.001 to 0.01 torr.
I did etching. As a result, we were able to cleanly cut the periphery of the board at an angle of 85 to 90 degrees perpendicular to the substrate surface.

In this embodiment, the width of this first area is 3~
It was set to 200 μm. Part of it is field insulator 2
As in this embodiment, the capacitance of the capacitor 15 is increased, and the parasitic capacitance between the region 5 and the substrate 1 is decreased. After this, a silicon oxide film 19 of 500 to
It was formed to a thickness of 5000 Å and covered.

This silicon oxide film absorbs wet oxygen at 900 to 1100℃ for 50 minutes.
High-pressure oxidation method, which oxidizes by pressurizing to ~10 atmospheres, or
It was formed by reducing the pressure to 0.001 to 1 torr and generating plasma using high-frequency induction energy.

This coating 4 may be another insulating film such as alumina which is a metal oxide, and this first region is also not made of silicon doped with impurities, but may be a multilayer film of an intrinsic or an intrinsic semiconductor and a P or N type semiconductor. It may also be a metal or a metal compound, in particular Mo, W or a silicide thereof (Mo ₂ Si, W ₂ Si).

Next, openings 41 and 42 were formed using a photomask using a known plasma etching method using CF gas.

Next, covering the insulating films 11 and 19, a conductive or semiconductor film 5 with a thickness of 0.1 to 1 μm was formed on the upper surface by, for example, a low pressure CVD method. This coating 5
In this process, it is extremely important to form the upper and side surfaces of the first region 3 constituting the convex portion to be uniform and to a predetermined thickness.

In this way, the thickness direction of the side periphery of the first region 3 is the same as the thickness of the coating 5, but the apparent thickness of that region from above the substrate is 2.
It has become possible to make the thickness up to 5 times.

For example, N-type silicon has a thickness of 0.10 to 1.5 μm, especially 0.3 to 1.5 μm.
It was formed to a thickness of 0.7 μm. The concentration and conductivity type of the impurities added to this film generally depend on the degree of conductivity of this electrode 6, the selectivity of the film to be of an ohmic contact type or a PN junction type at the opening 41 with the semiconductor substrate 1, and It is determined by the selectivity of whether the semiconductor substrate under the gate insulator 11 under this layer 6 is of a depletion type or an enhancement type.

It is an N-channel type MIS.FET, for example, substrate 1
is P-type, and the N-type layer 20 at the interface is converted to P by the build potential of the gate electrode to make it an enhancement type, which is the so-called multi-carrier type. By adding B to a concentration of 10 ¹⁸ to 10 ²¹ cm ^-3 , P
A type of silicon may be used. For this reason, the coating is made N-type for ohmic contact with the N-type second region 13 provided on the semiconductor substrate and its lead 9;
Thereafter, only the gate electrode 6 was formed as a P type.

On the other hand, impurities are added to this film 5 in advance.
An impurity for N type may be added at a concentration of 5 to 100 times that of the lead 9 in a subsequent step.

On the other hand, if the second region 13 and the gate electrode 6 are of the same conductivity type and are of the depletion type, the coating 5 is of the N type, and the openings 41 and 42 are simply made in ohmic contact with the N-type second region 13. That's fine.

When the film 5 is made of a compound or mixture of silicon such as W ₂ Si, Mo ₂ Si, tungsten, or molybdenum, the film is formed to a thickness of 0.3 to 1.5 μm by LPCVD, electron beam evaporation, or reactive sputtering. It is sufficient to form the layer with a thickness of 0.5 to 0.7 μm.

Thus, Figure 2B was obtained.

Next, as shown in FIG. 2C, a photoresist (for example, OMR-83 manufactured by Tokyo Ohka) was coated on the upper surface on the area to be left as part of the film, and after exposure, photoetching was performed.

For this etching, it is important to use an etching method with very little side etching and taper etching or which is not clean, rather than the conventional solution etching method. Specifically, reactive gases for etching, such as nitrogen fluoride (NF ₃ ) and (CF ₄ ), are chemically activated using microwaves using 2.45 GHz, and the degree of vacuum is further reduced to 0.1 to 0.001 torr, especially 0.005 to 0.01. In an effort to completely eliminate side etching, a fluorine shower generated as plasma in a vacuum atmosphere of torr was flowed vertically from the top surface of the substrate.

As a result, when the flat portion of the coating 5 on which no photoresist is formed is completely removed, the first
The coating 8 around the side, which is the corner part of the area 3, could be left as it is as a triangular or angular layer 6 around the side.

In addition, a counter electrode 3 of the capacitor is disposed on the insulating film 15.
It was possible to configure and provide it as Furthermore, the contact 41 and its lead 9 in the second region were N-type in this embodiment and could be left as the electrode lead 9. Furthermore, the gate electrode 6 does not extend over the upper surface of the convex first region 3, and its width is not determined by photolithography, but is determined by the thickness of the side surface of the coating 5 as the channel length. It has the characteristic of being

This triangular layer 6 has a width of 0.05 to 2.0 μm,
It typically has a height of 0.1 to 1.5 μm, and further has a height of 0.3 to 2.5 μm, typically 0.4 to 0.8 μm. In particular, this width is a function of the thickness of the coating 5 and the etching time and intensity when side etching is performed by plasma etching, but it can be 0.05 to 0.05 mm without using advanced techniques such as electron beam exposure.
It was possible to provide an extremely short channel (hereinafter referred to as a microchannel) of 1.0 μm.

In this FIG. 2C, the triangular layer 6 has a width of
Although it is as thin as 0.1 to 1 μm, when the layer is extended as a lead over the field insulator (not over the first region) as required by the design, the lead width can be made to have a low sheet resistance. The width of the MIS is 1 to 10μm, and other MISs are installed on the same board.
It goes without saying that it may be electrically connected to the electrode lead of the FET or to another electrode lead 9. In addition, to create this triangular gate electrode, instead of removing unnecessary materials by etching, oxidation is performed using a method in which oxidation proceeds from above, such as anodic oxidation or selective oxidation, to electrically connect the electrode. is also valid.

Next, as shown in FIG. 2D, a second region 13 serving as a source or drain was formed by ion implantation so that the other end of the second region 13 was approximately coincident with the upper part of the substrate under the triangular layer 6. In addition, this region and the lead 9 were brought into ohmic contact.

Then, the first and second regions 14 and 13 could be formed into a .mu.-channel MIS.FET whose both ends substantially coincided with each other under both ends of the triangular layer 6.

In addition, in order to bring the electrode or lead 9 into ohmic contact with the second region 13 acting as a source or drain, a further impurity diffusion layer is formed under the electrode to a depth of 50 to 2000 Å, and furthermore, the capacitor is Under the dielectric film 15 under the first region 3, which is a counter electrode, there is an impurity layer 14 that constitutes a drain or source by a depletion layer determined by the charge of an N-type layer or a capacitor, and serves as an electrode of the capacitor.
can be provided.

As is clear from the above embodiments, the present invention makes it possible to make the triangular layer 6 substantially larger in height (thickness) than in width, and furthermore, the width can be made as small as 0.1 to 1 μm. , and connect a capacitor in series with it to create a 1Tr/cell dynamic
I was able to obtain RAM memory cells.

Furthermore, since the layer 6 that becomes the gate electrode is thick, it becomes geometrically weak.
In addition, since the unevenness tends to become large, it can be reinforced electrically by isolating it with the insulating film 4 and mechanically by making it lean against the convex first region. It is characterized by

As is clear from FIG. 2D, by the above manufacturing method, the first regions 3, 14 and the second region 13 are separated from each other by a triangular layer 6, and one is used as a source and the other as a drain, An extremely short channel (μ channel) type MIS with layer 6 as the gate electrode.
I was able to make a FET. In addition, the first region 3 constituting the source or drain is used as one counter electrode, and the insulating film 15 is further provided with an electrode 14 below it.
A feature of the present invention is that a 1Tr/cell memory cell is provided by a capacitor 15 in series with the MIS.FET made by configuring.

Furthermore, lead 1 in the direction perpendicular to these leads 9 and 5
When the interlayer insulator 25 was formed from a polyimide-based insulator such as PIQ, the metal on the upper surface of the interlayer insulator 25 could be selectively removed or oxidized using photolithography.

Another feature of the present invention is that the first region in which one source or drain of the μ-channel MIS.FET having a frequency response speed of 1 to 10 GHz is provided in series can be left as it is as the lower electrode of the capacitor. It is a feature of

FIG. 2E shows a memory cell in which the MIS.FET and capacitor in the vertical cross-sectional view of FIG. 2D are symbolized by corresponding numbers.

In the embodiment of the present invention, the conductivity type is that the substrate is P type, the channel region 12 is N type, and the first and second regions 1
This is an sensement type μ-channel MIS.FET using so-called multiple carriers in which 3 and 14 are N-type and the gate electrode 16 is P-type.

However, the gate electrode also has the same N as the source and drain.
It is also possible to use MIS.FET of a depression type multiple carrier type.

Alternatively, it may be an enhancement type or depletion type MIS.FET using a bulk minority carrier with a P type in the channel region, an N type in the first and second regions, and a P or N type gate electrode.

Figure 1 shows a 1Tr/cell dynamic RAM memory cell formed by one MIS.FET and one capacitor on the substrate, but another MIS.FET of the same type is placed in another part separated by a field insulator. The present invention can be further promoted by using a so-called LSI or VLSI, which is provided on a substrate to create a plurality of MIS.FETs.

All of the above embodiments are aimed at producing a 1Tr/cell RAM. However, in all of the processes of the present invention, μ-channel MIS.
can be formed without adding any extra photomask. This made it extremely convenient for creating memory systems or logic systems.

Further, the lower electrode, the upper electrode, and the first region of the capacitor may all be formed of a silicon family made of the same main component as the substrate to improve reliability. Further, in the fourth embodiment, a multilayer lead made of Al or the like may be formed on the upper side with an interlayer insulator interposed therebetween.

In the present invention, a floating gate type nonvolatile memory may be constructed by electrically floating the gate electrode.

In the above embodiments, the material constituting the first region or the material constituting the triangular layer 6 is P
Alternatively, the description is centered on a material having the same main component as the substrate doped with an impurity having an N-type conductivity type, for example, silicon.

However, they may be mixtures or compounds of silicon, Mo, and W (Mo ₂ Si, W ₂ Si), and may also be made of multilayer structures of intrinsic, P-type, or N-type semiconductors, or may be made of semiconductors such as silicon. Needless to say, it may have a multilayer structure of Mo, W, platinum, or a compound thereof.

Furthermore, the semiconductor substrate is made of single crystal silicon. but
It goes without saying that it may be a compound semiconductor such as GaAs or InP, or a polycrystalline, amorphous, or semi-amorphous semiconductor.

As is clear from the above embodiments, the present invention does not have a conventional structure in which a pair of sources and drains are separated from each other by a gate electrode, but the details thereof lean toward the first region that can constitute the source or drain. In this way, the gate electrode was mechanically reinforced, and its source or drain was provided on the semiconductor substrate. In addition, the other source and drain have a structure provided on the upper part of the semiconductor approximately in line with one end of the gate, and their structural features include a frequency response speed of 0.1 to 1 μ and a frequency response speed of 1 to 10 GHz.
Ultra short channel (μ channel) MIS.FET with
The major feature of this method is that it can be carried out without using techniques such as electron beam exposure as an absolute requirement.

[Brief explanation of drawings]

FIG. 1 shows a vertical cross-sectional view of a conventionally known MIS.FET. FIG. 2 is a longitudinal sectional view showing the manufacturing process and structure of an embodiment of the present invention.

Claims (1)

[Claims] 1. A step of forming a first insulating film on one surface of a semiconductor, a step of forming a film having a semiconductor or a conductor on the insulating film, and selectively removing the film. a step of forming a convex first region and providing a corner portion with the first region and the insulating film; a step of forming a second insulator covering the first region; forming a layer made of a conductor or semiconductor covering the first insulator and the second insulator, and selectively etching the layer using an etching method with very little or no side etching and taper etching. By leaving a triangular or vertical angular layer at the corner,
a step of forming a gate electrode; and a step of forming a second region on the semiconductor upper part, which is spaced apart from the first region and substantially coincident with one end of the electrode, and forms a source or a drain on the semiconductor upper part. A method for manufacturing a semiconductor device, comprising: 2. Claim 1 is characterized in that the selective etching is performed by flowing a reactive gas for etching activated by microwaves in an atmosphere of 0.1 to 0.001 torr in a vertical direction from the upper surface of the substrate. A method for manufacturing a semiconductor device.