JPH0524522B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a compensator used within a feedback control loop.

Conventional technology As an example of feedback control, for example,
The rotation speed of the motor is detected by a speed detector,
Motor speed control devices that control the power supplied to the motor based on the detection signal are widely used in video tape recorder capstan motors, cylinder heaters, etc. (for example, the patent application proposed by the present applicant (See No. 142724, 1983). however,
Such a speed control device only performs conventionally used proportional, integral, and differential control, and is unable to sufficiently control rotational speed fluctuations due to load torque fluctuations.

In order to solve these problems, the present applicant proposed a high-performance motor speed control device that is extremely resistant to load torque fluctuations in Japanese Patent Application No. 60-229143 and No. 60-229144. did. In other words, Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-229144 disclose a rotation sensor that generates an AC signal with a period corresponding to the rotation speed of the motor, and a rotation sensor that generates an AC signal with a period corresponding to the rotation speed of the motor. A speed detection means performs the detection, and calculations and calculations are performed based on the detection signal of the speed detection means.
A speed control system is constituted by a compensating means for storing and generating a control signal, and a power amplifying means (driving means) for supplying electric power to the motor according to the control signal of the compensating means. Furthermore, a rotation error detection means for obtaining a rotation error in response to a detection signal of the speed detection means, a memory means for storing NxL (plural) memory value groups M[0] to M[NxL−1], and a memory. A composite value calculation means (memory output value creation means) that essentially calculates a composite value that is compositely calculated using Nx memory value groups separated by L intervals of the means, and a composite value and rotation of the composite value calculation means. update storage means for substantially sequentially updating and storing memory values in the memory means with update values corresponding to values obtained by calculating and combining the rotational errors of the error detection means; and a composite value of the composite value calculation means and rotational error detection means. A high-performance motor speed control device is realized by using a compensating means having a control signal generating means that generates a control signal by calculating and synthesizing the number of errors.

Problems to be solved by the invention However, Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60
−229144, it is essential to use a large number of digital memories, typically 16 bits ×
A memory of about 1000 words = 16 kbits is required. Although the price of IC elements for memory is rapidly decreasing due to improvements in semiconductor manufacturing technology in recent years,
Using 16kbits of memory is undesirable, as it increases the cost significantly.

In addition, the operation of the compensation means including the composite value calculation means (memory output value creation means) and the update storage means requires a considerable amount of calculation, and in order to complete the predetermined calculation within the detection period of the speed detector, it is necessary to It was necessary to perform high-speed calculations using expensive high-speed multipliers. That is, there are severe restrictions regarding the configuration and operating speed of the hardware that implements the compensation means.

Taking these points into consideration, the present invention considers a compensator for a control device that uses a large amount of memory as shown in the example above, and significantly reduces the required memory without deteriorating control performance. And,
It is an object of the present invention to provide a compensator in which constraints on calculation time are relaxed.

Means for Solving the Problems In order to achieve the above object, the compensator of the present invention includes error detection means for obtaining digital errors at every predetermined timing or approximately every predetermined timing, and at least Nx·L (herein, Nx is an integer of 1 or more; L is an integer of 4 or more; , updating storage means for updating and storing the Nx·L memory values in order by an updated value obtained by calculating and combining the digital error of the error detection means and the memory output of the memory output value creation means; and Nx is 1.
If , use at least one memory value,
When Nx is 2 or more, the memory output value generates the memory output value in synchronization with the update timing using at least one set of Nx memory value groups whose update intervals are L times or more apart from the update timing. generating means; control signal generating means for generating a control signal by calculating and combining the digital error of the error detecting means and the memory output value of the memory output value generating means at each predetermined timing; and at least the memory output according to a program. The control signal generating means generates a new control signal each time the error detecting means obtains a new digital error, and the error detecting means generates a new control signal. Every time a new digital error is obtained Q times, the memory output value creation means and the update storage means update one memory value, and the memory output value creation means and the update storage means update one memory value. The update operation is divided into a plurality of partial operations, and each partial operation is executed by the calculation means at different timings of the error detection means.

Effects In the present invention, by adopting the above configuration, a high-performance compensator is realized with a small number of memories (1/Q). Further, the update operation of one memory value by the memory update means (memory output value creation means and update storage means) is divided into a plurality of partial operations, and each partial operation is performed at different timings of the error detection means. This greatly reduces the amount of calculation required within one timing of the error detection means. As a result, it has become possible to realize the compensator of the present invention even when using a calculation means with a slow calculation speed. Furthermore, in a motor speed control device using the compensator of the present invention, as shown in Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-229144, the influence of specific frequency fluctuations in load torque can be avoided. It can be significantly reduced. That is, by using the compensator of the present invention, a high-performance control device can be constructed economically.

Embodiment A compensator according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing an example of a motor speed control device using the compensator of the present invention. In FIG. 2, a DC motor 1 directly drives a rotation sensor 2 and a load 10 to rotate. The rotation sensor 2 rotates Zq times per rotation as the motor 1 rotates (Zq is an integer of 2 or more, and in a capstan motor of a video tape recorder, usually
generates an alternating current signal a of Zq=357). The alternating current signal a of the rotation sensor 2 is input to the speed detector 3, and a digital signal b corresponding to the period of the alternating current signal a is obtained.

A specific example of the configuration of the speed detector 3 is shown in FIG. The AC signal a is waveform-shaped by a waveform shaping circuit 31 to obtain a shaped signal g. The shaping signal g is input to an AND circuit 33 and a flip-flop 35. The clock pulse p of the oscillation circuit 32 and the overflow output signal w of the counter 34 are also input to the input side of the AND circuit 33. The oscillation circuit 32 is composed of a crystal oscillator, a frequency divider, etc., and generates a clock pulse p (approximately 500 kHz) which has a considerably higher frequency than the frequency of the shaped signal g. The counter 34 is a 12-bit up counter that counts up its contents every time the output pulse h of the AND circuit 33 arrives. Further, the overflow output signal w is "H" when the count content of the counter 34 is less than a predetermined value, and when the count content of the counter 34 is equal to or greater than the predetermined value, w changes to "L" (here, "H" represents a high potential state, and "L" represents a low potential state). The data input type flip-flop 35 is
The falling edge of the shaping signal g is used as a trigger signal to capture "H" input to the data input terminal, and the output Q is set to "H"(q="H"). Furthermore, when the reset signal r from the compensator 4 becomes "H", the internal states of the counter 34 and flip-flop 35 are reset (b="
LLLLLLLLLLLL”, w = “H”, q = “L”).

Next, the operation of the speed detector 3 shown in FIG. 3 will be explained. Assume that the counter 34 and flip-flop 35 have been reset by the reset signal r. Output signal g of waveform shaping circuit 31
changes from “L” to “H”, AND circuit 33
The clock pulse p of the oscillation circuit 32 is outputted as the output signal h. The counter 34 counts the output signal h and changes its internal state. When the output signal g of the waveform shaping circuit 31 changes from "H" to "L", the output signal h of the AND circuit 33 becomes "L", and the counter 34 saves its internal state. Further, the flip-flop 35 takes in data "H" at the falling edge of the signal g, and changes its output signal q from "L" to "H". The digital signal b of the counter 34 is a value proportional to the (half) cycle length of the alternating current signal a of the rotation sensor 2, and is inversely proportional to the rotation speed of the motor 1. A compensator 4, which will be described later, looks at the output signal q of the flip-flop 35, and when q becomes "H", inputs the digital signal b of the counter 34, and then sets the reset signal r to "H" for a predetermined short period of time. Then, the counter 34 and flip-flop 35 are reset to their initial states in preparation for the next speed detection operation. Note that when the rotational speed of the motor 1 is too slow, the period of the output signal g of the waveform shaping circuit 31 is long, so the internal state of the counter 34 exceeds a predetermined value, and the overflow output signal w changes from "H" to "L". Instead, the output signal h of the AND circuit 33 becomes "L", and the counter 34 may hold a predetermined large value.

The second compensator 4 includes a compensator 5, a memory 6 and a D/
It is composed of an A converter 7, and calculates and processes the digital signal b of the speed detector 3 using a built-in program, which will be described later, and outputs a control signal c. Compensator 4
The control signal c is input to the power amplifier 8 (drive section), and the power amplified drive signal d (current proportional to the control signal c) is supplied to the motor 1. Therefore,
A speed control system is constituted by the motor 1, the rotation sensor 2, the speed detector 3, the compensator 4, and the power amplifier 8 (drive section), and the rotation speed of the motor 1 is controlled to a predetermined value.

The memory 6 of the compensator 4 of the present invention is divided into a ROM area (ROM: read-only memory) in which predetermined programs and constants are stored, and a RAM area (RAM: random access memory) in which necessary values are stored. . The arithmetic unit 5 performs predetermined operations and calculations according to a program in the ROM area. FIG. 1 shows a specific example of the program. Next, the operation will be explained in detail.

(1) <Error Detection Unit 1A> First, the arithmetic unit 5 inputs the output signal q of the flip-flop 35 of the speed detector 3, and waits for the signal q to become "H". That is, the speed detector 3 detects the (half) period of the AC signal a,
The output of a new digital signal b is monitored. When q becomes "H", the digital signal b of the speed detector 3 is read and the digital signal b
At the same time, the counter 34 and flip-flop 35 of the speed detector 3 are reset by setting the reset signal r to "H" for a predetermined period of time. Predetermined reference value S
Subtract the speed detection value S from ref, multiply that value by R (here, R is a predetermined positive constant), and
Calculate the current rotation error E of . [E=
R.(Sref-S)]. That is, a new digital error E is obtained at every predetermined timing (every time the speed detector 3 outputs a new digital signal b) or approximately every predetermined timing.

(2) <Control signal generation section 1B> The memory output value Vo from the memory output value generation section 1E, which will be described later, and the current rotational error E of the error detection section 1A are divided into a predetermined ratio D:1 (here, D is 0<
The control signal value Y is calculated by performing calculation and synthesis using a constant D≦1, preferably D=1 (Y=E
+D・Vo). The control signal value Y is output to the D/A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y.

(3) <First counting part IC> Q (here, Q is an integer of 2 or more) modulo
, the first count variable I1 is counted up each time a new speed detection value S is obtained. In other words, I1=I1+1 (I1+1 becomes new I1)
After setting I1 to 0, if I1=Q, reset I1 to 0. If such an operation is performed, I1 will be an integer between 0 and Q-1. Note that the initial value of I1 is 0. If I1 is 0, operations (4) and (5) are executed, if I1 is 1, operation (6) is executed, and if I1 is not 0 or 1, the operation returns to (1).

(4) <Second count part ID> Nx・L (here, Nx is an integer, L is an integer of 4 or more. In particular, an integer of Nx2 or more, L is (Zq/Q)
Since it is preferable that the value be an integer multiple of 2 or more, such a case will be described below. )
With mod (mod), the second count variable I2 is counted up every time the first count variable I1 becomes 0 (every time Q new speed detection values S are obtained). In other words, after setting I2=I2+1,
If I2NxL, reset I2 to 0. If such an operation is performed, I2 will be an integer between 0 and NxL-1. Note that the initial value of I2 is NxL−
Set to 1.

(5) <Memory output value creation unit 1E> Set the integer J equal to I2 (J=I2), and create a group of Nx memory values M[J-nL (mod NxL) in the RAM area of the memory 6, spaced apart by L intervals. ] (n=1,...,
Nx) to create the memory output value Vo using the following formula.

Vo= _Nx 〓 ^n-1 Wn・M [J-nL (mod NxL)] ...(1) Here, the value of the ratio W is 0<Wn<2/Nx (n=1,...,Nx) ... ...(2), and is further standardized as _Nx 〓 ^n-1 Wn=1 ...(3). Specifically, when Nx≧2, Wn=1/Nx (n=1,...,Nx)...(4), then equation (1) becomes the memory value group MP[J-nL(mod
NxL)] (n=1, . . . , Nx) are simply added and combined and then divided by Nx (an integer), making the calculation extremely simple. After that, the operation returns to (1).

(6) <Update storage unit IF> Memory output value by memory output value creation unit 1E
An updated value is calculated by calculating Vo and the rotational error E of the error detection unit 1A at a ratio of 1:1, and the memory value M[I2] in the ram area corresponding to the second count fluctuation I2 is updated. (M[I2]=E+Vo), stored and saved until the next update. After that, the operation returns to (1).

In the motor speed control device using the compensator of the present embodiment, as in the prior patent, the variation is extremely strong against a specific frequency component of the load torque fluctuation caused by the load 10 shown in FIG. Furthermore, as shown in the compensator of this embodiment, the control signal generation section 1B generates a new control signal every time the error detection section 1A obtains a new error signal, and the error detection section 1A generates a new error signal. If the update storage unit 1F updates one memory value every time Q values are acquired, the number of memories required for the memory unit is substantially reduced to 1/Q. Even if the number of memories is reduced in this way, in the control device, the above-mentioned effect of being extremely strong against a specific frequency component of load torque fluctuation (effect of not causing rotational speed fluctuation) is maintained. This can be explained as follows. It has been found that by increasing the value of L, the frequency components improved by the operations of the memory 6, the memory output value creation section 1E, and the update storage section 1F can be made considerably lower than the detection frequency of the error detection section 1A. Therefore,
Error detection unit 1A used in update storage unit 1F
Even if the frequency of the error signal is reduced to 1/Q, it is possible to prevent the above-mentioned improvement effect from being adversely affected.

In addition, a memory output value creation unit 1E and an update storage unit 1
A memory update unit is configured by F, and the update operation of one memory value (memory update operation by the memory output value creation unit 1E and update storage unit 1F) is performed at the timing with respect to the digital error detection operation of the signal difference detection unit 1A. Since the values are shifted, the amount of calculation required within one detection period of the error detection section 1A is reduced. Furthermore, the operation of the memory output value creation section 1E is controlled by I1.
Since it is performed when = 0, the control signal generation unit 1B
The memory output value Vo used in is changed without delay.

In addition, in the motor speed control device using the compensator of the present invention, if L=(Zq/Q)・k (here, k is an integer of 2 or more), the motor 1
This has the effect of significantly suppressing rotational speed fluctuations due to load torque fluctuations with a period k times one rotation period. Such an effect is highly desirable in the case of video tape recorder capstan motors. This will be explained. The load on the capstan motor is magnetic tape or pinch rollers, so
The load fluctuations generated by the load 10 include not only components that are periodic to the rotation of the motor 1 (periodic load fluctuations with one revolution of the motor 1 as the basic cycle), but also load fluctuations at a frequency lower than the rotational frequency of the motor 1. components often occur. Such load fluctuations cause fluctuations in the rotational speed of the capstan motor, causing wow and flutter in the tape speed. By the way, it has been found that such load fluctuations are often periodic fluctuations having a period that is an integral multiple of the period of one revolution of the motor 1. Therefore, due to the above-mentioned effects, it is possible to effectively reduce considerably low-frequency fluctuations in the rotational speed of the motor 1 due to load torque fluctuations. It should be noted that Q is not limited to a divisor of Zq (for example,
If Q=k, Q becomes irrelevant to Zq).

FIG. 4 shows an example of a program for the compensator 4 of the present invention, which takes into consideration the stability of the entire control system. Here, we will explain how to calculate the update value in the update storage section,
The number of memory output values prepared in the memory output value generation section and the way the memory output value generation section uses the memory output values in the control signal generation section are improved. Next, its operation will be explained in detail (the overall configuration of the motor speed control device is the same as that shown in FIG. 2, and the explanation will be omitted).

(11) <Error Detection Unit 4A> First, the arithmetic unit 5 inputs the output signal q of the flip-flop 35 of the speed detector 3, and waits for the signal q to become "H". That is, the speed detector 3 detects the (half) period of the AC signal a,
The output of a new digital signal b is monitored. When q becomes "H", the digital signal b of the speed detector 3 is read and the digital signal b
At the same time, the counter 34 and flip-flop 35 of the speed detector 3 are reset by setting the reset signal r to "H" for a predetermined period of time. Predetermined reference value S
Subtract the speed detection value S from ref, multiply that value by R (here, R is a predetermined positive constant), and
Calculate the current rotation error E of [E=R・
(Sref-S)]. That is, a new digital error E is obtained at every predetermined timing (every time the speed detector 3 outputs a new digital signal b) or approximately every predetermined timing.

(12) <Control signal generation unit 4B> A control signal value is generated by calculating and combining the memory output value Vo by the memory output value generation unit 4E, which will be described later, and the current rotation error E of the error detection unit 4A at a predetermined ratio D:1. Calculate Y (Y=E+D・V0). The control signal value Y is output to the D/A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y.

(13) <First counting unit 4C> With Q as mod, new speed detection value S
The first count variable I1 is counted up each time . Memory output value Vo where I1 is equal to Qa (where Qa is an integer smaller than Q)
is changed to V[Px], which will be described later, and such a changing operation is not performed if I1 is not equal to Qa. As a result, in the range of I1<Qa, Vo=V[Px−1]
(described later), and in the range of I1≧Qa, V0=V
It has become [Px]. Furthermore, if I1 is 0,
The operations (14) and (15) are executed, and if I1 is 0 or 1, the operation (16) is executed, and if I1 is not 0 or 1, the operation returns to (11).

(14) <Second counting unit 4D> With Nx·L as mod, the second count variable is set every time the first count variable I1 becomes 0 (every time Q new speed detection values S are obtained). Count up I2.

(15) <Memory output value creation unit 4E> After sequentially transferring the contents of register variable V[m+1] to V[m] (m=0, 1,..., Px-
1), use NxL as mod to the second count variable I2
Px (here, Px is an integer greater than or equal to 1 and less than or equal to 3, preferably Px = 1) is added to calculate the integer J [J = I2 + Px (mod NxL)]. Memory value group M [J-nL (mod NxL)] (n=
1,...,Nx) and put the latest memory output value calculated by the following formula into V[Px].

V[Px] = _Nx 〓 ^n-1 Wn...M[J-nL (mod NxL)]
...(1) Here, the value of Wn satisfies equations (2), (3), and (4). That is, from V[Px] to V[0]
Obtain a group of Px+1 consecutive memory output values.
At this time, if the integer J in formula (5) when calculating V[Px] is J1, and the integer J in formula (5) when calculating V[0] is J2, then J1=J2+Px. There is a relationship. Next, the memory output value Vo used first in the control signal generation unit 4B is set to V[Px-1]
(Vo=V[Px-1]). After that, the operation returns to (11).

(16) <Update storage unit 4F> After sequentially transferring the contents of register variable X[m+1] to X[m] (m=0, 1, 2,...,
2Kd−1), X[2Kd] (here, Kd is an integer, and preferably Kd=3) is the old memory output value V created by the memory output value creation unit 4E.
[0] and the rotation error E of the error detection unit 4A at 1:1.
Input the composite value calculated and synthesized at the ratio of (X
[2Kd]=E+V[0]). That is, 2Kd+1 consecutive addition values (addition values of the memory output value and rotation error) from X[2Kd] to X[0] are obtained.
From the second count variable I2 with NxL as mod
Calculate the integer K by subtracting Kd. [K=I2−Kd
(mod NxL)]. Next, set a predetermined ratio to X[m]
Obtain a new updated value by adding and combining the values multiplied by Cm (m=0, 1,..., 2Kd), and store it as memory M[K] in the RAM area of memory 6 until the next update. That is, M[K] = _2Kd 〓 ^m-0 Cm・X[m] ...(6). Here, the ratio Cm has the following relationship.

Cm=C _2Kd-n (m=0, 1..., Kd)
...(7) _Nx 〓 ^m-1 Cm=1 After that, the operation returns to (11).

Like the compensator of this embodiment, a calculation for taking a weighted average may be inserted into the update storage section 4F, or a memory output value creation section 4E used in the control signal creation section 4F.
There is a predetermined deviation (V[Px] is V It was confirmed that if a control system (more advanced than [0]) is provided, the operation of the entire control system becomes stable.In particular, the
The values of Px and Qa are deeply related to the value of Q, and (QPx − Qa)
I also found out that it is better to set ≧Q/2. This is done in the update storage unit 4F of the same memory output value (for example, the value of V[0]) of the memory output value creation unit 4E.
The timing of use in the control signal generation unit 4B is compared to the timing of use in the error detection unit 4A.
When converted to the number of detections, this means Q/2 or more times faster.

Furthermore, as shown in the compensator of this embodiment, if the operation of the memory output value creation section 4E or the operation of the update storage section 4F includes many transfers and multiplications, the memory output value creation section 4E The update operation of one memory value by the memory update section consisting of the update storage section 4F is divided into a plurality of partial operations, and the corner section operations are calculated and executed at different detection timings of the error detection section 4A.
If it is processed, the amount of computation required by the arithmetic unit 5 within one detection period of the error detection unit 4A will be significantly reduced, and the restriction on the computation speed required by the arithmetic unit 5 will be significantly relaxed.

FIG. 5 shows another example of a program for the compensator 4 of the present invention, which takes into consideration the stability of the entire control system. Here, improvements have been made in the method of calculating memory output values in the memory output value generation section and the number of memory output values to be prepared, as well as the way in which the memory output values of the memory output value generation section are used in the control signal generation section. Next, its operation will be explained in detail (the overall configuration of the motor speed control device is the same as that shown in FIG. 2, and the explanation will be omitted).

(21) <Error Detection Unit 5A> First, the arithmetic unit 5 inputs the output signal q of the flip-flop 35 of the speed detector 3, and waits for the signal q to become "H". That is, the speed detector 3 detects the (half) cycle of the AC signal a,
The output of a new digital signal b is monitored. When q becomes "H", the digital signal b of the speed detector 3 is read and the digital signal b
The counter 34 and flip-flop 35 of the speed detector 3 are reset by setting the reset signal r to "H" for a predetermined period of time. Predetermined reference value S
Subtract the speed detection value S from ref, multiply that value by R (here, R is a predetermined positive constant), and
Calculate the rotation error E at the current point in time. [E=R・
(Sref-S)]. That is, a new digital error E is obtained at every predetermined timing (every time the speed detector 3 outputs a new digital signal b) or approximately every predetermined timing.

(22) <Control signal generation unit 5B> A control signal value is generated by calculating and combining the memory output value Vo from the memory output value generation unit 5E (described later) and the current rotation error E of the error detection unit 5A at a predetermined ratio D:1. Calculate Y (Y=E+D・Vo). The control signal value Y is output to the D/A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y.

(23) <First counting unit 5C> With Q as mod, new speed detection value S
The first count variable I1 is counted up each time . Memory output value Vo where I1 is equal to Qa (where Qa is an integer smaller than Q)
is changed to V[Px], which will be described later, and such a changing operation is not performed if I1 is not equal to Qa. As a result, in the range of I1<Qa, Vo=V[Px−1]
(described later), and in the range of I1≧Qa, V0=V
It has become [Px]. Furthermore, if I1 is 0, execute operations (24) and (25), if I1 is 1, execute operation (26), and if I1 is not 0 or 1, return to operation (21). .

(24) <Second counting unit 5D> With Nx·L as mod, the second count is performed every time the first count variable I1 becomes 0 (every time Q new speed detection values S are obtained). The variable I2 is counted up.

(25) <Memory output value creation unit 5E> After sequentially transferring the contents of register variable X[m+1] to X[m] (m=0, 1, 2, ...,
2kd−1), and NxL as mod, calculate the integer J by adding Px+Kd (Px is an integer greater than or equal to 1 and less than or equal to 3, and Kd is an integer greater than or equal to 1) to the second count variable 12 [J=12+Px+Qx( modNxL)].
A group of Nx memory values in the RAM area M[J−nL
(mod NxL)] (n=1,...,Nx) and enter the calculated value calculated by the following formula into X[2Kd].

X[2Kd] = _NX 〓 ^n-1 Wn・M[J-nL (modNxL)
...(9) Here, the value of Wn satisfies equations (2), (3), and (4). That is, from X[2Kd] to X[0]
2Kd+1 consecutive calculated values (calculated values obtained from Nx memory values separated by L intervals) are obtained. Next, after sequentially transferring the contents of register variable V[m+1] to V[m] (m=0,
1,...,Px-1), X[m](m=0,1,...,
2Kd) to a predetermined positive ratio Cm (m=0, 1,...,
2Kd) to obtain the latest memory output value and put it in V[Px].

V[Px] = _2Kd 〓 _n-0 Cm・X[m] ...(10) Here, the ratio Cm has the relationship of equations (7) and (8). That is, Px+1 memory output values consecutive from V[Px] to V[0] are obtained. At this time, the integer J in equation (9) when actually calculating V[Px] is set to J1, and the integer J in equation (9) when substantially calculating V[0] is set to J2. Then, J1=J2+
There is a Px relationship. That is, V[Px] and V
There is a gap between [0] corresponding to the integer Px.
Next, the memory output value Vo is set to V[Px-1] (Vo=V[Px-1]). After that, the operation returns to (21).

(26) <Update storage unit 5F> The old memory output value V[0] created by the memory output value creation unit 5E and the rotation error E of the error detection unit 5A are calculated and combined at a ratio of 1:1. Calculate the update value and calculate the memory value M[12] in the RAM area of the memory 6 corresponding to the second count variable 12
is updated (M[12]=E+V[0]) and stored until the next update. After that, the operation returns to (21).

As in the compensator of the present embodiment, a memory output value creating section for use in the control signal creating section 5B includes an operation for taking a weighted average and an operation for preparing a plurality of memory output values in the memory output value creating section 5E. 5E
The first memory output value Vo (V [Px]) and the memory output value creation unit 5E used in the update storage unit 5F.
By providing a predetermined deviation (V[Px] is ahead of V[0]) between the second memory output values V[0], the operation of the entire control system becomes stable. In this case as well, it is better to set (QPx−Qa)≧Q/2.

It should be noted that calculations using the ratios Wn and Cm are not limited to the above formats, as long as they substantially realize the contents of the above program, and it goes without saying that various equivalent formula transformations are possible. stomach. Also, when a new digital rotation error is obtained, the control signal generation section first outputs a new control signal, and then the memory output value generation section generates the memory output value to be used at the next sampling point. If the calculation is performed, the calculation time of the memory output value creation section can be lengthened, and the time delay until the control signal is output can be shortened, making it easier to ensure the stability of the control system. In addition, various modifications can be made without changing the gist of the present invention.

Effects of the Invention The compensator of the present invention is capable of obtaining extremely good control characteristics at a specific frequency while using a small amount of memory. Furthermore, improvements have been made so that the computation speed required for the compensator can be reduced. Therefore, if a control device is constructed using the compensator of the present invention in a feedback loop, a control device having extremely high performance control characteristics can be obtained at low cost. For example, if used in a motor speed control device for a capstan motor of a video tape recorder, a high performance motor speed control device can be constructed economically.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing an example of the built-in program of the compensator of the present invention, FIG. 2 is a block diagram showing the configuration of an example of a motor speed control device using the compensator of the present invention, and FIG. FIG. 2 is a block diagram showing a specific example of the configuration of the speed detector, FIG. 4 is a flowchart showing another example of the built-in program of the compensator of the present invention, and FIG. 5 is a block diagram of the compensator of the present invention. FIG. 7 is a flowchart showing another example of a built-in program. DESCRIPTION OF SYMBOLS 1... Motor, 2... Rotation sensor, 3... Speed detector, 4... Compensator, 5... Arithmetic unit, 6... Memory, 7... D/A converter, 8... Power amplifier,
10...Load, 1A, 4A, 5A...Error detection section, 1B, 4B, 5B...Control signal creation section, 1
C, 4C, 5C...1st count section, 1D, 4
D, 5D...Second count section, 1E, 4E, 5
E...Memory output value creation section, 1F, 4F, 5F...
...Update storage department.

Claims (1)

[Claims] 1. Error detection means that obtains digital errors at every predetermined timing or approximately every predetermined timing, and at least Nx·L (here, Nx is an integer of 1 or more,
a memory means for storing ordered memory values (L is an integer of 4 or more); and a memory means for storing ordered memory values (L is an integer of 4 or more); update storage means for updating and storing memory values in order with updated values obtained by calculating and combining the digital error of the error detection means and the memory output of the memory output value creation means; and when Nx is 1, at least one memory; Using the value Nx
is 2 or more, creating the memory output value in synchronization with the update timing by using at least one set of Nx memory value groups whose update intervals are L times or more apart from the update timing; means for generating a control signal by calculating and combining the digital error of the error detecting means and the memory output value of the memory output value generating means at each predetermined timing, and controlling at least the memory output value according to a program. comprising a calculation means for executing the operation of the creation means and the operation of the update storage means,
Each time the error detection means obtains a new digital error, the control signal creation means creates a new control signal, and each time the error detection means obtains a new digital error Q times, the memory output value creation means and the update storage means One memory value is updated, and one memory value update operation by the memory output value creation means and the update storage means is divided into a plurality of partial operations, and each of the partial operations is processed by the error detection means. The compensator is executed by the calculation means at different timings.