JP2574235B2 - Motor speed control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

TECHNICAL FIELD The present invention relates to a motor speed control device. 2. Description of the Related Art A motor speed control device that detects and controls the rotation speed of a motor with a speed detector is widely used for a capstan motor or a cylinder motor of a video tape recorder (for example, Japanese Patent Application No. 56-1427
No. 24). However, such a speed control device merely performs the proportional / integral / differential control which has been conventionally used, and cannot sufficiently suppress the fluctuation of the rotation speed due to the fluctuation of the load torque. In order to solve such a problem, the present applicant has
Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-229144 have proposed a high-performance motor speed controller which is extremely resistant to load torque fluctuations. That is, Japanese Patent Application No. 60-229143 and Japanese Patent Application
No. 60-229144 discloses a rotation sensor that generates an AC signal having a cycle corresponding to the rotation speed of a motor, a speed detection unit that performs a plurality of detections per rotation of the motor based on the AC signal of the rotation sensor, and a detection signal of the speed detection unit. A speed control system is constituted by compensating means for calculating and storing a control signal based on the calculation and storage, and power amplifying means (driving means) for supplying the motor with power according to the control signal of the compensating means. Further, a rotation error detecting means for obtaining a rotation error in response to a detection signal of the speed detecting means, and NxL (multiple) memory value groups M

[0]
And M [Nx L-1] from the memory means, and a combined value calculating means (memory) for substantially calculating a combined value to be combined and calculated using Nx memory value groups separated by L intervals of the memory means. Output value creation means) and update storage means for updating and storing the memory values of the memory means substantially in order with an update value corresponding to a value obtained by arithmetically combining the combined value of the combined value calculation means and the rotation error of the rotation error detection means. And a compensating means having a control signal creating means for creating a control signal by arithmetically combining the combined value of the combined value calculating means and the rotation error of the rotation error detecting means, thereby providing a high-performance motor speed control device. Has been realized. Problems to be Solved by the Invention However, Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-2291
In No. 44, it is indispensable to use a large number of digital memories, and usually, a memory of about 16 bits × 1000 words = 16 kbits is required. Although the cost of memory IC elements has been rapidly reduced due to the improvement in semiconductor manufacturing technology in recent years, the use of memories of 16 kbits causes a significant increase in cost, which is not preferable. In view of the above, the present invention is designed to greatly reduce the number of required memories in a motor speed control device using many memories as shown in the above example. Means for Solving the Problems In the motor speed control device of the present invention, a rotation sensor that generates an AC signal having a cycle corresponding to the motor rotation speed, and a plurality of rotations per one rotation of the motor by the AC signal of the rotation sensor. Speed detecting means for performing detection, compensating means for calculating and storing a control signal based on the detection signal of the speed detecting means, and driving means for driving the motor in response to the control signal of the compensating means. A compensating means, a rotational error detecting means for obtaining a rotational error in response to a detection signal of the speed detecting means, and Nx updated by an update storing means.
L (where Nx is an integer of 1 or more, L is an integer of 4 or more)
, M [1],..., M [NxL-1], and a first memory value created from the memory value stored in the memory means. A memory output value generating unit for obtaining a memory output value and a second memory value; and the memory unit using an updated value obtained by arithmetically combining a second memory output value of the memory output value generating unit and a rotation error of the rotation error detection unit. M [0], M [1],..., M
The update storage means for updating and storing in the order of [NxL-1], and the first memory output value of the memory output value creation means and the rotation error of the rotation error detection means are arithmetically synthesized to generate the control signal. It comprises a control signal creation means,
Each time the speed detecting means obtains a new detection signal, the control signal generating means is configured to generate a new control signal, and the speed detecting means generates Q new detection signals (where Q is The memory output value creation means and the update storage means are operated so as to update one memory value stored in the memory means each time the control signal creation means is obtained. The first memory output value used in the means is Nx memory values M [J1-nL (mod NxL)] (n = 1,2) of the memory means.
.., Nx) (where J1 is an integer) and is used in the update storage means and the second memory output value is Nx memory values M [J2-nL ( mod
Nx L)] (n = 1,..., Nx) (where J2 is an integer), and the integers J1 and J2 are calculated as J1 = J2 + Px (mod Nx L)
(Where Px is an integer of 1 or more) solves the above problem. Operation In the present invention, by adopting the above configuration, decimal numbers (Q
A high-performance motor speed control device is realized by the number of memories of (1/1). Also in the motor speed control device of the present invention, as shown in Japanese Patent Application Nos. 60-229143 and 60-229144, the influence of a specific frequency fluctuation of the load torque can be greatly reduced. . That is, according to the present invention, a high-performance motor speed control device can be economically constructed. Embodiment 2 FIG. 2 is a block diagram showing an embodiment of the present invention. In FIG. 2, a DC motor 1 directly drives a rotation sensor 2 and a load 10 to rotate. The rotation sensor 2 rotates Zq times per rotation with the rotation of the motor 1 (Zq is an integer of 2 or more, and in a capstan motor of a video tape recorder, Zq = 35 normally).
7) The AC signal a is generated. The AC signal a of the rotation sensor 2 is input to the speed detector 3 to obtain a digital signal b corresponding to the cycle of the AC signal a. FIG. 3 shows a specific configuration example of the speed detector 3. The AC signal a is shaped by the waveform shaping circuit 31 to obtain a shaped signal g. The shaping signal g is input to the AND circuit 33 and the flip-flop 35. The input side of the AND circuit 33 further includes a clock pulse p of the oscillation circuit 32 and a counter.
The overflow output signal w of 34 is also input. The oscillating circuit 32 is composed of a crystal oscillator and a frequency divider, etc.
(About 500 kHz). The counter 34 is a 12-bit up counter that counts up the content of the output pulse h of the AND circuit 33 each time it arrives. The overflow output signal w is "H" when the count of the counter 34 is equal to or less than a predetermined value, and changes to "L" when the count of the counter 34 is equal to or more than the predetermined value (here, "H"). Represents a high potential state, and “L” represents a low potential state). The data input type flip-flop 35 captures “H” input to the data input terminal using the falling edge of the shaping signal g as a trigger signal, and changes the output Q to “H”.
(Q = “H”). When the reset signal r from the compensator 4 becomes “H”, the counter 34 and the flip-flop 35
Is reset (b = “LLLLLLLLLLLL”,
w = “H”, q = “L”). Next, the operation of the speed detector 3 shown in FIG. 3 will be described. Now, it is assumed that the counter 34 and the flip-flop 35 are reset by the reset signal r. When the output signal g of the waveform shaping circuit 31 changes from “L” to “H”, the clock pulse p of the oscillation circuit 32 is output as the output signal h of the AND circuit 33. The counter 34 counts the output signal h and changes its internal state. When the output signal g of the waveform shaping circuit 31 changes from “H” to “L”, the output signal h of the AND circuit 33 changes to “L”, and the counter 34 holds its internal state. The flip-flop 35 captures the data “H” at the falling edge of the signal g, and changes the output signal g from “L” to “H”. The digital signal b of the counter 34 is a value proportional to the (half) cycle length of the AC signal a of the rotation sensor 2 and is inversely proportional to the circuit speed of the motor 1. The compensator 4, which will be described later, sees the output signal q of the flip-flop 35, when q becomes "H", activates the digital signal b of the counter 34, and thereafter changes the reset signal r to "H" for a predetermined short time. Then, the counter 34 and the flip-flop 35 are reset to the initial state to prepare for the next speed detection operation. When the rotation speed of the motor 1 is too slow, the counter of the output signal g of the waveform shaping circuit 31 is long,
The internal state of 34 becomes a predetermined value or more, the overflow output signal w changes from “H” to “L”, the output signal h of the AND circuit 33 changes to “L”, and the counter 34 holds a predetermined large value. Sometimes. The compensator 4 shown in FIG. 2 is composed of an arithmetic unit 5, a memory 6, and a D / A converter 7. The compensator 4 calculates and processes a digital signal b of the speed detector 3 by a built-in program described later and outputs a control signal c. I do. The control signal c of the compensator 4 is input to the power amplifier 8 (driving means), and the power-amplified drive signal d (current proportional to the control signal c) is supplied to the motor 1. Therefore, a speed control system is configured by the motor 1, the rotation sensor 2, the speed detector 3, the compensator 4, and the power amplifier 8 (drive means), and the rotation speed of the motor 1 is controlled to a predetermined value. The memory 6 of the compensator 4 is divided into a ROM area (R0M: read only memory) in which a predetermined program and a constant are stored, and a RAM area (RAM: random access memory) in which necessary values are stored as needed. The arithmetic unit 5 performs a predetermined operation or calculation according to a program in the ROM area. FIG. 1 shows a specific example of the program. Next, the operation will be described in detail. (1) <Rotation error detector 1A> First, the arithmetic unit 5 is a flip-flop 35 of the speed detector 3.
, And waits until the signal q becomes “H”. That is, it monitors that the speed detector 3 detects the (half) period of the AC signal a and outputs a new digital signal b. When q becomes "H", the digital signal b of the speed detector 3 is read and converted to the speed detection value S (digital value) corresponding to the digital signal b, and the reset signal r is set to "H" for a predetermined time to change the speed. Detector 3 counter
Reset 34 and flip-flop 35. Predetermined reference value
The speed detection value S is subtracted from Sref, the value is multiplied by R (here, R is a predetermined positive constant), and the current rotation error E of the motor 1 is calculated [E = R · (Sref−S )]. (2) <Control signal creation unit 1B> Memory output value V0 by memory output value creation unit 1E described later
And the current rotation error E are calculated and synthesized at a predetermined ratio D: 1 (where D is a constant satisfying 0 <D ≦ 1 and preferably D = 1) to calculate a control signal value Y (Y = E + D.V0). The control signal value Y is output to the D / A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y. (3) <First count section 1C> With Q (where Q is an integer of 2 or more) mod (modulus), the first count conversion is performed each time a new speed detection value S is obtained.
Count up I1. That is, I1 = I1 + 1
(I1 + 1 is newly set to I1), then if I1 = Q
Reset I1 to 0. If you do such an operation,
I1 is an integer between 0 and Q-1. Note that the initial value of I1 is 0. If I1 is 0, the operation after (4) is executed,
If I1 is not 0, the operation returns to the operation of (1). (4) <Second counting unit 1D> Nx · L (Nx is an integer, L is an integer of 4 or more. Here, Nx is an integer of 2 or more, and L is 2 or more of (Zq / Q). Since such an integer is preferably an integral multiple, such a case will be described hereinafter). When the first count variable I1 becomes 0 (Q new speed detection values S are obtained). Each time) the second count variable I2 is counted up. That is, after setting I2 = I2 + 1, I2 = NxL
If so, reset I2 to zero. With such an operation, I2 is an integer between 0 and NxL-1. Note that I2
Is NxL-1. (5) <Memory output value creation unit 1E> The integer J is set equal to I2 (J = I2), and Nx memory value groups M [J−nL (mod Nx
L)] (n = 1,..., Nx) to generate the memory output value V0 by the following equation. Here, the value of the ratio Wn is 0 <Wn <2 / Nx (n = 1,..., Nx) (2). It has been standardized. Specifically, when Nx ≧ 2, Wn = 1 / Nx (n = 1,..., Nx)... (4) If the expression (1) is used, the memory value group M [J−nL (mod Nx
L)] (n = 1,..., Nx), and Nx
(Integer), which greatly simplifies the operation. (6) <Update storage unit 1F> The memory output value V0 and the rotation error E by the memory output value creation unit 1E are arithmetically combined at a ratio of 1: 1 to calculate an update value, and correspond to the second count variable I2. Memory value M in the ram area
[I2] is added (M [I2] = E + V0) and stored until the next update. Thereafter, the operation returns to the operation (1). With this configuration, it is extremely strong against a specific frequency component of the load torque fluctuation generated by the load 10 in FIG. 2, as in the patent of the prior application. Further, as shown in the present embodiment, each time the speed detector obtains a new detection signal, the control signal generating means generates a new control signal, and each time the speed detector obtains Q new signals, the update storage means Is updated by one memory value, the number of memories required for the memory means is substantially reduced by a factor of Q. That is, even if the number of memories is reduced in this way, the effect of extremely increasing the above-described specific frequency component of the load torque fluctuation (the effect of not causing the rotation speed fluctuation) is maintained. This can be explained as follows. It has been found that when the value of L is increased, the frequency component improved by the operation of the memory means, the memory output value creation means and the update storage means can be considerably lower than the detection frequency of the speed detector. Therefore, even if the frequency of the detection signal of the speed detector used in the update storage unit is reduced to 1 / Q, it is possible to prevent the above-described improvement effect from being adversely affected. If L = (Lq / Q) · k (where k is an integer of 2 or more), the rotation speed fluctuation due to the load torque fluctuation of k times the rotation period of the motor 1 is largely suppressed. Has the effect of doing Such an effect is very favorable in the case of a capstan motor of a video tape recorder. This will be described. Since the load of the capstan motor is a magnetic tape or a pinch roller, the load fluctuation generated by the load 10 is a component synchronous with the rotation of the motor 1 (periodic load fluctuation with one rotation of the motor 1 as a basic cycle). In addition, a load fluctuation component having a frequency lower than the rotation frequency of the motor 1 often occurs. Such load fluctuations cause fluctuations in the rotational speed of the capstan motor, and cause the tape speed to flutter. By the way, it has been found that such load fluctuations are often periodic fluctuations having a period that is an integral multiple of the period of one rotation of the motor 1. Therefore, by the above-described effect, a considerably low frequency fluctuation of the rotation speed of the motor 1 due to the fluctuation of the load torque can be effectively reduced. It should be noted that Q is not limited to a divisor of Zq (for example, if Q = k, Q is irrelevant to Zq). FIG. 4 shows a compensator 4 in consideration of the stability of the entire control system.
Here is an example of the program. Here, the method of calculating the update value in the update storage unit, the number of prepared memory output values in the memory output value creation unit, and the method of using the memory output value of the memory output value creation unit in the control signal creation unit are improved. doing. Next, the operation will be described in detail (the overall configuration is the same as that of FIG. 2 and the description is omitted). (11) <Rotation error detection unit 4A> First, the arithmetic unit 5 is a flip-flop 35 of the speed detector 3.
, And waits until the signal q becomes “H”. That is, it monitors that the speed detector 3 detects the (half) period of the AC signal a and outputs a new digital signal b. When q becomes "H", the digital signal b of the speed detector 3 is read and converted to the speed detection value S (digital value) corresponding to the digital signal b, and the reset signal r is set to "H" for a predetermined time to change the speed. Detector 3 counter
Reset 34 and flip-flop 35. Predetermined reference value
The speed detection value S is subtracted from Sref, the value is multiplied by R (here, R is a predetermined positive constant), and the current rotation error E of the motor 1 is calculated [E = R · (Sref−S )]. (12) <Control signal creation unit 4B> Memory output value V0 by memory output value creation unit 4E described later
And the rotation error E at the present time are calculated and synthesized at a predetermined ratio D: 1 to calculate a control signal value Y (Y = E + D · V0). The control signal Y is output to the D / A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y. (13) <First Counting Unit 4C> Each time a new speed detection value S is obtained, the first count variable I1 is incremented by using Q as a mod (modulus). I1
Is changed to Qa (where Qa is an integer smaller than Q), the memory output value V0 is changed to V [Px] described later. If I1 is not equal to Qa, such a change operation is not performed. Thus, in the range of I1 <Qa, V0 = V [Px-1] (described later).
V0 = V [Px] in the range of I1 ≧ Qa.
Further, if I1 is 0, the operation after (14) is executed, and if I is not 0, the operation returns to (11). (14) <Second counting unit 4D> With Nx · L being mod (modulus), the second count is performed each time the first count variable I1 becomes 0 (every Q new speed detection values S are obtained). Count up variable 12. (15) <Memory output value creation unit 4E> After sequentially transferring the contents of the register variable V (m + 1) to V [m] (m = 0, 1,... Px (where Px is 1 or more and 3
Integer J obtained by adding the following integer, preferably Px = 1)
[J = I2 + Px (mod Nx L)]. Memory value group M in the RAM area [J-nL (mod NxL)] (n = 1,..., N
Using x), put the latest memory output value calculated by the following equation into V [Px]. Here, the value of Wn satisfies the expressions (2), (3) and (4). That is, from V [Px] to V

Px + 1 memory output value groups continuous to [0] are obtained. At this time, V
When calculating [Px], let J1 be the integer J and the integer J in the equation (5),
V

Assuming that the integer J in the equation (5) for calculating [0] is J2, there is a relationship of J1 = J2 + Px. Next, the control signal creation unit 4B
The memory output value V0 used first in V is set to V [Px−
1] (V0 = V [Px-1]). (16) <Update storage unit 4F> After sequentially transferring the contents of the register variable X [m + 1] to X [m] (m = 0, 1, 2,..., 2Kd-1), X [2Kd)
(Where Kd is an integer and Kd = 3 is preferable) and the old memory output value V created by the memory output value creation unit 4E

[0] and the rotation error E at a ratio of 1: 1 are put in a composite value (X [2Kd] = E + V

[0]). That is, from X [2Kd] to X

Then, 2Kd + 1 additional values (added value of the memory output value and the rotation error) continuous to [0] are obtained. Nx L
Integer K obtained by subtracting Kd from the second count variable I2 as mod
[K = I2-Kd (mod Nx L)]. Next, X
[M] is multiplied by a predetermined positive ratio Cm (m = 0, 1,..., 2Kd) to obtain a new updated value. Store and save until update.
That is, And Here, the ratio Cm has the following relationship. Cm = C2Kd-m (m = 0, 1,..., Kd) (7) Thereafter, the operation returns to the operation of (11). As in the present embodiment, a calculation for obtaining a weighted average is inserted into the update storage unit 4F, or the first memory output value V0 (V [P
x]) and the second memory output value V of the memory output value creation unit 4E used in the update storage unit 4F.

A predetermined deviation (V [Px] is V

It was confirmed that the operation of the entire control system would be stable if (0) was provided. In particular, it has been found that the values of Px and Qa related to the use timing are deeply related to the value of Q, and it is better to satisfy (QPx−Qa) ≧ Q / 2. This is because the same memory output value (for example, V

This means that when the use timing in the control signal creation unit 4B is converted into the number of times of detection in the speed detection period, the use timing in the update storage unit 4F of the value [0]) is Q / 2 times or more. . FIG. 5 shows a compensator 4 in consideration of the stability of the entire control system.
Here is another program example. Here, the method of calculating the memory output value and the number of preparations in the memory output value generator and the method of using the memory output value of the memory output value generator in the control signal generator are improved. Next, the operation will be described in detail (the overall configuration is the same as that of FIG. 2 and the description is omitted). (21) <Rotation error detection unit 5A> First, the arithmetic unit 5 is a flip-flop 35 of the speed detector 3.
, And waits until the signal q becomes “H”. That is, it monitors that the speed detector 3 detects the (half) period of the AC signal a and outputs a new digital signal b. When q becomes "H", the digital signal b of the speed detector 3 is read and converted to the speed detection value S (digital value) corresponding to the digital signal b, and the reset signal r is set to "H" for a predetermined time to change the speed. Detector 3 counter
Reset 34 and flip-flop 35. Predetermined reference value
The speed detection value S is subtracted from Sref, the value is multiplied by R (here, R is a predetermined positive constant), and the current rotation error E of the motor 1 is calculated [E = R · (Sref−S )]. (22) <Control signal creation unit 5B> Memory output value VO by memory output value creation unit 5E described later
And the rotation error E at the present time are calculated and synthesized at a predetermined ratio D: 1 to calculate a control signal value Y (Y = E + D · V0). The control signal value Y is output to the D / A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y. (23) <First Counting Unit 5C> The first count variable I1 is incremented each time a new speed detection value S is obtained, using Q as a mod (modulus). I1
Is changed to Qa (where Qa is an integer smaller than Q), the memory output value V0 is changed to V [Px] described later. If I1 is not equal to Qa, such a change operation is not performed. Thus, in the range of I1 <Qa, V0 = V [Px-1] (described later).
, And V0 = V [px] in the range of I1 ≧ Qa.
Further, if I1 is 0, the operation after (24) is executed and I1 becomes 0
If not, the operation returns to the operation of (21). (24) <Second count unit 5D> With Nx · L being mod (modulus), the second count is performed each time the first count variable I1 becomes 0 (every Q new speed detection values S are obtained). Count up the variable I2. (25) <Memory output value creation unit 5E> After sequentially transferring the contents of the register variable X [m + 1] to X [m] (m = 0, 1, 2,..., 2Kd−1), mod
As the second count variable I2, Px + Kd (Px is 1 or more and 3
Is an integer J, where Kd is an integer of 1 or more)
[J = I2 + Px + Qx (mod Nx L)]. Nx memory value groups M [J-nL (mod NxL)] (n =
1, ... Nx) and the calculated value by the following equation
[2Kd]. Here, the value of Wn satisfies the expressions (2), (3) and (4). That is, from X [2Kd] to X

2Kd + 1 calculation values (calculation values obtained from Nx memory values separated by L intervals) successive to [0] are obtained. Next, after the contents of the register variable V [m + 1] are sequentially transferred to V [m] (m = 0, 1,..., Px−1), X [m] (m = 0, 1,. , 2K
d) is multiplied by a predetermined positive ratio Cm (m = 0, 1,..., 2Kd) to obtain the latest memory output value obtained by adding and synthesizing, and V [Px]
Put in. Here, the ratio Cm has the relationship of the equations (7) and (8).
That is, from V [Px] to V

Px + 1 memory output values continuous to [0] are obtained. At this time, V [Px]
Is calculated, and the integer J in the equation (9) is set to J1.

Assuming that the integer J in the equation (9) for calculating [0] is J2, there is a relationship of J1 = J2 + Px. That is, V [Px] and V

There is a shift corresponding to the integer Px between [0]. Next, the memory output value V0 is set to V [Px-1] (V0 = V [Px-
1]. (26) <Update storage unit 5F> Old memory output value V created by memory output value creation unit 5E

[0] and the rotation error E are arithmetically combined at a ratio of 1: 1 to calculate an update value, and update the memory value M [I2] in the ram area corresponding to the second count variable I2 (M [ I2] = E
+ V

[0]), and store until the next update. Thereafter, the operation returns to the operation of (21). As in the present embodiment, a calculation for taking a weighted average and a calculation for preparing a plurality of memory output values are inserted into the memory output value creation unit 5E, and the memory output value creation unit 5E of the memory output value creation unit 5E used in the control signal creation unit 5B. One memory output value Vo (V [Px]) and the second memory output value V of the memory output value creation unit 5E used in the update storage 5F

A predetermined deviation (V [Px] is V

If (0) is provided, the operation of the entire control system becomes stable. Also in this case, (Q Px−Qa) ≧ Q /
Better to 2 It should be noted that the calculation using the ratios Wn and Cm is not limited to the above-described form, but may be any as long as it substantially realizes the contents of the above-described program, and it is needless to say that various equivalent expression transformations are possible. No. Also, when a new rotation error is obtained, the control signal generating unit first performs a new control signal output operation, and then the memory output value generating unit calculates the memory output value to be used at the next sampling time. In this case, the operation time of the memory output value creation unit can be extended, and the time delay until the output of the control signal can be shortened, so that the stability of the control system can be easily secured. In each of the above embodiments, only the rotation speed of the motor is detected by the speed detector, but in addition to this, the rotation phase of the motor is detected by a well-known phase detector, and the two are combined to generate a rotation error. Needless to say, this is included in the present invention. Further, the output of the compensator may be a digital signal or a PWM signal (pulse width modulation signal), or the output signal of the power image width unit (driving means) may be a PWM signal. Further, a brushless DC motor may be used as the motor. Further, the compensator may be constituted by complete hardware such as a PLA (Programmable Logic Array) or the like, so that the same operation as the above-described operation by the program may be performed. Further, an analog operation element may be used. In addition, various changes can be made without changing the gist of the present invention. Advantageous Effects of Invention The motor speed control device of the present invention has extremely good control characteristics at a specific frequency while greatly reducing the number of memories, and the fluctuation of the rotation speed due to the fluctuation of the load torque is greatly reduced. Has been reduced. Therefore, if a capstan motor of a video tape recorder is configured based on the present invention, a high-performance motor speed control device can be economically configured.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an example of a built-in program of the compensator shown in FIG. 2, FIG. 2 is a block diagram showing an entire configuration of an embodiment of the present invention, and FIG. FIG. 4 is a configuration diagram showing a specific configuration example, FIG. 4 is a flowchart diagram showing another example of a built-in program of the compensator of the present invention, and FIG. 5 is a flowchart showing another example of a built-in program of the compensator of the present invention. FIG. 1 ... motor, 2 ... rotation sensor, 3 ... speed detector,
4 Compensator, 5 Computing unit, 6 Memory, 7 D /
A converter, 8: Power amplifier, 10: Load.

Claims (1)

(57) [Claims] 1. A rotation sensor for generating an AC signal having a cycle corresponding to a rotation speed of a motor, speed detection means for detecting a plurality of times per rotation of the motor based on the AC signal of the rotation sensor, and the speed detection means And compensating means for calculating and storing the control signal based on the detection signal of the above, and driving means for driving the motor in response to the control signal of the compensating means, wherein the compensating means detects the speed of the speed detecting means. A rotation error detecting means for obtaining a rotation error in response to the signal, and Nx L pieces of data updated by the update storage means (where Nx is an integer of 1 or more;
L is an integer of 4 or more) M [0], M [1],.
.., M [NxL-1], and a memory output value for obtaining a first memory output value and a second memory value created from the memory value stored in the memory means A memory value of the memory means by an update value obtained by arithmetically synthesizing a second memory output value of the memory output value creating means and a rotation error of the rotation error detection means.
.., M [NxL−1] in the order of [0], M [1],..., M [NxL−1], a first memory output value of the memory output value creating means, and the rotation error detecting means. And control signal generating means for generating the control signal by arithmetically synthesizing the rotation error of the control signal so that the control signal generating means generates a new control signal each time the speed detecting means obtains the new detection signal. Each time the speed detecting means obtains Q new detection signals (where Q is an integer of 2 or more), the memory output value creating means and the update storing means operate to operate the memory means. Is updated, and the first memory output value used in the control signal generating means is Nx memory values M [J1- nL (mod Nx L)] (n =
1,..., Nx) (where J1 is an integer) and the second memory output value used in the update storage means is Nx memory values M [J2- nL (mo
d Nx L)] (n = 1,..., Nx) (where J2 is an integer), and the integers J1 and J2 are calculated as J1 = J2 + Px (mod Nx
L) (where Px is an integer of 1 or more).