JPH0681533B2 - Motor speed controller - Google Patents

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor speed control device. 2. Description of the Related Art A motor speed control device that detects the rotation speed of a motor with a speed detector and controls the power supplied to the motor by the detection signal is widely used for capstan motors and cylinder motors of video tape recorders. (See, for example, Japanese Patent Application No. 56-142724 proposed by the applicant). However, in such a speed control device, only the conventionally used proportional / integral / derivative control is performed, and it is not possible to sufficiently suppress the fluctuation of the rotation speed due to the fluctuation of the load torque. In order to solve such a problem, the present applicant has filed Japanese Patent Application No.
-229143 (not known) and Japanese Patent Application No. 60-229144 (not known) proposed a high-performance motor speed control device that is extremely resistant to load torque fluctuations. That is, in Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-229144, a rotation sensor that generates an AC signal with a cycle corresponding to the rotation speed of the motor and a plurality of rotation sensors per rotation of the motor by the AC signal of the rotation sensor A speed detecting means for detecting, a compensating means for calculating and storing a control signal based on a detection signal of the speed detecting means, and a power amplifying means (driving means) for supplying electric power according to the control signal of the compensating means to the motor. ) Constitutes the speed control system. Further, a rotation error detecting means for obtaining a rotation error in response to the detection signal of the speed detecting means, and N _x L
Memory value groups M [O] to M [N _x L-1]
A memory means for storing, and a composite value calculating means (memory output value creating means) for substantially calculating a composite value calculated by using N _x memory value groups separated by L intervals of the memory means. An update storage means for updating and storing the memory values of the memory means in a substantially sequential manner by an update value corresponding to a value obtained by arithmetically combining the combined value of the combined value calculation means and the rotation error of the rotation error detection means, and the combined value calculation means A high-performance motor speed control device is realized by using a compensating means having a control signal generating means for arithmetically combining the combined value and the rotation error of the rotation error detecting means to generate a control signal. Problems to be Solved by the Invention However, in Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-229144, it is indispensable to use a large number of digital memories, and normally 16 bits × 1000 words = 16 kbits Memory is needed. Although IC devices for memories have been rapidly reduced in price due to recent improvements in semiconductor manufacturing technology, it is not preferable to use a memory of 16 kbits because the cost is significantly increased. In consideration of such a point, the present invention is devised so that the required number of memories in the motor speed control device using a large number of memories as shown in the above example is significantly reduced. Means for Solving the Problems In the motor speed control device of the present invention, a rotation sensor that generates an AC signal with a cycle corresponding to the rotation speed of the motor, and Zq per rotation of the motor by the AC signal of the rotation sensor.
The speed detecting means for detecting the number of times (where Zq is an integer of 8 or more), the compensating means for generating a control signal based on the detection signal of the speed detecting means, and the motor according to the control signal of the compensating means. The compensating means comprises a driving means for driving, and the compensating means, at each detection timing at which the speed detecting means obtains a new detection signal, a rotation error detecting means for obtaining a new rotation error based on the detection signal, and Nx · L ( Where Nx is 1
Memory means for storing and storing ordered memory values of the above integers, where L is an integer of 4 or more); and a synthetic error creating means for producing a synthetic error by arithmetically synthesizing a plurality of rotation errors of the rotation error detecting means, The Nx · L memory values are sequentially combined with the composite error of the composite error creating means by using the timing at which the rotation error detection means obtains a new rotation error Q times (where Q is an integer of 2 or more) as update timing. An update saving means for updating and saving the memory output value of the memory output value creating means by an update value obtained by arithmetic synthesis, and at least one memory value when Nx is 1, and an update interval when Nx is 2 or more. Using at least one set of Nx memory value groups separated by L times or more of the update timing, the memory output value creating means for creating the memory output value in synchronization with the update timing; The above problem is caused by including the control signal generating means for arithmetically synthesizing the rotation error of the rotation error detecting means and the memory output value of the memory output value generating means at each detection timing to generate the control signal. Has been resolved. Action In the present invention, by using the above-mentioned structure, Japanese Patent Application No.
As described in Japanese Patent Application No. 229143 and Japanese Patent Application No. 60-229144, it is possible to significantly reduce the influence of load torque fluctuation at a specific frequency. Moreover, an economically high-performance motor speed control device is realized by using a small number (1 / Q) of the number of memories. Embodiment Hereinafter, a motor speed control device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing an embodiment of the present invention. In FIG. 2, the DC motor 1 directly drives the rotation sensor 2 and the load 10 to rotate. The rotation sensor 2 rotates Z _q times (Z _q
Is an integer of 2 or more, and a capstan motor of a video tape recorder normally generates an AC signal a of Z _q = 357). The AC signal a of the rotation sensor 2 is input to the speed detector 3, and a digital signal b corresponding to the cycle of the AC signal a is obtained. FIG. 3 shows a specific configuration example of the speed detector 3. The AC signal a is waveform-shaped by the waveform shaping circuit 31 to obtain the shaped signal g. The shaping signal g is input to the AND circuit 33 and the flip-flop 35. On the input side of the AND circuit 33, the clock pulse p of the oscillation circuit 32 and the counter are further provided.
34 overflow output signals w are also input. The oscillation circuit 32 is composed of a crystal oscillator, a frequency divider, etc., and has a clock pulse p of a frequency considerably higher than the frequency of the shaping signal g.
(About 500kHz) is generated. The counter 34 is a 12-bit up counter that counts up the contents of the output pulse h of the AND circuit 33 each time it arrives. The overflow output signal w is “H” when the count content of the counter 34 is less than or equal to a predetermined value, and w changes to “L” when the count content of the counter 34 is greater than or equal to the predetermined value (here, “H”). Represents a high potential state, "L" represents a low potential state). The data input flip-flop 35 takes in "H" input to the data input terminal with the falling edge of the shaping signal g as a trigger signal, and outputs its output Q to "H".
(Q = “H”). Further, when the reset signal r from the compensator 4 becomes “H”, the counter 34 and the flip-flop 35.
The internal state of is reset (b = "LLLLLLLLLLLL",
w = “H”, q = “L”). Next, the operation of the speed detector 3 shown in FIG. 3 will be described.
Now, it is assumed that the counter 34 and the flip-flop 35 are reset by the reset signal r. When the output signal g of the waveform shaping circuit 32 changes from "L" to "H", the clock pulse p of the oscillation circuit 32 is output as the output signal h of the AND circuit 33.
Is output. The counter 34 counts the output signal h,
The internal state is changed. When the output signal g of the waveform shaping circuit 31 changes from "H" to "L", the output signal h of the AND circuit 33 becomes "L", and the counter 34 holds its internal state. Further, the flip-flop 35 takes in the data "H" at the falling edge of the signal g and outputs its output signal q.
Is changed from “L” to “H”. The digital signal b of the counter 34 is a value proportional to the (half) cycle length of the AC signal a of the rotation sensor 2 and inversely proportional to the rotation speed of the motor 1. The compensator 4, which will be described later, looks at the output signal q of the flip-flop 35, inputs the digital signal b of the counter 34 when q becomes “H”, and then outputs the reset signal r to “H” for a predetermined short time. Then, the counter 34 and the flip-flop 35 are reset to the initial state to prepare for the next speed detection operation.
When the rotation speed of the motor 1 is too slow, the internal state of the counter 34 exceeds a predetermined value because the cycle of the output signal g of the waveform shaping circuit 31 is long, and the overflow output signal w
May change from "H" to "L", the output signal h of the AND circuit 33 becomes "L", and the counter 34 may hold a predetermined large value. The compensator 4 of FIG. 2 is composed of a computing unit 5, a memory 6 and a D / A converter 7, and a digital signal b of the speed detector 3 is obtained.
Is calculated and processed by a built-in program described later, and a control signal c is output. The control signal c of the compensator 4 is input to the power amplifier 8 (driving means), and the power amplified drive signal d.
(Current proportional to the control signal c) is supplied to the motor 1. Therefore, the motor 1, the rotation sensor 2, the speed detector 3, the compensator 4, and the power amplifier 8 (driving means) constitute a speed control system, and the rotation speed of the motor 1 is controlled to a predetermined value. The memory 6 of the compensator 4 is divided into a ROM area (ROM: read only memory) in which a predetermined program and constants are stored and a RAM area (RAM: random access memory) in which a required value is stored at any time. The computing unit 5 performs a predetermined operation or computation according to a program in the ROM area. FIG. 1 shows a concrete example of the program. Next, the operation will be described in detail. (1) <Rotation error detecting means 1A> First, the arithmetic unit 5 inputs the output signal q of the flip-flop 35 of the speed detector 3 and waits for the signal q to become “H”. That is, it is monitored that the speed detector 3 detects the (half) cycle of the AC signal a and outputs a new digital signal b. When q becomes "H", the digital signal b of the speed detector 3 is read, the speed detection value S (digital value) corresponding to the digital signal b is read, and the reset signal r is set to "H" for a predetermined time to set the speed. Counter 34 of detector 3
And reset the flip-flop 35. Predetermined reference value Sr
The speed detection value S is subtracted from ef, and the value is multiplied by R (here,
R is a predetermined positive constant), and the current rotation error E of the motor 1 is calculated [E = R. (Sref-S)]. (2) <Control signal creating means 1B> The memory output value V0 by the memory output value creating means, which will be described later, and the current rotation error E are set to a predetermined ratio D: 1 (where D is 0).
A control signal value Y is calculated (Y = E + D · V0) by performing arithmetic synthesis with a constant of <D ≦ 1, preferably D = 1). The control signal value Y is output to the D / A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y. (3) <Save 1C of rotation error time series> Memory value F [I [I] corresponding to a first count variable I1 described later.
The current rotation error E is stored and saved in [1] (F [I
1] = E). (4) <First Counting Means 1D> Q (where Q is an integer of 2 or more) is mod (modulus),
Each time a new speed detection value S is obtained, the first count variable I1 is incremented. That is, I1 = I1 + 1 (I1 +
1 is changed to I1), then I1 is set to 0 if I1 = Q
Reset to. If such an operation is performed, I1 is 0
To an integer between Q-1. The initial value of I1 is 0. If I1 is 0, the operation after (5) is executed and I1 becomes 0.
If not, the operation returns to (1). (5) <Synthesis error creating means 1E> F [m] (m
= 0,1, ..., Q-1) stores Q consecutive rotation errors. F _d of these (where F _d is 2 or more and Q
The latest rotation error F [Q-m] (m = 1,2,
……, F _d ), and a predetermined ratio B _m (m = 1,2, ……,
The value multiplied by F _d ) is added and combined to generate a combined error E _g . That is, Where the coefficient B _m is There is a relationship. further, Have been standardized. (6) <Second Counting Means 1F> N _x · L (Generally, N _x is an integer, L is an integer of 4 or more. However, N _x is an integer of 2 or more, and L is (Z _q / Q) 2 Since it is preferable that the integer is an integer multiple of the above, such a case will be described below) as a mod (modulus), and each time the first count variable I1 becomes 0 (new speed detection value S is changed to Q The second count variable I2 is incremented each time a new number is obtained. That is, after setting I2 = I2 + 1, I2 is reset to 0 if I2 = N _× L. If such an operation is performed, I2 will be an integer between 0 and N _x L-1. The initial value of I2 is N _x L-1. (7) <Memory output value creating means 1G> The integer J is made equal to I2 (J = I2), and N _x memory value groups M [J-nL (modN _x L) are separated by L intervals in the RAM area. ] (N
= 1, ..., N _x ) is used to generate the memory output value V0 by the following equation. Here, the value of the ratio W _n is 0 <W _n <2 / N _x (n = 1, ..., N _x ) ... (5), and Is standardized. Specifically, if W _n = 1 / N _x (n = 1, ..., N _x ) ... (7) when N _x ≧ 2, the equation (4) becomes the memory value group M [J- nL (modN _x L))
(N = 1, ..., N _x ) is simply added and synthesized, and then divided by N _x (integer), which greatly simplifies the operation. (8) <Update / storing means 1H> Memory output value V0 and synthesis error by the memory output value creating means
Calculate the update value by calculating and combining E _g at a ratio of 1: 1
Memory value M in the RAM area corresponding to the count variable I2 of
[I2] is updated (M [I2] = _Eg + V0) and stored and saved until the next update. After that, the operation returns to (1). With such a configuration, it is extremely strong against a specific frequency component of the load torque fluctuation caused by the load 10 in FIG. 2 that the patent of the prior application (Japanese Patent Application No. 60-229143, 60-229144).
Is the same as. Furthermore, as shown in the present embodiment, each time the speed detector 3 obtains a new detection signal, the control signal generating means 1B
Generates a new control signal, and each time the speed detector 3 obtains Q new detection signals, the update storing means 1H updates one memory value, so that the memory means is substantially stored. The number of required memories was reduced to 1 / Q. As described above, even if the number of memories is significantly reduced, it is possible to secure the effect of being extremely strong with respect to the specific frequency component of the load torque fluctuation (the effect of causing no rotation speed fluctuation). This is because when the value of L is increased, the frequency component improved by the compensator 4 described above becomes
It turns out that it can be made considerably lower than the detection frequency of
Even if the update frequency of the update saving means 1H is reduced to 1 / Q, a synthetic error E _g is created from a plurality of rotation errors E, and the memory value is updated and saved using this synthetic error E _g. This is because it was possible to prevent the system stability and the above-described improvement effect from being adversely affected. Furthermore, as shown in this embodiment obtains a combined error E _g by combining F _d number of rotational errors successive memory value M by combining values of the combined error E _g and the memory output value V ₀ [I2] It has been found that the operation of the control system can be prevented from becoming unstable due to unnecessary noise components included in the rotation error if is updated. This is because the combined error creating unit 1E has an effect of preventing the influence of a considerably high frequency fluctuation included in the rotation error E from entering the memory value of the update saving unit 1H and the memory output value of the memory output value creating unit 1G. Because I was able to get it. Further, if L = (Z _q / Q) · k (where k is an integer), the rotation speed fluctuation due to the load torque fluctuation in a cycle of k times (an integer times) of one rotation cycle of the motor 1 is significantly increased. Has the effect of suppressing. Such an effect is very preferable in the case of a capstan motor of a video tape recorder. This will be described. Since the load of the capstan motor is a magnetic tape or a pinch roller, the load fluctuation generated by the load 10 is a component synchronized with the rotation of the motor 1 (periodic load fluctuation with one rotation of the motor 1 as a basic cycle). Besides, a load fluctuation component having a frequency lower than the rotation frequency of the motor 1 often occurs. Such load fluctuations cause fluctuations in the rotational speed of the capstan motor, causing wow and flutter of the tape speed. By the way, it has been found that such load fluctuations often have periodic fluctuations having a cycle that is an integral multiple of the cycle of one rotation of the motor 1. Therefore, due to the above-mentioned effect, a considerably low frequency fluctuation of the rotation speed of the motor 1 due to the load torque fluctuation can be effectively reduced. It should be pointed out that Q is not limited to a divisor of Z _q (for example, if Q = k, then Q becomes independent of Z _q ). FIG. 4 shows a program example of the compensator 4 in consideration of the stability of the entire control system. Here, the method of calculating the update value in the update saving means, the number of preparations of the memory output value in the memory output value creating means, and the method of using the memory output value in the control signal creating means are improved. ing. Next, the operation will be described in detail (the entire configuration is the same as that in FIG. 2, and the description is omitted). (11) <Rotation error detecting means 4A> First, the arithmetic unit 5 inputs the output signal q of the flip-flop 35 of the speed detector 3 and waits for the signal q to become "H". That is, it is monitored that the speed detector 3 detects the (half) cycle of the AC signal a and outputs a new digital signal b. When q becomes "H", the digital signal b of the speed detector 3 is read, the speed detection value S (digital value) corresponding to the digital signal b is read, and the reset signal r is set to "H" for a predetermined time to set the speed. Counter 34 of detector 3
And reset the flip-flop 35. Predetermined reference value Sr
The speed detection value S is subtracted from ef, and the value is multiplied by R (here,
R is a predetermined positive constant), and the current rotation error E of the motor 1 is calculated [E = R. (Sref-S)]. (12) <Control signal creating means 4B> The memory output value V0 by the memory output value creating means to be described later and the current rotation error E are arithmetically combined at a predetermined ratio D: 1,
The control signal value Y is calculated (Y = E + D · V0). The control signal value Y is output to the D / A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y. (13) <Saving of rotation error time series 4C> Memory value F [I] corresponding to a first count variable I1 described later.
The current rotation error E is stored and saved in [1] (F [I
1] = E). (14) <First Counting Means 4D> With Q as a mod, the first count variable I1 is incremented each time a new speed detection value S is obtained. I1 is
When it becomes equal to Q _a (where Q _a is an integer smaller than Q), the memory output value V0 is changed to V [P _x ] described later, and when I1 is not equal to Q _a , such a changing operation is performed. Not performed. This causes the I1 <Q _a in the range of V0 = V [P _x -1] (described later), in the range of I1 ≧ Q _a has become V0 = V [P _x]. Furthermore, if I1 is 0, the operation after (15) is executed and I1 becomes 0.
If not, it returns to the operation of (11). (15) <Composite error creating means 4E> F [m] (m
= 0,1, ..., Q-1) stores Q consecutive rotation errors. F _d number of the most recent rotation error F of among this [Q-
m] (m = 1, 2, ..., F _d ), each has a predetermined ratio B _m (m
= 1,2, ..., F _d )
Create E _g [Equations (1), (2), (3)]. (16) <Second Counting Means 4F> The first count variable I1 is 0 when N _x · L is mod (modulus).
Every 2 times (every Q new speed detection values S are obtained)
The count variable I2 of is incremented. (17) <Memory output value creating means 4G> After transferring the contents of the register variable V [m + 1] to V [m] in order (m = 0, 1, ..., P _x −1), N _x L As a mod, an integer J is calculated by adding P _x (where P _x is an integer of 1 or more and 3 or less, and P _x = 1 is preferable) to the second counter variable I2 [J = I2 + P _x (mod N _x L)]. The latest memory output value calculated by the following equation using the memory value group M [J-nL (mod N _x L)] (n = 1, ..., N _x ) in the RAM area is V
Put in [P _x ]. Here, the value of W _n satisfies the equations (5), (6) and (7). That is, from V [P _x ] to V

A group of P _x +1 memory output values consecutive to [0] is obtained. At this time, V
Let V be the integer J in equation (8) when calculating [P _x ]

When the integer J in the equation (8) when calculating [0] is J2, there is a relation of J1 = J2 + P _x . Next, the memory output value V0 used first in the control signal generating means is set to V [P _x −
1] (V0 = V [P _x -1]). (18) <Update storing means 4H> After transferring the contents of the register variable X [m + 1] to X [m] in order (m = 0,1,2, ..., 2K _d −1), X [2K _d ]
(Where K _d is an integer, preferably K _d = 3), the old memory output value V created by the memory output value creating means

[0] and the composite error E _g are arithmetically combined at a ratio of 1: 1 and the composite value is entered (X [2K _d ] = E _g + V

[0]). That is, from X [2K _d ] to X

2K _d +1 addition values (addition value of memory output value and synthesis error) continuous to [0] are obtained. N _x L
Is used as mod and an integer K is calculated by subtracting K _d from the second count variable I2 to calculate K [K = I2−K _d (mod N _× L)]. Next, a predetermined positive ratio C _m (m = 0,1, ..., 2K _d ) to X [m]
A new updated value obtained by adding and synthesizing the values multiplied by is obtained and stored as the memory value M [K] in the RAM area until the next updating. That is, And Here, the ratio C _m has the following relationship. Then, the operation returns to (11). As in the present embodiment, the calculation for taking the weighted average is inserted into the update storage means 4H, or the first memory output value V0 (V0 of the memory output value generation means 4G used in the control signal generation means 4B is used.
[P _x ]) and the second memory output value V of the memory output value creating means 4G used in the update storing means 4H.

A certain deviation (V [P _x ] is V

It has been confirmed that the operation of the entire control system becomes stable if (0) is provided). In particular, the value of P _x and Q _a related to its use timing deeply related to the operand number F _d of the combined error preparing means 4E, (QP _x -
We also found that it is better to make Q _a ) ≧ (Q + F _d ) / 2.
This means that the same memory output value (for example, V

Compared with the use timing in the update storage means 4H in [0]), when the use timing in the control signal creating means 4B is converted into the number of detection times of the speed detector 3, it is (Q + F _d ) / 2 times faster than means. FIG. 5 shows another program example of the compensator 4 in consideration of the stability of the entire control system. Here, the method of calculating the memory output value in the memory output value creating means and the number of preparations, and the way of using the memory output value of the memory output value creating means in the control signal creating means are improved. Next, the operation will be described in detail (the entire configuration is the same as that in FIG. 2, and the description is omitted). (21) <Rotation error detecting means 5A> First, the arithmetic unit 5 inputs the output signal q of the flip-flop 35 of the speed detector 3 and waits until the signal q becomes "H". That is, it is monitored that the speed detector 3 detects the (half) cycle of the AC signal a and outputs a new digital signal b. When q becomes "H", the digital signal b of the speed detector 3 is read, the speed detection value S (digital value) corresponding to the digital signal b is read, and the reset signal r is set to "H" for a predetermined time to set the speed. Counter 34 of detector 3
And reset the flip-flop 35. Predetermined reference value Sr
The speed detection value S is subtracted from ef, and the value is multiplied by R (here,
R is a predetermined positive constant), and the current rotation error E of the motor 1 is calculated [E = R. (Sref-S)]. (22) <Control signal creating means 5B> The memory output value V0 by the memory output value creating means described later and the current rotation error E are arithmetically combined at a predetermined ratio D: 1,
Calculate the control signal value Y (Y = E + D · V0). The control signal value Y is output to the D / A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y. (23) <Saving the rotation error time series 5C> The memory value F [I] corresponding to the first count variable I1 described later.
The current rotation error E is stored and saved in [1] (F [I
1] = E). (24) <First Counting Means 5D> With Q as a mod, the first count variable I1 is incremented each time a new speed detection value S is obtained. I1 is
When it becomes equal to Q _a (where Q _a is an integer smaller than Q), the memory output value V0 is changed to V [P _x ] described later, and when I1 is not equal to Q _a , such a changing operation is performed. Not performed. This causes the I1 <Q _a in the range of V0 = V [P _x -1] (described later), in the range of I1 ≧ Q _a has become V0 = V [P _x]. Furthermore, if I1 is 0, the operation after (25) is executed and I1 becomes 0.
If not, the operation returns to (21). (25) <Composite error creating means 5E> F [m] (m
= 0,1, ..., Q-1) stores Q consecutive rotation errors. F _d number of the most recent rotation error F of among this [Q-
m] (m = 1, 2, ..., F _d ), each has a predetermined ratio B _m (m
= 1,2, ..., F _d )
Create E _g [Equations (1), (2), (3)]. (26) <Second Counting Means 5F> The first count variable I1 is 0 when N _x · L is mod (modulus).
Every 2 times (every Q new speed detection values S are obtained)
The count variable I2 of is incremented. (27) <Memory output value creating means 5G> After the contents of the register variable X [m + 1] are sequentially transferred to X [m] (m = 0, 1, 2, ..., 2K _d −1), N _{x Let} L be a mod and calculate an integer J by adding P _x + K _d (P _x is an integer of 1 or more and 3 or less and K _d is an integer of 1 or more) to the second count variable I2 [J = I2 + P _x + Q _x (mod N _x L)]. N in the ram region
_x memory value group M [J-nL (mod N _x L)] (n = 1, ..., N
_x ) is calculated by the following formula as X [2K _d ]
Put in. Here, the value of W _n satisfies the equations (5), (6) and (7). That is, from X [2K _d ] to X

2K _d +1 calculated values (calculated values obtained from N _x memory values separated by L intervals) consecutive to [0] are obtained. Next, after sequentially transferring the contents of the register variable V [m + 1] to V [m] (m = 0,1, ..., _Px- 1), X [m] (m = 0,1, ... …, 2
The latest memory output value obtained by adding and combining a value obtained by multiplying K _d ) by a predetermined positive ratio C _m (m = 0,1, ..., 2K _d ) is obtained, and V [P _x ]
Put in. Here, the ratio C _m has a relationship of equations (10) and (11). That is, from V [P _x ] to V

P _x +1 memory output values consecutive to [0] are obtained. At this time, the integer J in the equation (12) when substantially calculating V [P _x ] is J1, and V is substantially V

If the integer J2 in the equation (12) when calculating [0] is J1
Relationship of = J2 + P _x. That is, V [P _x ] and V

[0]
There is a gap corresponding to the integer P _x . Next, the memory output value V0 is set to V [P _x -1] (V0 = V [P _x -1]). (28) <Update storing means 5H> Old memory output value V created by the memory output value creating means

[0] and the composite error E _g are arithmetically combined at a ratio of 1: 1 to calculate the update value, and the memory value M [I2] in the RAM area corresponding to the second count variable I2 is updated (M [I2] = E _g +
V

[0]), store and save until the next update. After that,
Return to the operation of (21). As in the present embodiment, the arithmetic operation for taking a weighted average and the arithmetic operation for preparing a plurality of memory output values are inserted in the memory output value creating means 5G, and the memory output value creating means 5G used in the control signal creating means 5B One memory output value V0 (V [P _x ])
And the second memory output value V of the memory output value creating means 5G used in the update storing means 5H.

A certain deviation (V [P _x ] is V

If it is more advanced than [0], the operation of the entire control system becomes stable. Again, (QP
_It is better to make _x- Q _a ) ≧ (Q + F _d ) / 2. The calculation by the ratios W _n and C _m is not limited to the above-mentioned form, and it suffices as long as it substantially realizes the contents of the above-mentioned program, and various equivalent formula modifications are possible. Needless to say. Also, when a new rotation error is obtained, the control signal creating means first outputs a new control signal, and then the memory output value creating means calculates the memory output value to be used at the next sampling time. In this case, the calculation time of the memory output value creating means can be lengthened and the time delay until the output of the control signal can be shortened, so that the stability of the control system can be easily ensured. In each of the above-described embodiments, the speed detector detects only the rotation speed of the motor, but in addition to this, the rotation phase of the motor is detected by a well-known phase detector, and both are combined to generate a rotation error. Needless to say, it is included in the present invention. Further, the output of the compensator may be a digital signal or a PWM signal (pulse width modulation signal), or the output signal of the power amplifier (driving means) may be a PWM signal.
A brushless DC motor may be used as the motor.
Further, the compensator may be composed of complete hardware such as a PLA (Programmable Logic Array) or the like so as to perform the same operation as the above-mentioned program. Alternatively, an analog arithmetic element may be used. Besides, various modifications can be made without changing the gist of the present invention. Advantageous Effects of Invention The motor speed control device of the present invention has extremely good control characteristics at a specific frequency while significantly reducing the number of memories, and the fluctuation of the rotation speed due to the fluctuation of the load torque is significantly reduced. Has been reduced. Therefore, if a capstan motor of a video tape recorder is constructed according to the present invention, a high speed motor speed control device can be economically constructed.

[Brief description of drawings]

1 is a flow chart showing an example of a built-in program of the compensator shown in FIG. 2, FIG. 2 is an overall configuration diagram of an embodiment of the present invention, and FIG. 3 is a concrete example of the speed detector shown in FIG. FIG. 4 is a configuration diagram showing a configuration example, FIG. 4 is a flow chart diagram showing another example of a built-in program of the compensator of the present invention, and FIG. 5 is a flow chart diagram showing another example of a built-in program of the compensator of the present invention. . 1 ... motor, 2 ... rotation sensor, 3 ... speed detector,
4 ... Compensator, 5 ... Calculator, 6 ... Memory, 7 ... D /
A converter, 8 ... Power amplifier, 10 ... Load, 1A, 4A, 5A ...
… Rotation error detection means, 1B, 4B, 5B …… Control signal creation means,
1E, 4E, 5E ... Composite error creation means, 1G, 4G, 5G ... Memory output value creation means, 1H, 4H, 5H ... Update storage means.

Claims (2)

[Claims] 1. A rotation sensor that generates an AC signal having a cycle corresponding to the rotation speed of a motor, and detection of Zq times (where Zq is an integer of 8 or more) per rotation of the motor based on the AC signal of the rotation sensor. Comprising: speed detecting means for performing, a compensating means for producing a control signal based on a detection signal of the speed detecting means, and a driving means for driving the motor according to the control signal of the compensating means, wherein the compensating means is Rotation error detection means for obtaining a new rotation error based on the detection signal at each detection timing at which the speed detection means obtains a new detection signal, and Nx · L (where Nx is an integer greater than or equal to 1 and L is 4) Memory means for storing and storing ordered memory values of (the above integers); synthetic error creating means for producing a synthetic error by arithmetically synthesizing a plurality of rotational errors of the rotational error detecting means; The means obtains a new rotation error Q times (where Q is an integer of 2 or more) as the update timing, and the Nx · L memory values are sequentially produced by the synthesis error producing means and the memory output value producing means. Update saving means for updating and saving the memory output value of the means by the updated value obtained by arithmetic synthesis, and when Nx is 1, at least one memory value is used, and when Nx is 2 or more, the update interval is the update timing. Memory output value creating means for creating the memory output value in synchronization with the update timing by using at least one set of Nx memory value groups separated by L times or more, and the rotation error detecting means for each detection timing. Of the rotation speed and the memory output value of the memory output value generating means are arithmetically combined to generate the control signal. 2. A speed control device for a motor according to claim 1, wherein L = (Zq / Q) · k (where k is an integer of 1 or more).