JPH0734667B2 - Motor speed controller - Google Patents

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor speed control device. 2. Description of the Related Art A motor speed control device that detects the rotation speed of a motor with a speed detector and controls the power supplied to the motor by the detection signal is widely used for capstan motors and cylinder motors of video tape recorders. (See, for example, Japanese Patent Application No. 56-142724 proposed by the applicant). However, in such a speed control device, only the conventionally used proportional / integral / derivative control is performed, and it is not possible to sufficiently suppress the fluctuation of the rotation speed due to the fluctuation of the load torque. This will be described below with reference to the drawings. FIG. 8 shows the configuration of a conventional motor speed control device. The rotation sensor 2 directly connected to the DC motor 1 generates an AC signal as the motor 1 rotates. The speed detector 3 produces a DC voltage corresponding to the cycle of the AC signal of the rotation sensor 2 and inputs it to the proportional compensator 9. The signal amplified by a predetermined factor by the proportional compensator 9 is input to the power amplifier 8. The power amplifier 8 power-amplifies the input signal and uses it as the power supplied to the motor, and controls the rotational speed of the load 10 by increasing or decreasing the torque generated by the motor 1. Problems to be Solved by the Invention FIG. 9 shows a control block diagram of this conventional speed control device. In FIG. 9, the value (Tm-T1) obtained by subtracting the load torque T1 from the torque Tm generated by the motor 1 becomes the net drive torque (addition point 41), and the combined inertia moment Jm of the motor 1 and the load 10 is rotationally driven. To do. Driving torque is moment of inertia
It is integrated by Jm (block 42) and converted into the rotation speed ωm of the motor 1. Incidentally, s in the block 42 is a Laplace operator. The rotation speed ωm is multiplied by Kv and detected by the rotation sensor 2 and the speed detector 3 (block 43),
By comparison with the reference signal Sref (addition point 44), an equivalent speed error e is obtained. The speed error e is converted to R by the proportional compensator 9.
It is amplified twice (block 45) and further converted into Ba times current by the power amplifier 8 (block 46), and the motor 1
Is supplied to. The motor 1 generates a torque Tm that is a torque constant Kt times the supply current of the power amplifier 8 (block 47). The transfer function from the load torque T1 to the rotation speed ωm is Becomes A Bode-gain diagram of the frequency transfer function G (jω) is shown in FIG. Within the control range below the corner frequency fc, it can be approximated as G (jω) ≈−1 / (KvRBaKt) (2). From the equation (2), if the gain R of the proportional compensator 9 is increased,
It can be seen that the fluctuation of the rotation speed ωm of the motor 1 due to the fluctuation of the load torque T1 is reduced. However, in reality, since the speed detection operations of the rotation sensor 2 and the speed detector 3 have a time delay, if the gain R of the proportional compensator 9 is too large, the control system becomes unstable. . That is, the gain R of the proportional compensator 9 has a limit. as a result,
The rotation speed of the motor 1 fluctuated greatly due to the torque fluctuation generated by the load 10. In consideration of such a point, the present invention is devised so as to greatly reduce the fluctuation of the motor rotation speed due to the fluctuation of the load torque. Means for Solving the Problems In a motor speed control device of the present invention, a rotation sensor that generates an AC signal with a cycle corresponding to the rotation speed of the motor, and a plurality of times per rotation of the motor by the AC signal of the rotation sensor. Detecting means, a compensating means for calculating and storing a control signal based on a detection signal of the speed detecting means, and a power amplifying means for supplying electric power in response to the control signal of the compensating means to the motor. The compensating means includes rotation error detecting means for obtaining a rotation error in response to a detection signal of the speed detecting means, and Nx L pieces (where L is an integer of 4 or more and Nx is a positive integer). Memory means for storing and saving memory value groups M [0] to M [NxL-1], and Nx memory values M [J-nL (mod NxL)] of the memory means.
(N = 1, ..., Nx) (where J is an integer), a memory output means for obtaining a plurality of memory output values, a second memory output value of the memory output means, and the rotation error detection means. Update storage means for updating and storing the memory value of the memory means in the order of M [0], M [1], ..., M [NxL-1] by the update value obtained by arithmetically combining the rotation error of The control signal generating means is configured to generate the control signal by arithmetically combining the first memory output value of the output means and the rotation error of the rotation error detecting means, and further, in the control signal of the control signal generating means. A ratio of a signal in the direct transmission path from the rotation error to the control signal is set to 1, and an indirect transmission path from the rotation error to the control signal via the memory means, the update storage means and the memory output means is set. If the signal ratio is D 0.25 ≦ D ≦ 0.5, the memory output means is configured to obtain at least two memory output values, and the first memory output value used in the control signal generating means is Nx memory values M [J1-nL (mod Nx L)] of the memory means
(N = 1, ..., Nx) (where J1 is an integer), and the second memory output value to be utilized in the update storage means is Nx memory values M [] of the memory means. J2-
nL (mod Nx L)] (n = 1, ..., Nx) (where J2 is an integer), and the integers J1 and J2 are calculated as J1 = J2 + Px (mo
d Nx L) (where Px is an integer of 1 or more and 5 or less), thereby solving the above problems. Operation According to the present invention, by adopting the above configuration, the frequency transfer function from load torque fluctuation to rotation speed fluctuation is 0 or extremely small at a specific frequency, and at other frequencies, it is almost the same as the conventional characteristic. I found out. That is, the influence of the fluctuation of the specific frequency of the load torque was significantly reduced, and the effect of suppressing the fluctuation of the other frequencies to the same level as the conventional one could be obtained. As a result, the combined value of rotational speed fluctuations is greatly reduced,
A high-performance motor speed controller was realized. Practical Example FIG. 2 is a block diagram showing an embodiment of the present invention. In FIG. 2, the DC motor 1 directly drives the rotation sensor 2 and the load 10 to rotate. The rotation sensor 2 is Zq times per rotation as the motor 1 rotates (Zq is an integer of 4 or more. In a capstan motor of a video tape recorder, normally, Zq = 10.
The AC signal a of 0) is generated. The AC signal a of the rotation sensor 2 is input to the speed detector 3, and a digital signal b corresponding to the cycle of the AC signal a is obtained. FIG. 3 shows a specific configuration example of the speed detector 3. The AC signal a is waveform-shaped by the waveform shaping circuit 31 to obtain the shaped signal g. The shaping signal g is input to the AND circuit 33 and the flip-flop 35. On the input side of the AND circuit 33, the clock pulse p of the oscillation circuit 32 and the counter are further provided.
34 overflow output signals w are also input. The oscillating circuit 32 is composed of a crystal oscillator and a frequency divider, etc.
(About 500kHz) is generated. The counter 34 is a 12-bit up counter that counts up the contents of the output pulse h of the AND circuit 33 each time it arrives. The overflow output signal w is "H" when the count content of the counter 34 is less than or equal to a predetermined value, and w changes to "L" when the count content of the counter 34 is greater than or equal to the predetermined value.
(Here, "H" represents a high potential state and "L" represents a low potential state). The data input type flip-flop 35 is
"H" input to the data input terminal is fetched by using the rising edge of the shaping signal g as a trigger signal, and its output Q is set to "H" (q = "H"). Further, when the reset signal r from the compensator 4 becomes “H”, the internal states of the counter 34 and the flip-flop 35 are reset (b = “LLLLLLLLLLL
L ", w =" H ", q =" L ") Next, the operation of the speed detector 3 shown in FIG. 3 will be described.
Now, it is assumed that the counter 34 and the flip-flop 35 are reset by the reset signal r. When the output signal g of the waveform shaping circuit 31 changes from “L” to “H”, the clock pulse p of the oscillation circuit 32 is output as the output signal h of the AND circuit 33.
Is output. Counting the output signal h of the counter 34,
The internal state is changed. When the output signal g of the waveform shaping circuit 31 changes from "H" to "L", the output signal h of the AND circuit 33 becomes "L", and the counter 34 holds its internal state. Further, the flip-flop 35 takes in the data “H” at the falling edge of the signal g and outputs its output signal q.
Is changed from “L” to “H”. The digital signal b of the counter 34 is a value proportional to the (half) cycle length of the AC signal a of the rotation sensor 2 and inversely proportional to the rotation speed of the motor 1. The compensator 4, which will be described later, looks at the output signal q of the flip-flop 35, inputs the digital signal b of the counter 34 when q becomes “H”, and then outputs the reset signal r to “H” for a predetermined short time. Then, the counter 34 and the flip-flop 35 are reset to the initial state to prepare for the next speed detection operation.
When the rotation speed of the motor 1 is too slow, the internal state of the counter 34 exceeds a predetermined value because the cycle of the output signal g of the waveform shaping circuit 31 is long, and the overflow output signal w
May change from "H" to "L", the output signal h of the AND circuit 33 becomes "L", and the counter 34 may hold a predetermined large value. The compensator 4 shown in FIG.
The digital signal b of the D / A converter 7 is calculated and processed by a built-in program, which will be described later, to output a control signal c. The control signal c of the compensator 4 is input to the power amplifier 8 and the power amplified drive signal d.
(Current proportional to the control signal c) is supplied to the motor 1. Therefore, the motor 1, the rotation sensor 2, the speed detector 3, the compensator 4, and the power amplifier 8 constitute a speed control system, and the rotation speed of the motor 1 is controlled to a predetermined value. The memory 6 of the compensator 4 is divided into a ROM area (ROM: read only memory) in which a predetermined program and constants are stored and a RAM area (RAM: random access memory) in which a required value is stored at any time. The computing unit 5 performs a predetermined operation or computation according to a program in the ROM area. FIG. 1 shows a concrete example of the program. Next, the operation will be described in detail. (1) First, the arithmetic unit 5 inputs the output signal q of the flip-flop 35 of the speed detector 3 and waits for the signal q to become “H”. That is, it is monitored that the speed detector 3 detects the (half) cycle of the AC signal a and outputs a new digital signal b. (2) When q becomes “H”, the digital signal b of the speed detector 3 is read, the speed detection value S (digital value) corresponding to the digital signal b is read, and the reset signal r is kept “H” for a predetermined time. Then, the counter 34 and the flip-flop 35 of the speed detector 3 are reset. (3) The speed detection value S is subtracted from the predetermined reference value S ref (E ₀ = Sref-S), and the value E ₀ is multiplied by R (E = R · E ₀ ),
The current rotation error E of the motor 1 is calculated (rotation error detection unit 1A). (4) Nx · L (where Nx is an integer greater than or equal to 1 and L
Is an integer multiple of 2 or more of Zq) and modifies the variable I each time a new speed detection value S is obtained (count unit 1B). That is, I = I + 1 (I +
After setting 1 to new I, if I = NxL, I = 0
To If such an operation is performed, I is 0 to NxL
It will be an integer between -1. The initial value of I is NxL-1. (5) The control signal value Y is calculated by adding and synthesizing the calculated value V (memory output value) by the calculated value calculation unit 1E (memory output means) described later and the current rotation error E at a predetermined ratio D: 1. (Control signal generator 1C). That is, Y = E + D · V.
Here, the ratio D is selected to be a value within the range of 0.25 ≦ D ≦ 0.5. (6) The control signal value Y is output to the D / A converter 7 and converted into a DC voltage (control voltage) corresponding to the value of Y. (7) A calculated value V (memory output value) calculated by a calculated value calculation unit 1E (memory output means), which will be described later, and a current rotation error E
An update value is calculated by adding and synthesizing at a ratio of 1: 1 and the digital value M [1] in the RAM area corresponding to the count value I of the counting means is updated (M [I] = E + V), and the next value is calculated. Store and save until update (update save section 1D). (8) With NxL being mod, an integer J obtained by adding 1 to I is calculated [J = I + 1 (mod NxL)], and Nx digital values M [J−nL (mod NxL )]
Using (n = 1, ..., Nx), the calculated value V
(Memory output value) is calculated (calculated value calculation unit 1E [memory output means]), and then the operation returns to (1). Here, the value of the ratio Wn is 0 <Wn <2 / Nx (n = 1, ..., Nx) .... (4) Shall be satisfied. Specifically, when Wn = 1 / Nx (n = 1, ..., Nx) (6), preferable characteristics are easily obtained. The calculated value V (memory output value) is a control signal after the next speed detection value S is obtained and the counting unit 1B increments the count value I (substantially equal to I and J). It is used in the creation unit 1C and the update storage unit 1D. With this structure, it becomes extremely strong against fluctuations in the load torque that generate the load 10 shown in FIG. This will be described. A control block diagram of this embodiment is shown in FIG.
The same elements as those shown in FIG. 9 are designated by the same reference numerals and symbols, and their explanations are omitted. The operation of the compensator 4 corresponds to the broken line portion 50 shown. Addition point 44 of reference value Sref and detection value S
And the rotation error E obtained by multiplying the gain R is obtained (block 45). D: calculated value V (memory output value) and rotation error E
The control signal value Y is obtained by adding and synthesizing at a ratio of 1 (addition point 5
3 and block 54). Further, the calculated value V (memory output value) and the rotation error E are added and combined at a ratio of 1: 1 to obtain an updated value, which is updated and saved as a new digital value M [I] (addition point 51). Further, since the next new calculated value V (memory output value) is calculated from the digital value group in the RAM area according to the equation (3), the relationship between the digital value M [I] and the calculated value V (memory output value) is It is represented as block 52. Here, z zexp (sTx) (...) (7) in the block 52, and Tx corresponds to one sampling period of the speed detector 3. Rotation speed ωm from load torque T1 of the control block in FIG.
The transfer function to Becomes Within the control range below the corner frequency fc, Gx (jω) ≈− {1 / (KvRBaKt)} · H (jω) ≈G (jω) · H (jω) (10). Equation (10) is the control characteristic Gx (j
ω) is equal to the conventional control characteristic G (Jω) multiplied by H (jω). FIG. 5 shows an example of the amplitude characteristic of the frequency transfer function H (jω) when Nx = 2, W1 = 0.5, W2 = 0.5. In Fig. 5, D =
For 0.5, for D = 0.25, and
The case of D = 1 is shown for comparison. Further, fr is fr = 1 / (L · Tx) ... (11), and H (jω) is a periodic function of fr. Fifth
As shown in the figure, the frequency fr, 2fr, 3fr, ...
It can be seen that the frequency transfer function is | H (jω) | = 0 at. As can be understood by comparing and with, and, when D = 0.5 () and D = 0.25 (), fr, 2fr, ...
It was found that | H (jω) | is almost equal to 1 at frequencies other than. In general, the smaller D becomes, | H (jω) | at frequencies other than fr, 2fr, ...
Is closer to 1. However, if D is too small,
It was also found that the frequency range of | H (jω) | << 1 near fr, 2fr, ... That is, there is an optimum range for the value of the ratio D, and 0.25 ≦ D ≦ as in the present embodiment.
If it is 0.5, the frequency transfer function Gx (jω) is
At frequencies fr, 2fr, 3fr, ... and their neighboring frequencies, | Gx (jω) | = 0 and | Gx (jω) | << 1, and at other frequencies, the conventional frequency transfer function G It is almost equal to (jω). As a result, a very good control characteristic Gx (jω) can be obtained, and the combined value of fluctuations in the rotation speed ωm of the motor 1 due to fluctuations in the load torque T1 can be reliably made smaller than the conventional control performance value. It has become possible. It was also found that such an effect is more easily obtained as Nx is larger. However, in order to reduce the number of memories in the RAM area while obtaining the above effect,
It can be said that Nx = 2 is preferable. If L is equal to an integer multiple of 2 or more of Zq (L
Is a value corresponding to an integer multiple of 2 or more of one rotation cycle of the motor 1), the rotation speed ω due to the fluctuation of the load torque T1.
There is an effect of greatly suppressing the fluctuation of m as a whole. next,
This will be described by taking a capstan motor of a video tape recorder as an example. Since the load of the capstan motor is a magnetic tape or a pinch roller, the load fluctuation generated by the load 10 is a component synchronized with the rotation of the motor 1 (periodic load fluctuation with one rotation of the motor 1 as a basic cycle). Besides, a load fluctuation component having a frequency lower than the rotation frequency of the motor 1 often occurs. Such load fluctuations cause fluctuations in the rotational speed of the capstan motor, causing wow and flutter of the tape speed. By the way, such load fluctuations often have a periodic fluctuation having a cycle that is an integral multiple of the cycle of one rotation of the motor 1, and the fluctuation of the rotation speed of the conventional motor 1 also has a cycle that is an integral multiple of the cycle of one rotation. It was found that many low frequency periodic fluctuations occurred. Therefore, L
If is set to a value corresponding to an integer multiple of 2 or more of one rotation cycle of the motor 1, fr becomes an integer of 2 or more of the rotation frequency fm of the motor 1, and the rotation speed of the motor 1 due to the load torque T1. It is possible to effectively reduce the low frequency fluctuation of ωm. Such an effect is obtained by increasing the gain of the proportional compensator 9 of the conventional motor speed controller shown in FIG.
It cannot be obtained by adding an integral or differential compensator after. It should be noted that the larger the value of L is, the more effective it is for load fluctuations having a long cycle, but the size of the ram region becomes large, and there is a practical limit. Usually, it is preferable to set L to 6 times the one rotation cycle of the motor from the following points. That is, since 6 has many divisors of 1,2,3,6, the fluctuation of the rotation speed due to the load fluctuation of 1,2,3,6 times the one rotation cycle of the motor 1 is completely Can be expected to suppress. FIG. 6 shows a program example of the compensator 4 in consideration of the safety of the entire control system. Here, the method of calculating the update value in the update storage unit and the calculated value calculation unit (memory output means)
The number of preparations of the calculated value (memory output value) in (3) and the way of using the calculated value of the calculated value calculation unit in the control signal generation unit are improved. Next, the operation will be described in detail (the entire configuration is the same as that in FIG. 2, and the description is omitted). (9) First, the arithmetic unit 5 inputs the output signal q of the flip-flop 35 of the speed detector 3 and waits for the signal q to become “H”. That is, it is monitored that the speed detector 3 detects the (half) cycle of the AC signal a and outputs a new digital signal b. (10) When q becomes "H", the digital signal b of the speed detector 3 is read, the speed detection value S (digital value) corresponding to the digital signal b is read, and the reset signal r is kept at "H" for a predetermined time. Then, the counter 34 and the flip-flop 35 of the speed detector 3 are reset. (11) The speed detection value S is subtracted from the predetermined reference value Sref (E ₀ = Sref-S), and the value E ₀ is multiplied by R (E = R · E ₀ ),
The current rotation error E of the motor 1 is calculated (rotation error detection unit 6A). (12) With Nx · L as the mod, the variable I is incremented each time a new speed detection value S is obtained (count unit 6B). (13) The latest calculated value V [Px] (first memory output value) calculated by the calculated value calculation unit 6E (memory output means) described later and the current rotation error E are added at a D: 1 ratio. They are combined (0.25 ≦ D ≦ 0.5) and the control signal value Y is calculated (control signal creation unit 6C). That is, Y = E + D · V [Px]. (14) The control signal value Y is output to the D / A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y. (15) Old calculated value V calculated by a calculated value calculation unit 6E (memory output means) described later

[0] (second memory output value) and the current rotation error E are added and combined at a ratio of 1: 1 to obtain an added value M ₀ (M ₀ = E + V

[0]). Mod NxL
Then, an integer K is calculated by subtracting Qf (Qf is an integer of 2 or more, and Qf = 3 is preferable) from the count variable I [K
= I-Qf (mod NxL)]. Transfer the contents of register variable X [m + 1] to X [m] in order (m = 0,1,2, ..., 2Qf
-1) Put M ₀ in X [2Qf]. That is, X [2Qf]
To X

2Qf + 1 additional values (an additional value obtained by adding and combining the calculated value and the rotation error at a ratio of 1: 1) consecutive to [0] are obtained. Next, a predetermined positive ratio Cm (m = 0,1, ...) to X [m].
, 2Qf) is added to obtain a new updated value, which is stored and saved as the digital value M [K] in the RAM area until the next update (update saving unit 6D). Where the ratio Cm
Have the following relationships: Cm = C2Qf-m (m = 0,1, ..., Qf) ……… （12） (16) NxL is mod, and an integer J is calculated by adding 1 + Px (Px is an integer of 1 or more and 5 or less, preferably Px = 3) to the count variable I [J = I + 1 + Px (mod Nx
L)]. After transferring the contents of the register variable V [m + 1] to V [m] in order (m = 0, 1, ..., Px−1), the digital value group M [J−nL (mod NxL) in the RAM area is transferred. )] (N =
1, ... ......, Nx) is used to enter the latest calculated value calculated by the following equation into V [Px] (calculated value calculation unit 6E [memory output means]). Then, the operation returns to (11). Here, the value of Wn satisfies the equations (4), (5) and (6). That is, from V = [Px]

Px + 1 calculated values (memory output values) consecutive to [0] are obtained. At this time, when V [Px] (first memory output value) is calculated, the integer J in the equation (14) is set to J1, and V

When the integer J in the equation (14) when calculating [0] (second memory output value) is J2, there is a relationship of J1 = J2 + Px. That is, V [Px] and V

There is a gap corresponding to the integer Px between [0]. As described above, after the next speed detection value S is obtained and the count value I of the counting section 6B is incremented, V [Px] is used in the control signal generating means to obtain V

[0] is used in the update storage means. As in the present embodiment, the calculation for calculating the weighted average is inserted into the update storage unit 6D, or the first calculated value (first memory) of the calculated value calculation unit 6E (memory output means) used in the control signal generation 6C. If a predetermined deviation is provided between the output value) and the second calculated value (second memory output value) of the calculated value calculation section 6E (memory output means) used in the update storage section 6D, within the control range It was confirmed that good control characteristics as described above were obtained and the operation of the entire control system was stable (satisfying the Nyquist stability condition). Especially, to ensure the stability of the control system and simplify the calculation, Qf = 3, Px = 3,
I also found that setting L> Qf + Px is good. FIG. 7 shows another program example of the compensator 4 in consideration of the stability of the entire control system. Here, the method of calculating the calculated value (memory output value) in the calculated value calculation unit (memory output means) and the number of preparations, and the method of using the calculated value of the calculated value calculation unit in the control signal generation unit are improved. There is. Next, the operation will be described in detail (the entire configuration is the same as that in FIG. 2, and the description is omitted). (17) First, the calculator 5 inputs the output signal q of the flip-flop 35 of the speed detector 3 and waits for the signal q to become “H”. That is, it is monitored that the speed detector 3 detects the (half) cycle of the AC signal a and outputs a new digital signal b. (18) When q becomes "H", the digital signal b of the speed detector 3 is read and converted into the speed detector S (digital value) corresponding to the digital signal b, and the reset signal r is kept at "H" for a predetermined time. Then, the counter 34 and the flip-flop 35 of the speed detector 3 are reset. (19) The speed detection value S is subtracted from the predetermined reference value Sref (E ₀ = Sref-S), and the value E ₀ is multiplied by R (E = R · E ₀ ),
The current rotation error E of the motor 1 is calculated (rotation error detection unit 7A). (20) The variable I is incremented each time a new speed detection value S is obtained with Nx · L as the mod (modulus) (count unit 7B). (21) The latest calculated value V [Px] (first memory output value) calculated by the calculated value calculation unit 7E (memory output means) described later and the current rotation error E are added at a D: 1 ratio. They are combined (0.25 ≦ D ≦ 0.5) and the control signal value Y is calculated (control signal creation unit 7C). That is, Y = E + D · V [Px]. (22) The control signal value Y is output to the D / A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y. (23) Old calculated value V calculated by the calculated value calculation unit 7E (memory output means) described later.

[0] (second memory output value) and the current rotation error E are added and combined at a ratio of 1: 1 to calculate an updated value, and a digital value in the ram area corresponding to the count value I of the counting means. Update M [I] (M
[I] = E + V

[0]), and stores and saves until the next update (update saver 7D). (24) 1 + Px + Qf for count variable I with NxL as mod
(Px is an integer greater than or equal to 1 and less than or equal to 5 and Qf is an integer greater than or equal to 2) to calculate an integer J [J = I + 1 + Px + Qx
(Mod NxL)]. The contents of the register variable X [m + 1] are X
Transfer to [m] in order (m = 0,1,2, ..., 2Qf-1),
Nx digital value group M [J−nL (mod Nx
L] (n = 1, ..., Nx) is calculated by the following formula, and the added value is put in X [2Qf]. Here, the value of Wn satisfies the equations (4), (15) and (6). That is, from X [2Qf] to X

2Qf + 1 addition values (addition values obtained from Mx digital values) consecutive to [0] are obtained. Next, register variable V [m +
After the contents of 1] are sequentially transferred to V [m] (m = 0, 1,
, Px-1), X [m] (m = 0,1, ..., 2Qf) is added and synthesized to obtain the latest calculated value and put it in V [Px] (calculated value calculation Part 7E [memory output means]). That is,
From V [Px] to V

Px + 1 calculated values consecutive to [0] are obtained. Here, the ratio Cm has a relationship of equations (12) and (13). Then, the operation returns to (21). At this time, the integer J in the equation (15) when calculating V [Px] (first memory output value) is substantially J1,

When the integer J in the equation (15) when calculating [0] (second memory output value) is J2, there is a relationship of J1 = J2 + Px. That is, V [Px] and V

A gap corresponding to the integer Px exists between [0]. As described above, V [Px] (first memory output value) is used in the control signal generating unit 7C after the new speed detection value S is obtained and the count value I of the counting unit 7B is incremented.

[0] (second memory output value) is used in the update storage unit 7D. As in the present embodiment, the calculated value calculation unit 7E is inserted with the calculation for taking the weighted average and the calculation for preparing a plurality of calculated values, and the calculated value calculation unit 7E (memory output means) used in the control signal generation unit 7C is used. Between the first calculated value (first memory output value) and the second calculated value (second memory output value) of the calculated value calculation unit 7E (memory output means) used in the update storage unit 7D. If such a deviation is provided, good control characteristics as described above can be obtained, and the operation of the entire control system becomes cheaper (the Nyquist stability condition is satisfied). In this case, too, to ensure the stability of the control system and simplify the calculation, Qf
＝ 3, Px ＝ 3, L ＞ Qf ＋ Px. It is needless to say that the calculation by the ratios Wn and Cm is not limited to the above-mentioned form, but may be any one that realizes the contents of the above-mentioned program, and various equivalent formula modifications are possible. Also, when a new rotation error is obtained,
First, if the control signal generation unit performs a new control signal output operation, and then the calculated value calculation unit (memory output unit) calculates the calculated value to be used at the next sampling time, the calculated value calculation is performed. Since it is possible to lengthen the calculation time of the part and shorten the time delay until the output of the control signal, it is easy to ensure the stability of the control system. In each of the above-described embodiments, the speed detector detects only the rotation speed of the motor, but in addition to this, the rotation phase of the motor is detected by a well-known phase detector, and both are combined to generate a rotation error. Needless to say, it is included in the present invention. Further, the output of the compensator may be a digital signal or a PWM signal (pulse width modulation signal), or the output signal of the power amplifier may be a PWM signal. A brushless DC motor may be used as the motor. Further, the compensator may be configured with complete hardware so that the compensator can perform the same operation as the above program. Besides, various modifications can be made without changing the gist of the present invention. Effects of the Invention The motor speed control device of the present invention has extremely good control characteristics at a specific frequency, and is substantially the same as the conventional control characteristics at other frequencies as well. The fluctuation of the rotation speed due to the fluctuation is significantly reduced. Therefore, if the capstan motor of the video tape recorder is constructed based on the present invention, the running speed of the magnetic tape can be controlled extremely accurately and a high performance video tape recorder with less wow and flutter can be obtained.

[Brief description of drawings]

FIG. 1 is a flow chart showing an example of a built-in program of the compensator shown in FIG. 2, FIG. 2 is a block diagram showing the entire constitution of an embodiment of the present invention, and FIG. 3 is a diagram showing the speed detector shown in FIG. FIG. 4 is a block diagram showing a control block of an embodiment of the present invention, and FIG. 5 is a frequency transfer function | H (jω).
6 is a characteristic diagram showing a characteristic example of |, FIG. 6 is a flowchart showing another example of a built-in program of the compensator of the present invention, and FIG. 7 is a flowchart showing another example of a built-in program of the compensator of the present invention. FIG. 8 is a diagram showing a configuration of a conventional example, FIG. 9 is a block diagram showing a control block of the conventional example, and FIG. 10 is a control characteristic | G of the conventional example.
It is a characteristic view showing (jω) |. 1 ... motor, 2 ... rotation sensor, 3 ... speed detector,
4 ... Compensator, 5 ... Calculator, 6 ... Memory, 7 ... D /
A converter, 8 ... power amplifier, 10 ... load.

Claims (1)

[Claims] 1. A rotation sensor for generating an AC signal having a cycle in response to a rotation speed of a motor, speed detection means for detecting a plurality of times per rotation of the motor by the AC signal of the rotation sensor, and the speed detection means. Compensation means for calculating / storing a control signal based on the detection signal of (1) and power amplification means for supplying electric power in response to the control signal of the compensation means to the motor, wherein the compensation means is the speed detection means. Error detection means for obtaining a rotation error in response to the detection signal of N, and Nx L memory value groups M (where L is an integer of 4 or more and Nx is a positive integer).
Memory means for storing and saving [0] to M [Nx L-1], and Nx memory values M [J-nL (mod
Nx L)] (n = 1, ..., Nx) (where J is an integer), and a memory output means for obtaining a plurality of memory output values; a second memory output value of the memory output means; The memory value of the memory means is M [0], M [1], ..., M [Nx L by the updated value obtained by arithmetically combining the rotation error of the rotation error detecting means.
-1] in order of updating and storing, and a control signal generating means for generating the control signal by arithmetically combining the first memory output value of the memory output means and the rotation error of the rotation error detecting means. Further, the ratio of the signal in the direct transmission path from the rotation error in the control signal of the control signal generating means to the control signal is 1, and the memory means, the update storage means and the memory output means When the ratio of the signal in the indirect transmission path from the rotation error via the control signal to the control signal is D, 0.25 ≦ D ≦ 0.5, and the memory output means obtains at least two memory output values. And the first memory output value used in the control signal generating means is Nx memory values M [J1-nL (mod Nx
L)] (n = 1, ..., Nx) (where J1 is an integer), and the second memory output value to be used in the update storing means is Nx pieces of the memory means. Memory value M
[J2-nL (mod Nx L)] (n = 1, ..., Nx) (where J2 is an integer), and the integers J1 and J2 are J1 =
A motor speed control device characterized by having a configuration of J2 + Px (mod Nx L) (where Px is an integer of 1 or more and 5 or less).