JPH0681534B2 - Motor speed controller - Google Patents

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor speed control device. 2. Description of the Related Art A motor speed control device that detects the rotation speed of a motor with a speed detector and controls the power supplied to the motor based on the detection signal is widely used in capstan mochiers and cylinder motors of video tape recorders. (See, for example, Japanese Patent Application No. 56-142724 proposed by the applicant). However, in such a speed control device, only the conventionally used proportional / integral / derivative control is performed, and the fluctuation of the rotation speed due to the fluctuation of the load torque cannot be sufficiently suppressed. In order to solve such a problem, the present applicant has filed Japanese Patent Application No.
-229143 (not known) and Japanese Patent Application No. 60-229144 (not known) proposed a high-performance motor speed control device that is extremely resistant to load torque fluctuations. That is, in Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-229144, a rotation sensor that generates an AC signal with a cycle corresponding to the rotation speed of the motor and a plurality of rotation sensors per rotation of the motor by the AC signal of the rotation sensor. Speed detecting means for detecting, compensating means for calculating and storing a control signal based on the detection signal of the speed detecting means, and power amplifying means for supplying electric power according to the control signal of the compensating means to the motor. The (driving means) constitutes a speed control system. Further, a rotation error detecting means for obtaining a rotation error in response to the detection signal of the speed detecting means, and NxL
Memory value groups M [O] to M (NxL-1)
A memory value storing means, a composite value calculation means (memory output value creation means) for substantially calculating a composite value calculated by using Nx memory value groups separated by L intervals of the memory means, and Update value storage means for updating and storing the memory values of the memory means substantially in order by the update value corresponding to the combined value of the value calculation means and the rotation error of the rotation error detection means, and the combination of the combined value calculation means A high-performance motor speed control device is realized by using a compensating means having a control signal generating means for generating a control signal by arithmetically combining the value and the rotation error of the rotation error detecting means. Problems to be Solved by the Invention However, in Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-229144, it is indispensable to use a large number of digital memories, and normally 16 bits × 1000 words = 16 kbits Memory is needed. Although IC devices for memories have been rapidly reduced in price due to recent improvements in semiconductor manufacturing technology, it is not preferable to use a memory of 16 kbits because the cost is significantly increased. Further, there is a considerable amount of calculation in the operation of the compensating unit including the combined value calculating unit (memory output value creating unit) and the update storing unit, and in order to finish the predetermined calculation within the detection period of the speed detector, It was necessary to perform high-speed calculation using an expensive high-speed multiplier or the like. That is, there are considerable restrictions on the configuration and operating speed of the hardware that implements the compensation means. In consideration of such a point, the present invention significantly reduces the number of memories required in the speed control device for a motor that uses many memories as shown in the above example, and relaxes the constraint on the calculation time. It was devised as follows. Means for Solving the Problems In the motor speed control device of the present invention, a rotation sensor that generates an AC signal with a cycle corresponding to the rotation speed of the motor, and Zq per rotation of the motor by the AC signal of the rotation sensor.
The speed detecting means for detecting the number of times (where Zq is an integer of 8 or more), the compensating means for generating a control signal based on the detection signal of the speed detecting means, and the motor according to the control signal of the compensating means. The compensating means comprises driving means for driving, and the compensating means, at each detection timing at which the speed detecting means obtains a new detection signal, a rotation error detecting means for obtaining a new rotation error based on the detection signal, and Nx · L ( Here, Nx is an integer of 1 or more, and L is an integer of 4 or more). Memory means for storing and storing ordered memory values, and a synthetic error obtained by arithmetically synthesizing a plurality of rotational errors of the rotational error detecting means are created. The update timing is the timing at which the combined error creating means and the rotation error detecting means obtain a new rotation error Q times (where Q is an integer of 2 or more) as the update timing.
Update storage means for updating and storing L memory values in order by the update value obtained by arithmetically combining the composite error of the composite error creating means and the memory output value of the memory output value creating means, and Nx is 1.
If at least one memory value is used, and if Nx is 2 or more, at least one set of Nx memory value groups whose update interval is L times or more of the update timing is used as the update timing. The memory output value creating means for creating the memory output value in synchronization with each other, the rotation error of the rotation error detecting means and the memory output value of the memory output value creating means are arithmetically combined for each detection timing to generate the control signal. A control signal generating means for generating, a calculating means for executing the operation of at least the synthetic error generating means, the memory output value generating means and the update storing means according to a program, and the rotation error detecting means includes a new rotation error. The control signal generating means generates a new control signal each time the rotation error detecting means obtains a new rotation error Q times, and the composite error is generated. The generating means, the memory output value generating means and the update storing means update one memory value, and the update operation by the synthetic error generating means, the memory output value generating means and the update storing means is Q or less. The above problem is solved by dividing the partial operation into a plurality of partial operations and executing each of the partial operations by the calculating means at different timings of the rotation error detecting means. Action In the present invention, by using the above-mentioned structure, Japanese Patent Application No.
As described in Japanese Patent Application No. 229143 and Japanese Patent Application No. 60-229144, it is possible to significantly reduce the influence of load torque fluctuation at a specific frequency. Moreover, an economically high-performance motor speed control device is realized by using a small number (1 / Q) of the number of memories. In addition, since a composite error that combines a plurality of rotation errors of the rotation error detecting means is created by the composite error creating means, the composite error and the memory output value are arithmetically combined, and the memory value is updated and saved. It is possible to prevent the operation of the control system from becoming unstable due to the included unnecessary noise component.
Further, the updating operation of one memory value by the composite error creating means, the memory output value creating means, and the update saving means is divided into a plurality of partial operations of Q or less, and each partial operation is performed at different timings of the rotation error detecting means. Since the calculation is performed by the calculation means, the calculation amount of the calculation means that is processed within the detection timing is significantly reduced. Embodiment Hereinafter, a compensator according to an embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing an embodiment of the present invention. In FIG. 2, the DC motor 1 directly drives the rotation sensor 2 and the load 10 to rotate. The rotation sensor 2 generates an AC signal a Z times per rotation (Zq is an integer of 2 or more, which is usually Zq = 357 in a capstan motor of a video tape recorder) per rotation as the motor 1 rotates. The AC signal a of the rotation sensor 2 is input to the speed detector 3, and a digital signal b corresponding to the cycle of the AC signal a is obtained. FIG. 3 shows a specific configuration example of the speed detector 3. The AC signal a is waveform-shaped by the waveform shaping circuit 31 to obtain the shaped signal g. The shaping signal g is input to the AND circuit 33 and the flip-flop 35. On the input side of the AND circuit 33, the clock pulse p of the oscillation circuit 32 and the counter are further provided.
34 overflow output signals w are also input. The oscillation circuit 32 is composed of a crystal oscillator, a frequency divider, etc., and has a clock pulse p of a frequency considerably higher than the frequency of the shaping signal g.
(About 500kHz) is generated. The counter 34 is a 12-bit up counter that counts up the contents of the output pulse h of the AND circuit 33 each time it arrives. The overflow output signal w is "H" when the count content of the counter 34 is less than or equal to a predetermined value, and w changes to "L" when the count content of the counter 34 is greater than or equal to the predetermined value (here, "H"). Represents a high potential state, "L" represents a low potential state). The data input flip-flop 35 takes in "H" input to the data input terminal with the falling edge of the shaping signal g as a trigger signal, and outputs its output Q to "H".
(Q = “H”). Further, when the reset signal r from the compensator 4 becomes “H”, the counter 34 and the flip-flop 35.
The internal state of is reset (b = "LLLLLLLLLLLL",
w = “H”, q = “L”). Next, the operation of the speed detector 3 shown in FIG. 3 will be described.
Now, it is assumed that the counter 34 and the flip-flop 35 are reset by the reset signal r. When the output signal g of the waveform shaping circuit 31 changes from “L” to “H”, the clock pulse p of the oscillation circuit 32 is output as the output signal h of the AND circuit 33.
Is output. The counter 34 counts the output signal h,
The internal state is changed. When the output signal g of the waveform shaping circuit 31 changes from "H" to "L", the output signal h of the AND circuit 33 becomes "L", and the counter 34 holds its internal state. Further, the flip-flop 35 takes in the data "H" at the falling edge of the signal g and changes its output signal q from "L" to "H". The digital signal b of the counter 34 is a value proportional to the (half) cycle length of the AC signal a of the rotation sensor 2 and inversely proportional to the rotation speed of the motor 1. The compensator 4, which will be described later, looks at the output signal q of the flip-flop 35, inputs the digital signal b of the counter 34 when q becomes “H”, and then outputs the reset signal r to “H” for a predetermined short time. Then, the counter 34 and the flip-flop 35 are reset to the initial state to prepare for the next speed detection operation. When the rotation speed of the motor 1 is too slow,
Since the cycle of the output signal g of the waveform shaping circuit 31 is long, the internal state of the counter 34 becomes a predetermined value or more, the overflow output signal w changes from "H" to "L", and the output signal h of the AND circuit 33 changes to " In some cases, the counter 34 becomes L "and the counter 34 holds a predetermined large value. The compensator 4 of FIG. 2 is composed of a computing unit 5, a memory 6 and a D / A converter 7, and a digital signal b of the speed detector 3 is obtained.
Is calculated and processed by a built-in program described later, and a control signal c is output. The control signal c of the compensator 4 is input to the power amplifier 8 (driving means), and the power amplified drive signal d.
(Current proportional to the control signal c) is supplied to the motor 1. Therefore, the motor 1, the rotation sensor 2, the speed detector 3, the compensator 4, and the power amplifier 8 (driving means) constitute a speed control system, and the rotation speed of the motor 1 is controlled to a predetermined value. The memory 6 of the compensator 4 is divided into a ROM area (ROM: read only memory) in which a predetermined program and constants are stored and a RAM area (RAM: random access memory) in which a required value is stored at any time. The computing unit 5 performs a predetermined operation or computation according to a program in the ROM area. FIG. 1 shows a concrete example of the program. Next, the operation will be described in detail. (1) <Rotation error detecting means 1A> First, the arithmetic unit 5 inputs the output signal q of the flip-flop 35 of the speed detector 3 and waits for the signal q to become “H”. That is, it is monitored that the speed detector 3 detects the (half) cycle of the AC signal a and outputs a new digital signal b. When q becomes "H", the digital signal b of the speed detector 3 is read, the speed detection value S (digital value) corresponding to the digital signal b is read, and the reset signal r is set to "H" for a predetermined time to set the speed. Counter 34 of detector 3
And reset the flip-flop 35. Predetermined reference value Sr
The speed detection value S is subtracted from ef, and the value is multiplied by R (here,
R is a predetermined positive constant), and the current rotation error E of the motor 1 is calculated [E = R. (Sref-S)]. (2) <Control signal creating means 1B> The memory output value VO by the memo output value creating means, which will be described later, and the rotation error E at the present time are set to a predetermined ratio D: 1 (where D is 0 <
The control signal value Y is calculated (Y = E + DVO) with a constant of D ≦ 1, preferably D = 1). The control signal value Y is output to the D / A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y. (3) <Save 1C of rotation error time series> Memory value F [I [I] corresponding to a first count variable I1 described later.
The current rotation error E is stored and saved in [1] (F [I
1] = E). (4) <First Counting Means 1D> Q (generally, Q is an integer of 2 or more. Here, Q is an integer of 3 or more) is set as a mod (modulus) and a new speed detection value S is obtained. Then, the first count variable I1 is incremented. That is, after setting I1 = I1 + 1 (I1 + 1 is newly set to I1), if I1 = Q, I1 is reset to 0. If such an operation is performed, I1 is 0 to Q-
It will be an integer between 1. The initial value of I1 is 0. I1
If 0 is 0, the operations (5) and (6) are executed, if I1 is 1, the operation (7) is executed, and if I1 is 2, the operation (8) is executed and I1 is 0,1. If not, 2, the operation returns to (1). (5) <Second counting means 1E> Nx.L (generally, Nx is an integer, L is an integer of 4 or more. However, Nx is an integer of 2 or more, and L is an integer multiple of 2 or more of (Zq / Q). Since such a case is preferable, an explanation will be given of such a case hereinafter) as mod (modulus), every time the first count variable I1 becomes 0 (every Q new speed detection values S are obtained). ) Counting up the second count variable I2. That is, after setting I2 = I2 + 1, I2 is reset to 0 if I2 = NxL. If such an operation is performed, I2 will be an integer between 0 and NxL-1. The initial value of I2 is NxL-1. (6) <Memory output value creating means 1F> The integer J is made equal to I2 (J = I2), and Nx memory value groups M [J-nL (mod NxL)] (L interval apart in the RAM area) ( n = 1, ..., Nx) is used to generate the memory output value VO by the following equation. Here, the value of the ratio Wn is 0 <Wn <2 / Nx (n = 1, ..., Nx) (5), and Is standardized. Specifically, if Wn = 1 / Nx (n = 1, ..., Nx) (7) in the case of Nx ≧ 2, the equation (4) is expressed by the memory value group M [J−nL (mod Nx
L)] (n = 1, ..., Nx) is simply added and synthesized, and then Nx
It will be divided by (integer), which makes the calculation very simple.
After that, the operation returns to (1). (7) <Synthesis error creating means 1G> By the saving operation of the rotation error time series described above, F [m] (m
= 0,1, ..., Q-1) stores Q consecutive rotation errors. Fd in this (where Fd is 2 or more and Q
The latest rotation error F [Q-m] (m = 1,2,
......, Fd) to a predetermined ratio Bm (m = 1,2, ..., Fd)
The value multiplied by is added and combined to create a combined error Eg. That is, Here, the coefficient Bm has a relationship of Bm = BFd-m + 1 (m = 1,2, ..., Fd) (2). further, Have been standardized. After that, the operation returns to (1). (8) <Update / storing means 1H> Memory output value V0 and synthesis error by the memory output value creating means
Eg is calculated and combined at a ratio of 1: 1 to calculate the updated value, and the second
Memory value M in the RAM area corresponding to the count variable I2 of
[I2] is updated (M [I2] = Eg + VO), and stored and saved until the next update. After that, the operation returns to (1). With such a configuration, it is extremely strong against a specific frequency component of the load torque fluctuation caused by the load 10 in FIG. 2 that the patent of the prior application (Japanese Patent Application No. 60-229143, 60-229144).
Is the same as. Furthermore, as shown in the present embodiment, each time the speed detector 3 obtains a new detection signal, the control signal generating means 1B
Causes a new control signal to be generated, and the update storage means 1H updates one memory value each time the speed detector 3 obtains Q new detection signals, thereby substantially rewriting the memory means. The number of required memories was reduced to 1 / Q. That is, even if the number of memories is significantly reduced in this way, the effect of being extremely strong with respect to the specific frequency component of the load torque fluctuation (the effect of causing no rotation speed fluctuation) can be secured. It can be seen that when the value of L is increased, the frequency component improved by the compensator described above becomes considerably lower than the detection frequency of the speed detector, and a composite error Eg is created from a plurality of rotation errors E, Since the memory value is updated and saved by using this synthetic error Eg, the stability of the control system and the above-described improvement effect are not adversely affected even if the update frequency of the update saving means 1H is reduced to 1 / Q. It is because it was possible to do so. Further, as shown in the present embodiment, when the continuous Fd rotation errors are combined to obtain the combined error Eg, and the memory value M [I2] is updated by the combined value of the combined error Eg and the memory output value Vo, It has been found that the operation of the control system can be prevented from becoming unstable by an unnecessary noise component included in the rotation error E. This is because the synthetic error creating means 1G prevents the influence of a considerably high frequency fluctuation included in the rotation error E from entering the memory value of the update saving means 1H and the memory output value of the memory output value creating means 1F. Because you can get it. Further, a series of operations by the memory output value creating means 1F, the composite error creating means 1G, and the update saving means 1H for updating and saving one memory value is divided into a plurality of partial operations of Q or less, and the speed detector 3 Since each partial operation is performed at different timing with respect to the detection signal of
The amount of computation required within the detection cycle is significantly reduced. Further, the operation of the memory output value creating means 1F is set to I1 = 0.
At this time, the memory output value Vo used in the control signal generating means 1B is changed without delay. In addition,
The operation of the memory output value creating means 1F and the operation of the update saving means 1H may be performed at the same timing, and in such a case, it is possible to realize with Q = 2. Further, if L = (Zq / Q) · k (where k is an integer), the rotational speed fluctuation due to the load torque fluctuation of a cycle of k times (an integer times) one rotation cycle of the motor 1 is significantly increased. It has a suppressing effect. Such an effect is very preferable in the case of a capstan motor of a video tape recorder. This will be described. Since the load of the capstan motor is a magnetic tape or a pinch roller, the load fluctuation generated by the load 10 is a component synchronized with the rotation of the motor 1 (periodic load fluctuation with one rotation of the motor 1 as a basic cycle). Besides, a load fluctuation component having a frequency lower than the rotation frequency of the motor 1 often occurs. Such load fluctuations cause fluctuations in the rotational speed of the capstan motor, causing wow and flutter of the tape speed. By the way, it has been found that such load fluctuations often have periodic fluctuations having a cycle that is an integral multiple of the cycle of one rotation of the motor 1. Therefore, due to the above-mentioned effect, a considerably low frequency fluctuation of the rotation speed of the motor 1 due to the load torque fluctuation can be effectively reduced. It should be pointed out that Q is not limited to a divisor of Zq (for example, if Q = k, Q becomes irrelevant to Zq). FIG. 4 shows a program sequence of the compensator 4 in consideration of the stability of the entire control system. Here, the method of calculating the update value in the update storing means, the number of preparations of the memory output value in the memory output value creating means, and the method of using the memory output value in the memory output value creating means in the control signal creating means are improved. is doing. Next, the operation will be described in detail (the entire configuration is the same as that in FIG. 2, and the description is omitted). (11) <Rotation error detecting means 4A> First, the arithmetic unit 5 inputs the output signal q of the flip-flop 35 of the speed detector 3 and waits for the signal q to become "H". That is, it is monitored that the speed detector 3 detects the (half) cycle of the AC signal a and outputs a new digital signal b. When q becomes "H", the digital signal b of the speed detector 3 is read, the speed detection value S (digital value) corresponding to the digital signal b is read, and the reset signal r is set to "H" for a predetermined time to set the speed. Counter 34 of detector 3
And reset the flip-flop 35. Predetermined reference value Sr
The speed detection value S is subtracted from ef, and the value is multiplied by R (here,
R is a predetermined positive constant), and the current rotation error E of the motor 1 is calculated [E = R. (Sref-S)]. (12) <Control signal creating means 4B> The memory output value VO by the memory output value creating means to be described later and the current rotation error E are arithmetically combined at a predetermined ratio D: 1,
The control signal value Y is calculated (Y = E + D · Vo). The control signal value Y is output to the D / A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y. (13) <Saving of rotation error time series 4C> Memory value F [I] corresponding to a first count variable I1 described later.
The current rotation error E is stored and saved in [1] (F [I
1] = E). (14) <First Counting Means 4D> With Q as a mod, the first count variable I1 is incremented each time a new speed detection value S is obtained. I1 is
When it becomes equal to Qa (here, Qa is an integer smaller than Q), the memory output value Vo is changed to V [Px] described later, and when I1 is not equal to Qa, such a changing operation is not performed. As a result, Vo = V [Px-1] (described later) in the range of I1 <Qa, and Vo = V [Px] in the range of I1 ≧ Qa. Further, if I1 is 0, the operations of (15) and (16) are executed, and I1
If is 1, the operation of (17) is executed, and if I1 is 2, (18)
The operation of (1) is executed, and if I1 is not 0, 1 or 2, the operation of (11) is restored. (15) <Second Counting Means 4E> When Nx · L is mod (modulus), the first count variable I1 is 0.
Every 2 times (every Q new speed detection values S are obtained)
The count variable I2 of is incremented. (16) <Memory output value creating means 4F> After transferring the contents of the register variable V [m + 1] to V [m] in order (m = 0, 1, ..., Px−1), NxL is set as mod An integer J is calculated by adding Px (where Px is an integer of 1 or more and 3 or less, preferably Px = 1) to the count variable I2 of 2 [J = I2 + Px (mod NxL)]. The latest memory output value calculated by the following equation using the memory value group M [J−nL (modNxL)] (n = 1, ..., Nx) in the RAM area is input to V [Px]. Here, the value of Wn satisfies the equations (5), (6) and (7). That is, a group of Px + 1 memory output values consecutive from V [Px] to V [O] is obtained. At this time, V [P
Let x be the integer J in equation (8) when calculating
Assuming that the integer J in the formula (8) when calculating [O] is J2, there is a relationship of J1 = J2 + Px. Next, the memory output value VO used first in the control signal generating means is set to V [Px−
1] (VO = V [Px-1]). Then, the operation returns to (11). (17) <Synthesis error creating means 4G> F [m] (m
= 0,1, ..., Q-1) stores Q consecutive rotation errors. Fd latest rotation error F (Q-
m] (m = 1,2, ... Fd) to a predetermined ratio Bm (m =
1,2, ..., Fd) are added and combined, and the combined error Eg
[Formulas (1), (2), and (3)]. After that,
Return to the operation of (11). (18) <Update storing means 4H> After transferring the contents of the register variable X [m + 1] to X [m] in order (m = 0,1,2, ..., 2Kd-1), X [2Kd]
(Where Kd is an integer, preferably Kd = 3), the old memory output value V created by the memory output value creating means

A composite value obtained by arithmetically combining [0] and the composite error Eg at a ratio of 1: 1 is entered (X [2Kd] = Eg + V [O]). That is, 2Kd + 1 additional values (memory output value and combined error addition value) consecutive from X [2Kd] to X [O] are obtained. NxL to m
The integer K obtained by subtracting Kd from the second count variable I2 is calculated as od [K = I2-Kd (mod NxL)]. Next, X [m]
To a new positive value Cm (m = 0,1, ..., 2Kd) to obtain a new updated value, which is used as the memory value M [K] in the RAM area until the next update. Store and save. That is, And Here, the ratio Cm has the following relationship. Then, the operation returns to (11). As in the present embodiment, the calculation for taking the weighted average is inserted into the update storage means 4H, or the first memory output value VO (V of the memory output value creating means 4F used in the control signal creating means 4B is used.
[Px]) and the second memory output value V [O] of the memory output value creation means 4F used in the update storage means 4H, a predetermined deviation (V [Px] is ahead of V [O]. It was confirmed that the operation of the entire control system would be stable if () was provided. In particular, the values of Px and Qa related to the usage timing are deeply related to the number of operation terms Fd of the composite error creating unit 4G, and (QPx
It was also found that it is better to make −Qa) ≧ (Q + Fd) / 2. This is because the use timing of the control signal producing means 4B is detected by the speed detector 3 as compared with the use timing of the update storing means 4H of the same memory output value (for example, V [O]) of the memory output value producing means 4F. When converted to a circuit, it means (Q + Fd) / 2 or more times faster. Further, as shown in this embodiment, the memory output value creating means 4F
If the operation of the composite error creation means 4G and the update storage means 4H includes a large number of transfers and multiplications, the memory output value creation means 4F and the composite error creation means for updating and saving one memory value. By dividing a series of operations by 4G and the update storage means 4H into a plurality of partial operations of Q or less, and making each partial operation at different timings of the rotation error detection means 4A, within one detection cycle of the speed detector 3. The amount of calculation required for is significantly reduced, and the limitation on the calculation speed is considerably relaxed. As a result, the arithmetic unit 5 can be realized by a general-purpose microcomputer having a low arithmetic speed. FIG. 5 shows another program example of the compensator 4 in consideration of the stability of the entire control system. Here, the method of calculating the memory output value in the memory output value creating means and the number of preparations, and the way of using the memory output value of the memory output value creating means in the control signal creating means are improved. Next, the operation will be described in detail (the entire configuration is the same as that in FIG. 2, and the description is omitted). (21) <Rotation error detecting means 5A> First, the arithmetic unit 5 inputs the output signal q of the flip-flop 35 of the speed detector 3 and waits until the signal q becomes "H". That is, it is monitored that the speed detector 3 detects the (half) cycle of the AC signal a and outputs a new digital signal b. When q becomes "H", the digital signal b of the speed detector 3 is read, the speed detection value S (digital value) corresponding to the digital signal b is read, and the reset signal r is set to "H" for a predetermined time to set the speed. Counter 34 of detector 3
And reset the flip-flop 35. Predetermined reference value Sr
The speed detection value S is subtracted from ef, and the value is multiplied by R (here,
R is a predetermined positive constant), and the current rotation error E of the motor 1 is calculated [E = R. (Sref-S)]. (22) <Control signal creating means 5B> The memory output value VO by the memory output value creating means to be described later and the current rotation error E are arithmetically combined at a predetermined ratio D: 1,
The control signal value Y is calculated (Y = E + D.VO). The control signal value Y is output to the D / A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y. (23) <Saving 5C of rotation error time series> Memory value F [I1] corresponding to the first count variable I1 described later.
The current rotation error E is stored and stored in (F [I1] =
E). (24) <First Counting Means 5D> With Q as a mod, the first count variable I1 is incremented each time a new speed detection value S is obtained. I1 is
When it becomes equal to Qa (here, Qa is an integer smaller than Q), the memory output value VO is changed to V [Px] described later, and when I1 is not equal to Qa, such a changing operation is not performed. As a result, VO = V [Px−1] (described later) in the range of I1 <Qa, and VO = V [Px] in the range of I1 ≧ Qa. Further, if I1 is 0, the operations of (25) and (26) are executed, and I1
If is 1, the operation of (27) is executed, and if I1 is 2, (28)
The operation of (1) is executed, and if I1 is not 0, 1, 2 the operation returns to (21). (25) <Second Counting Means 5E> The first count variable I1 is 0 when Nx.L is mod.
Every 2 times (every Q new speed detection values S are obtained)
The count variable I2 of is incremented. (26) <Memory output value creation means 5F> After transferring the contents of the register variable X [m + 1] to X [m] in order (m = 0,1,2, ..., 2Kd-1), NxL is mod. Then, an integer J is calculated by adding Px + Kd (Px is an integer of 1 or more and 3 or less and Kd is an integer of 1 or more) to the second count variable I2 [J = I2 + Px + Qx (mod NxL)]. N in the ram region
x memory value group M [J−nL (mod NxL)] (n = 1, ...
, Nx) and the calculated value calculated by the following equation is X [2K
d]. Here, the value of Wn satisfies the equations (5), (6) and (7). That is, 2Kd + 1 calculated values (calculated values obtained from Nx memory values separated by L intervals) consecutive from X [2Kd] to X [O] are obtained. Next, after sequentially transferring the contents of the register variable V [m + 1] to V [m] (m = 0,1, ..., Px−1), X [m] (m = 0,1, ... , 2K
The latest memory output value obtained by adding and combining the value obtained by multiplying d) by a predetermined positive ratio Cm (m = 0,1, ..., 2Kd) is obtained, and V [Px]
Put in. Here, the ratio Cm has a relationship of equations (10) and (11). That is, Px + 1 memory output values consecutive from V [Px] to V [O] are obtained. At this time, the integer J in the equation (12) when substantially calculating V [Px] is J1, and V is substantially
When the integer J in the equation (12) when calculating [O] is J2, there is a relationship of J1 = J2 + Px. That is, V [Px] and V
There is a gap corresponding to the integer Px between [O]. Next, the memory output value VO is set to V [Px−1] (VO = V [Px−
1]). Then, the operation returns to (21). (27) <Synthesis error creating means 5G> F [m] (m
= 0,1, ..., Q-1) stores Q consecutive rotation errors. The latest Fd rotation errors F [Q-
m] (m = 1,2, ..., Fd) to a predetermined ratio Bm (m
= 1,2, ..., Fd) is added and combined, and the combined error E
Create g [Equations (1), (2), (3)]. Then, the operation returns to (21). (28) <Update storing means 5H> The old memory output value V [O] created by the memory output value creating means and the composition error Eg are arithmetically combined at a ratio of 1: 1 to calculate the updated value, and the second value is calculated. Memory value M [I2] in the ram area corresponding to the count variable I2 of (M [I2] = Eg +
V [O]), stored and saved until the next update. After that,
Return to the operation of (21). As in the present embodiment, the calculation of weighted average and the calculation of preparing a plurality of memory output values are inserted in the memory output value creating means 5F, and the memory output value creating means 5F used in the control signal creating means 5B One memory output value Vo [V [Px])
And a predetermined deviation (V (Px) is ahead of V [O]) between the second memory output value V [O] of the memory output value creating means 5F used in the update storage means 5H. If this is done, the operation of the entire control system will be stable.
It is better to make x−Qa) ≧ (Q + Fd) / 2. The calculation by the ratio Wn and Cm is not limited to the above-mentioned form, and it is needless to say that various equivalent formula modifications are possible as long as they substantially realize the contents of the above-mentioned program. Yes. Also, when a new rotation error is obtained, the control signal creating means first outputs a new control signal, and then the memory output value creating means calculates the memory output value to be used at the next sampling time. In this case, the calculation time of the memory output value creating means can be lengthened and the time delay until the output of the control signal can be shortened, so that the stability of the control system can be easily ensured. In each of the above-described embodiments, the speed detector detects only the rotation speed of the motor, but in addition to this, the rotation phase of the motor is detected by a well-known phase detector, and both are combined to generate a rotation error. Needless to say, it is included in the present invention. Further, the output of the compensator may be a digital signal or a PWM signal (pulse width modulation signal), or the output signal of the power amplifier (driving means) may be a PWM signal.
A brushless DC motor may be used as the motor.
Further, the compensator may be composed of complete hardware such as a PLA (Programmable Logic Array) or the like so as to perform the same operation as the above-mentioned program. Alternatively, an analog arithmetic element may be used. Besides, various modifications can be made without changing the gist of the present invention. Effects of the Invention The motor speed control device of the present invention has extremely good control characteristics at a specific frequency while significantly reducing the number of memories and the calculation time, and changes in the rotation speed due to changes in load torque. Has been significantly reduced. Therefore, if a capstan motor for a video tape recorder is constructed based on the present invention, a high speed motor speed control device can be economically constructed.

[Brief description of drawings]

1 is a flow chart showing an example of a built-in program of the compensator shown in FIG. 2, FIG. 2 is an overall configuration diagram of an embodiment of the present invention, and FIG. 3 is a concrete example of the speed detector shown in FIG. Diagram,
FIG. 4 is a flow chart showing another example of a built-in program of the compensator of the present invention, and FIG. 5 is a flow chart showing another example of a built-in program of the compensator of the present invention. 1 ... motor, 2 ... rotation sensor, 3 ... speed detector,
4 ... Compensator, 5 ... Calculator, 6 ... Memory, 7 ... D /
A converter, 8 ... Power amplifier, 10 ... Load, 1A, 4A, 5A ...
... Error detection means, 1B, 4B, 5B ... Control signal creation means, 1F, 4
F, 5F ... Memory output value creating means, 1G, 4G, 5G ... composite error creating means, 1H, 4H, 5H ... update storing means.

Claims (2)

[Claims] 1. A rotation sensor that generates an AC signal having a cycle corresponding to the rotation speed of a motor, and detection of Zq times (where Zq is an integer of 8 or more) per rotation of the motor based on the AC signal of the rotation sensor. Comprising: a speed detecting means for performing the above; a compensating means for generating a control signal based on a detection signal of the speed detecting means; and a driving means for driving the motor according to the control signal of the compensating means. The means includes rotation error detection means for obtaining a new rotation error based on the detection signal at each detection timing at which the speed detection means obtains a new detection signal, and Nx · L (where Nx is an integer of 1 or more, L is an integer of 4 or more), memory means for storing and storing ordered memory values, synthetic error creating means for producing a synthetic error by arithmetically synthesizing a plurality of rotational errors of the rotational error detecting means, and the rotational error detecting means. It means a new rotational error Q times (here, Q is an integer of 2 or more) as the update timing obtaining timing, the Nx ·
Update storage means for updating and storing L memory values in order by the update value obtained by arithmetically combining the composite error of the composite error creating means and the memory output value of the memory output value creating means, and Nx is 1.
If at least one memory value is used, and if Nx is 2 or more, at least one set of Nx memory value groups whose update interval is L times or more of the update timing is used as the update timing. The memory output value creating means for creating the memory output value in synchronization with each other, the rotation error of the rotation error detecting means and the memory output value of the memory output value creating means are arithmetically combined for each detection timing to generate the control signal. The rotation error detecting means is configured to include a control signal generating means for generating, a calculating means for executing the operation of at least the combined error generating means, the memory output value generating means and the update storing means according to a program, and the rotation error detecting means The control signal generating means generates a new control signal each time an error is obtained, and the synthetic error is generated every time the rotation error detecting means obtains a new rotation error Q times. The creating means, the memory output value creating means, and the update saving means update one memory value, and the updating operation by the synthetic error creating means, the memory output value creating means, and the update saving means is Q or less. And a speed control device for the motor, wherein each of the partial operations is executed by the calculating means at different timings of the rotation error detecting means. 2. A speed control device for a motor according to claim 1, wherein L = (Zq / Q) · k (where k is an integer of 1 or more).