JPH0681535B2 - Motor speed controller - Google Patents

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor speed control device. 2. Description of the Related Art A motor speed control device that detects the rotation speed of a motor with a speed detector and controls the power supplied to the motor by the detection signal is widely used for capstan motors and cylinder motors of video tape recorders. (See, for example, Japanese Patent Application No. 56-142724 proposed by the applicant). However, in such a speed control device, only the conventionally used proportional / integral / derivative control is performed, and it is not possible to sufficiently suppress the fluctuation of the rotation speed due to the fluctuation of the load torque. In order to solve such a problem, the present applicant has filed Japanese Patent Application No.
-229143 and Japanese Patent Application No. 60-229144 have proposed a high-performance motor speed control device that is extremely resistant to load torque fluctuations. That is, in Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-229144, a rotation sensor that generates an AC signal with a cycle corresponding to the rotation speed of the motor and a plurality of rotation sensors per rotation of the motor by the AC signal of the rotation sensor. Speed detecting means for detecting, compensating means for calculating and storing a control signal based on the detection signal of the speed detecting means, and power amplifying means for supplying electric power according to the control signal of the compensating means to the motor. The (driving means) constitutes a speed control system. Further, a rotation error detecting means for obtaining a rotation error in response to a detection signal of the speed detecting means, a memory means for storing NxL (plural) memory value groups M [O] to M [NxL-1], and a memory A composite value calculating means (memory output value creating means) for substantially calculating a composite value to be compositely calculated using Nx memory value groups separated by L intervals of the means, and a composite value and rotation of the composite value calculating means. Update storage means for updating and storing the memory values of the memory means substantially in order by the update value corresponding to the value obtained by arithmetically synthesizing the rotation error of the error detection means, rotation of the synthesis value and rotation error detection means of the synthesis value calculation means A high-performance motor speed control device is realized by using a compensating means having a control signal generating means for arithmetically combining the errors to generate a control signal. However, in Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-229144, it is indispensable to use a large number of digital memories, and normally a memory of 16 bits × 1000 words = 16 kbits is required. Is required. Although IC devices for memories have been rapidly reduced in price due to recent improvements in semiconductor manufacturing technology, it is not preferable to use a memory of 16 kbits because the cost is significantly increased. Further, there is a considerable amount of calculation in the operation of the compensating unit including the combined value calculating unit (memory output value creating unit) and the update storing unit, and in order to finish the predetermined calculation within the detection period of the speed detector, It was necessary to perform high-speed calculation using an expensive high-speed multiplier or the like. That is, there are considerable restrictions on the configuration and operating speed of the hardware that implements the compensation means. In consideration of such a point, the present invention has examined a speed control device for a motor that uses many memories as shown in the above example, and drastically reduces the required number of memories without deteriorating the control performance. An object of the present invention is to provide a speed control device for a motor, which reduces the number of times and relaxes the constraint on the calculation time. Means for Solving the Problems In order to achieve the above object, in a motor speed control device of the present invention, a rotation sensor that generates an AC signal having a cycle corresponding to the rotation speed of the motor, and the AC signal of the rotation sensor, Speed detecting means for detecting a plurality of times per one rotation of the motor, compensating means for generating a control signal based on the detection signal of the speed detecting means, and driving the motor according to the control signal of the compensating means. The compensation means includes a rotation error detection means that obtains a new rotation error based on the detection signal at each detection timing when the speed detection means obtains a new detection signal, and Nx · L (here) In addition, Nx is an integer of 1 or more, L is an integer of 4 or more, and a memory means for storing and storing ordered memory values, and the rotation error detecting means generates a new rotation error Q times (where Q is 2).
The integer above) is the update timing,
Update storage means for updating and storing the Nx · L memory values in order by an update value obtained by arithmetically combining the rotation error of the rotation error detection means and the memory output value of the memory output value creation means; and when Nx is 1, Uses at least one memory value, and when Nx is 2 or more, at least one set of Nx memory value groups whose update interval is L times or more of the update timing is used in synchronization with the update timing. The memory output value generating means for generating the memory output value, and the rotation error of the rotation error detecting means and the memory output value of the memory output value generating means are arithmetically combined for each detection timing to generate the control signal. It includes a control signal creating means, and a computing means for performing the operations of the rotation error detecting means, the memory output value creating means, the update storing means, and the control signal creating means according to a program. The calculation means executes the operation of the rotation error detection means and the control signal creation means at each detection timing at which the speed detection means obtains a new detection signal, and the memory output value creation means. The operation of updating one memory value by the update storing means is divided into a plurality of partial operations, and each partial operation is executed at different timings of the speed detecting means. Action In the present invention, by using the above-mentioned structure, Japanese Patent Application No.
As described in Japanese Patent Application No. 229143 and Japanese Patent Application No. 60-229144, it is possible to significantly reduce the influence of load torque fluctuation at a specific frequency. Moreover, an economically high-performance motor speed control device is realized by using a small number (1 / Q) of the number of memories. Furthermore, one memory value updating operation by the memory output value creating means and the update storing means is divided into a plurality of partial operations, and each partial operation is executed by the calculating means at different timings of the speed detecting means. Therefore, by using one calculation means with a slow calculation speed,
The rotation error detecting means, the memory output value creating means, the update saving means, and the control signal creating means can be executed. Embodiment Hereinafter, a motor speed control device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 2 shows an overall configuration diagram of the motor speed control device of the present invention. In FIG. 2, the DC motor 1 directly drives the rotation sensor 2 and the load 10 to rotate. The rotation sensor 2 is Zq times per rotation according to the rotation of the motor 1 (Zq is an integer of 2 or more, and normally Zq = 357 in a capstan motor of a video tape recorder).
To generate the AC signal a. The AC signal a of the rotation sensor 2 is input to the speed detector 3 to obtain a digital signal b corresponding to the cycle of the AC signal a. FIG. 3 shows a specific configuration example of the speed detector 3. The AC signal a is waveform-shaped by the waveform shaping circuit 31 to obtain the shaped signal g. The shaping signal g is input to the AND circuit 33 and the flip-flop 35. On the input side of the AND circuit 33, the clock pulse P of the oscillator circuit 32 and the counter are further provided.
34 overflow output signals w are also input. The oscillation circuit 32 is composed of a crystal oscillator, a frequency divider, etc., and has a clock pulse p of a frequency considerably higher than the frequency of the shaping signal g.
(About 500kHz) is generated. The counter 34 is a 12-bit up counter that counts up the contents of the output pulse h of the AND circuit 33 each time it arrives. The overflow output signal w is “H” when the count content of the counter 34 is less than or equal to a predetermined value, and w changes to “L” when the count content of the counter 34 is greater than or equal to the predetermined value (here, “H”). Represents a high potential state, "L" represents a low potential state). The data input flip-flop 35 takes in "H" input to the data input terminal with the falling edge of the shaping signal g as a trigger signal, and outputs its output Q to "H".
(Q = “H”). Further, when the reset signal r from the compensator 4 becomes “H”, the counter 34 and the flip-flop 35.
The internal state of is reset (b = "LLLLLLLLLLLL",
w = “H”, q = “L”). Next, the operation of the speed detector 3 shown in FIG. 3 will be described.
Now, it is assumed that the counter 34 and the flip-flop 35 are reset by the reset signal r. When the output signal g of the waveform shaping circuit 31 changes from “L” to “H”, the clock pulse p of the oscillation circuit 32 is output as the output signal h of the AND circuit 33.
Is output. The counter 34 counts the output signal h,
The internal state is changed. When the output signal g of the waveform shaping circuit 31 changes from "H" to "L", the output signal h of the AND circuit 33 becomes "L", and the counter 34 holds its internal state. Further, the flip-flop 35 takes in the data “H” at the falling edge of the signal g and outputs its output signal q.
Is changed from “L” to “H”. The digital signal b of the counter 34 is a value proportional to the (half) cycle length of the AC signal a of the rotation sensor 2 and inversely proportional to the rotation speed of the motor 1. The compensator 4, which will be described later, looks at the output signal q of the flip-flop 35, inputs the digital signal b of the counter 34 when q becomes “H”, and then outputs the reset signal r to “H” for a predetermined short time. Then, the counter 34 and the flip-flop 35 are reset to the initial state to prepare for the next speed detection operation. When the rotation speed of the motor 1 is too slow, the internal state of the counter 34 exceeds a predetermined value because the cycle of the output signal g of the waveform shaping circuit 31 is long, and the overflow output signal w changes from "H" to "L". In some cases, the output signal h of the AND circuit 33 becomes "L" and the counter 34 holds a predetermined large value. The compensator 4 shown in FIG. 2 is composed of a computing unit 5, a memory 6 and a D / A converter 7. The digital signal b of the speed detector 3 is calculated and processed by a built-in program described later, and a control signal c is output. To do. The control signal c of the compensator 4 is the power amplifier 8
The drive signal d (current proportional to the control signal c), which is input to the (drive unit) and is power-amplified, is supplied to the motor 1. Therefore, the motor 1, the rotation sensor 2, the speed detector 3, the compensator 4, and the power amplifier 8 (driving unit) constitute a speed control system, and the rotation speed of the motor 1 is controlled to a predetermined value. The memory 6 of the compensator 4 is divided into a ROM area (ROM: read only memory) in which a predetermined program and constants are stored and a RAM area (RAM: random access memory) in which a required value is stored at any time. The computing unit 5 performs a predetermined operation or computation according to a program in the ROM area. FIG. 1 shows a concrete example of the program. Next, the operation will be described in detail. (1) <Rotation error detector 1A> First, the calculator 5 inputs the output signal q of the flip-flop 35 of the speed detector 3 and waits for the signal q to become "H". That is, it is monitored that the speed detector 3 detects the (half) cycle of the AC signal a and outputs a new digital signal b. When q becomes "H", the digital signal b of the speed detector 3 is read, the speed detection value S (digital value) corresponding to the digital signal b is read, and the reset signal r is set to "H" for a predetermined time to set the speed. The counter 34 and the flip-flop 35 of the detector 3 are reset. The speed detection value S is subtracted from the predetermined reference value Sref, and the value is multiplied by R (where R is a predetermined positive constant) to calculate the rotation error E of the motor 1 at the present time [E = R. (Sref-S)]. (2) <Control signal creating unit 1B> The memory output value V0 by the memory output value creating unit 1E, which will be described later, and the current rotation error E of the rotation error detecting unit 1A are set to a predetermined ratio D:
1 (where D is a constant 0 <D ≦ 1, preferably D
= 1), the control signal value Y is calculated (Y =
E + D ・ V0). Output the control signal value Y to the D / A converter 7,
It is converted into a DC voltage (control signal) corresponding to the value of Y. (3) <first counting unit 1C> Q (where Q is an integer of 2 or more) is mod (modulus),
Each time a new speed detection value S is obtained, the first count variable I1 is incremented. That is, after setting I1 = I1 + 1 (I1 + 1 is newly set to I1), if I1 = Q, I1 is reset to 0. If such an operation is performed, I1 becomes an integer between 0 and Q-1. The initial value of I1 is 0. If I1 is 0, the operations (4) and (5) are executed, if I1 is 1, the operation (6) is executed, and if I1 is not 0 or 1, the operation returns to (1). (4) <Second Counting Unit 1D> Nx · L (where Nx is an integer and L is an integer of 4 or more. In particular,
Since Nx is preferably an integer of 2 or more and L is an integer multiple of 2 or more of (Zq / Q), such a case will be described below. ) As a mod (modulus), the second count variable I2 is incremented each time the first count variable I1 becomes 0 (every Q new speed detection values S are obtained). That is, after setting I2 = I2 + 1, if I2 = NxL, then I
Reset 2 to 0. If you do such an operation, I
2 will be an integer between 0 and NxL-1. The initial value of I2 is NxL-1. (5) <Memory output value creation unit 1E> The integer J is made equal to I2 (J = I2), and Nx memory value groups M [J-nL (mo
Using d NxL] (n = 1, ..., Nx), a memory output value V0 is created by the following equation. Here, the value of the ratio Wn is 0 <Wn <2 / Nx (n = 1, ..., Nx) (2), and Is standardized. Specifically, if Wn = 1 / Nx (n = 1, ..., Nx) (4) when Nx ≧ 2, the equation (1) is expressed by the memory value group M [J−nL (modNx
L)] (n = 1, ..., Nx) is simply added and synthesized, and then Nx
It will be divided by (integer), which makes the calculation very simple.
After that, the operation returns to (1). (6) <Update storage unit 1F> The memory output value V0 by the memory output value creation unit 1E and the rotation error E of the rotation error detection unit 1A are arithmetically combined at a ratio of 1: 1 to calculate the update value, and the second value is calculated. Update the memory value M [I2] in the RAM area of the memory 6 corresponding to the count variable I2 of (M [I2]
= E + V0), store and save until the next update. After that,
Return to the operation of (1). In the motor speed control device of this embodiment, the load 10 shown in FIG.
It is extremely strong with respect to a specific frequency component of the load torque fluctuation caused by the same as in the patent of the prior application. Further, as shown in the present embodiment, each time the rotation error detection unit 1A obtains a new rotation error signal, the control signal creation unit 1B creates a new control signal, and the rotation error detection unit 1A creates a new rotation error signal. If the update storage unit 1F updates one memory value each time Q is obtained, the number of memories required for the memory unit is substantially reduced to 1 / Q. Even if the number of memories is reduced in this way, the effect of becoming extremely strong with respect to the specific frequency component of the load torque fluctuation (the effect of not causing the rotation speed fluctuation) is retained. this is,
It can be explained as follows. When the value of L is increased, the frequency component improved by the operation of the memory 6, the memory output value creation unit 1E and the update storage unit 1F can be made considerably lower than the detection frequency of the rotation error detection unit 1A (speed detector 3). I understood. Therefore, even if the frequency of the rotation error signal of the rotation error detection unit 1A used in the update storage unit 1F is reduced to 1 / Q, it is possible to prevent the above improvement effect from being adversely affected. Further, the memory output value creation unit 1E and the update storage unit 1F constitute a memory update unit, and a rotation error detection is performed for one memory value update operation (memory update operation by the memory output value creation unit 1E and update storage unit 1F). Since the timing of the rotation error detection operation of the unit 1A (detection signal of the speed detector 3) is shifted, the amount of calculation required in one detection cycle of the rotation error detection unit 1A is reduced. Furthermore, since the operation of the memory output value creation unit 1E is performed when I1 = 0, the memory output value V0 used in the control signal creation unit 1B is changed without delay. Further, in the motor speed control device of the present invention, L =
If (Zq / Q) · k (where k is an integer of 2 or more), there is an effect of greatly suppressing the rotation speed fluctuation due to the load torque fluctuation of a cycle of k times one rotation cycle of the motor 1. . Such an effect is very preferable in the case of a capstan motor of a video tape recorder. This will be described. Since the load of the capstan motor is a magnetic tape or a pinch roller, the load fluctuation generated by the load 10 is a component synchronized with the rotation of the motor 1 (periodic load fluctuation with one rotation of the motor 1 as a basic cycle). Besides, motor 1
In many cases, a load fluctuation component having a frequency lower than the rotation frequency of is generated. Such load fluctuations cause fluctuations in the rotational speed of the capstan motor, causing wow and flutter of the tape speed. By the way, it has been found that such load fluctuations often have periodic fluctuations having a cycle that is an integral multiple of the cycle of one rotation of the motor 1. Therefore, due to the above-mentioned effect, a considerably low frequency fluctuation of the rotation speed of the motor 1 due to the load torque fluctuation can be effectively reduced. Note that Q is not limited to a divisor of Zq (for example, Q = k
Then, Q becomes independent of Zq). FIG. 4 shows a program example of the compensator 4 in consideration of the stability of the entire control system. Here, the method of calculating the update value in the update storage unit, the number of preparations of the memory output value in the memory output value creation unit, and the method of using the memory output value in the memory output value creation unit in the control signal creation unit are improved. is doing. Next, the operation will be described in detail (the entire configuration is the same as that in FIG. 2, and the description is omitted). (11) <Rotation Error Detection Unit 4A> First, the calculator 5 inputs the output signal q of the flip-flop 35 of the speed detector 3 and waits for the signal q to become “H”. That is, it is monitored that the speed detector 3 detects the (half) cycle of the AC signal a and outputs a new digital signal b. When q becomes "H", the digital signal b of the speed detector 3 is read, the speed detection value S (digital value) corresponding to the digital signal b is read, and the reset signal r
Is set to "H" for a predetermined time to reset the counter 34 and the flip-flop 35 of the speed detector 3. The speed detection value S is subtracted from the predetermined reference value Sref, and the value is multiplied by R (where R is a predetermined positive constant) to calculate the rotation error E of the motor 1 at the present time [E = R. (Sref-S)]. (12) <Control signal creating unit 4B> The memory output value V0 by the memory output value creating unit 4E described later and the current rotation error E of the rotation error detecting unit 4A are set to a predetermined ratio D:
Computation is performed in 1 to calculate the control signal value Y (Y = E +
D ・ V0). The control signal value Y is output to the D / A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y. (13) <First Count Unit 4C> With Q as a mod, the first count variable I1 is incremented each time a new speed detection value S is obtained. I1 is
When it becomes equal to Qa (where Qa is an integer smaller than Q), the memory output value V0 is changed to V [Px] described later, and when I1 is not equal to Qa, such a changing operation is not performed. As a result, V0 = V [Px−1] (described later) in the range of I1 <Qa, and V0 = V [Px] in the range of I1 ≧ Qa. Further, if I1 is 0, the operations (14) and (15) are executed, if I1 is 1, the operation (16) is executed, and if I1 is not 0 or 1, the operation returns to (11). . (14) <Second Counting Unit 4D> When Nx · L is mod (modulus), the first count variable I1 is 0.
Every 2 times (every Q new speed detection values S are obtained)
The count variable I2 of is incremented. (15) <Memory output value creation unit 4E> After transferring the contents of the register variable V [m + 1] to V [m] in order [m = 0, 1, ..., Px-1], and NxL as mod An integer J is calculated by adding Px (where Px is an integer of 1 or more and 3 or less, preferably Px = 1) to the count variable I2 of 2 [J = I2 + Px (mod NxL)]. The latest memory output value calculated by the following equation using the memory value group M [J−nL (mod NxL)] (n = 1, ..., Nx) in the RAM area is input to V [Px]. Here, the value of Wn satisfies the expressions (2), (3), and (4). That is, V [Px] to V

A group of Px + 1 memory output values consecutive to [0] is obtained. At this time, V
Let V be the integer J in equation (5) when calculating [Px]

When the integer J in the equation (5) when calculating [0] is J2, there is a relationship of J1 = J2 + Px. Next, the control signal generator 4B
The memory output value V0 used first in V [Px−
1] (V0 = V [Px-1]). Then, the operation returns to (11). (16) <Update storage unit 4F> After transferring the contents of the register variable X [m + 1] to X [m] in order (n = 0,1,2, ..., 2Kd-1), X [2Kd]
(Where Kd is an integer, preferably Kd = 3), the old memory output value V created by the memory output value creation unit 4E

[0] and the rotation error E of the rotation error detector 4A are arithmetically combined at a ratio of 1: 1 and the combined value is entered (X [2Kd] = E + V

[0]). That is, from X [2Kd] to X

2Kd + 1 addition values (addition value of memory output value and rotation error) consecutive to [0] are obtained. From the second count variable I2, where NxL is mod
Calculate the integer K minus Kd [K = I2-Kd (mod Nx
L)]. Next, a predetermined positive ratio Cm (m = 0,1,
.., 2Kd) is added to obtain a new updated value, which is stored and saved as the memory value M [K] in the RAM area of the memory 6 until the next update. That is, And Here, the ratio Cm has the following relationship. Then, the operation returns to (11). As in the present embodiment, a calculation for calculating a weighted average is inserted in the update storage unit 4F, or the first memory output value V0 (V [Px]) of the memory output value creation unit 4E used in the control signal creation unit 4B.
And memory output value creation unit 4E used in the update storage unit 4F
Second memory output value V of

A certain deviation (V
[Px] is V

If it is more advanced than [0],
It was confirmed that the operation of the entire control system was stable. In particular,
It was also found that the values of Px and Qa related to the usage timing are deeply related to the value of Q, and it is better to satisfy (QPx−Qa) ≧ Q / 2. This is the same memory output value (for example, V

(Value of [0]) When the use timing in the control signal creation unit 4B is converted into the number of detections of the rotation error detection unit 4A (the number of detections of the speed detector 3) compared to the use timing in the update storage unit 4F, Q / 2 means to be faster than twice. Further, as shown in the present embodiment, when a large number of transfers and multiplications are included in the operation of the memory output value creation unit 4E and the operation of the update storage unit 4F, the memory output value creation unit 4E and the update storage unit 4E. 4F
If one memory value updating operation by the memory updating section is divided into a plurality of partial operations and each partial operation is calculated and processed at different detection timings of the rotation error detecting section 4A, the rotation error detecting section 4A The calculation amount of the arithmetic unit 5 required within one detection period is significantly reduced, and the restriction on the arithmetic speed required for the arithmetic unit 5 is greatly relaxed. FIG. 5 shows another program example of the compensator 4 in consideration of the stability of the entire control system. Here, the method of calculating the memory output value and the number of preparations in the memory output value creating unit, and the method of using the memory output value of the memory output value creating unit in the control signal creating unit are improved. Next, the operation will be described in detail (the entire configuration is the same as that in FIG. 2, and the description is omitted). (21) <Rotation Error Detection Unit 5A> First, the arithmetic unit 5 inputs the output signal q of the flip-flop 35 of the speed detector 3 and waits for the signal q to become “H”. That is, it is monitored that the speed detector 3 detects the (half) cycle of the AC signal a and outputs a new digital signal b. When q becomes "H", the digital signal b of the speed detector 3 is read, the speed detection value S (digital value) corresponding to the digital signal b is read, and the reset signal r is set to "H" for a predetermined time to set the speed. The counter 34 and the flip-flop 35 of the detector 3 are reset. The speed detection value S is subtracted from the predetermined reference value Sref, and the value is multiplied by R (where R is a predetermined positive constant) to calculate the rotation error E of the motor 1 at the present time [E = R. (Sref-S)]. (22) <Control signal creation unit 5B> The memory output value V0 by the memory output value creation unit 5E, which will be described later, and the current rotation error E of the rotation error detection unit 5A are set to a predetermined ratio D:
Computation is performed in 1 to calculate the control signal value Y (Y = E +
D ・ V0). The control signal value Y is output to the D / A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y. (23) <First Count Unit 5C> With Q as a mod, the first count variable I1 is incremented each time a new speed detection value S is obtained. I1 is
When it becomes equal to Qa (here, Qa is an integer smaller than Q), the memory output value V0 is changed to V [Px] described later, and when I1 is not equal to Qa, such a changing operation is not performed. As a result, V0 = V [Px−1] (described later) in the range of I1 <Qa, and V0 = V [Px] in the range of I1 ≧ Qa. Further, if I1 is 0, the operations of (24) and (25) are executed, and I1
If is 1, the operation of (26) is executed, and if I1 is not 0 or 1, the operation returns to (21). (24) <Second Counting Unit 5D> When Nx · L is mod (modulus), the first count variable I1 is 0.
Every 2 times (every Q new speed detection values S are obtained)
The count variable I2 of is incremented. (25) <Memory output value creation unit 5E> After transferring the contents of register conversion X [m + 1] to X [m] in order (m = 0,1,2, ..., 2Kd−1), NxL is mod Then, an integer J is calculated by adding Px + Kd (Px is an integer of 1 or more and 3 or less and Kd is an integer of 1 or more) to the second count variable I2 [J = I2 + Px + Qx (mod NxL)]. N in the ram region
x memory value group M [J−nL (mod NxL)] (n = 1, ...
, Nx) and the calculated value calculated by the following equation is X [2K
d]. Here, the value of Wn satisfies the expressions (2), (3), and (4). That is, from X [2Kd] to X

2Kd + 1 calculated values (calculated values obtained from Nx memory values separated by L intervals) consecutive to [0] are obtained. Next, after sequentially transferring the contents of the register variable V [m + 1] to V [m] (m + 0,1, ..., Px-1), X [m] (m = 0,1, ...,
2Kd) is multiplied by a predetermined positive ratio Cm (m = 0,1, ... 2Kd) to obtain the latest memory output value, and V [Px]
Put in. Here, the ratio Cm has the relationship of the expressions (7) and (8).
That is, V [Px] to V

Px + 1 memory output values consecutive to [0] are obtained. At this time, substantially V [Px]
Let J1 be the integer J in equation (9) when calculating

Assuming that the integer J in the equation (9) when calculating [0] is J2, there is a relation of J1 = J2 + Px. That is, V [Px] and V

There is a gap corresponding to the integer Px between [0]. Next, the memory output value V0 is set to V [Px-1] (V0 = V [Px-
1]). Then, the operation returns to (21). (26) <Update storage unit 5F> Old memory value V created by the memory output value creation unit 5E

[0] and the rotation error E of the rotation error detection unit 5A are arithmetically combined at a ratio of 1: 1 to calculate an updated value, and the second count variable
Memory value M [I2] in RAM area corresponding to I2
Is updated (M [I2] = E + V

[0]), store and save until the next update. Then, the operation returns to (21). As in the present embodiment, the arithmetic operation for taking a weighted average and the arithmetic operation for preparing a plurality of memory output values are inserted in the memory output value creating unit 5E, and the first of the memory output value creating unit 5E used in the control signal creating unit 5B is inserted. One memory output value Vo (V [Px]) and the second memory output value V of the memory output value creation unit 5E used in the update storage unit 5F.

A certain deviation (V [Px] is V

If it is more advanced than [0], the operation of the entire control system becomes stable. Also in this case, (QPx−Qa) ≧ Q / 2
However, the calculation by the ratio Wn or Cm is not limited to the above-mentioned form, and it is sufficient as long as it substantially realizes the contents of the above-mentioned program, and various equivalent formula modifications are possible. Needless to say. Further, when a new digital rotation error is obtained, the control signal creating unit first outputs a new control signal, and then the memory output value creating unit calculates the memory output value to be used at the next sampling time. By doing so, the calculation time of the memory output value creation unit can be made longer and the time delay until the output of the control signal can be shortened, so that the stability of the control system can be easily ensured. Besides, various modifications can be made without changing the gist of the present invention. EFFECTS OF THE INVENTION The motor speed control device of the present invention is designed to obtain extremely good control characteristics at a specific frequency while using a small number of memories. Further, the calculation speed required for the arithmetic unit is improved so that it may be slow. Therefore, if a speed control device for a capstan motor of a video tape recorder is constructed based on the present invention, a high speed motor speed control device can be economically realized.

[Brief description of drawings]

FIG. 1 is a flow chart showing an example of a built-in program of the compensator shown in FIG. 2, FIG. 2 is a block diagram showing the entire constitution of an embodiment of the present invention, and FIG. 3 is a diagram showing the speed detector shown in FIG. FIG. 4 is a configuration diagram showing a specific configuration example, FIG. 4 is a flow chart diagram showing another example of the internal program of the compensator shown in FIG. 2, and FIG. 5 is another example of the internal program of the compensator shown in FIG. It is a flowchart figure showing. 1 ... motor, 2 ... rotation sensor, 3 ... speed detector,
4 ... Compensator, 5 ... Calculator, 6 ... Memory, 7 ... D /
A converter, 8 ... Power amplifier, 10 ... Load, 1A, 4A, 5A ...
… Rotation error detector, 1B, 4B, 5B …… Control signal generator, 1C, 4
C, 5C …… First counting section, 1D, 4D, 5D …… Second counting section, 1E, 4E, 5E …… Memory output value creation section, 1F, 4F, 5F ……
Update storage section.

Claims (1)

[Claims] 1. A rotation sensor for generating an AC signal having a cycle corresponding to the rotation speed of a motor, speed detection means for detecting a plurality of times per one rotation of the motor by the AC signal of the rotation sensor, and the speed detection means. Compensation means for generating a control signal based on the detection signal of, and drive means for driving the motor according to the control signal of the compensation means, wherein the compensation means is a new detection signal for the speed detection means. Rotation error detection means for obtaining a new rotation error based on the detection signal and Nx · L (where Nx is an integer of 1 or more and L is an integer of 4 or more) are ordered at each detection timing for obtaining The memory means for storing and storing the memory value and the rotation error detection means generate a new rotation error Q times (where Q is 2
The integer above) is the update timing,
Update storage means for updating and storing the Nx · L memory values in order by an update value obtained by arithmetically combining the rotation error of the rotation error detection means and the memory output value of the memory output value creation means; and when Nx is 1, Uses at least one memory value, and when Nx is 2 or more, at least one set of Nx memory value groups whose update interval is L times or more of the update timing is used in synchronization with the update timing. The memory output value generating means for generating the memory output value, and the rotation error of the rotation error detecting means and the memory output value of the memory output value generating means are arithmetically combined for each detection timing to generate the control signal. It includes a control signal creating means, and a computing means for performing the operations of the rotation error detecting means, the memory output value creating means, the update storing means, and the control signal creating means according to a program. The calculation means executes the operation of the rotation error detection means and the control signal creation means at each detection timing at which the speed detection means obtains a new detection signal, and the memory output value creation means. And an updating operation of the one memory value by the update storing means is divided into a plurality of partial operations, and each partial operation is executed at different timings of the speed detecting means. .