JPH06101949B2 - Cylinder motor control device - Google Patents

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cylinder motor control device. 2. Description of the Related Art A cylinder motor controller that detects the rotation speed of a cylinder motor with a speed detector and controls the power supplied to the cylinder motor based on the detection signal is widely used in magnetic tape running devices such as video tape recorders. (See, for example, Japanese Patent Application No. 56-142724). However, in such a control device, only the conventionally used proportional / integral / derivative control is performed, and it is not possible to sufficiently suppress the fluctuation of the rotation speed due to the fluctuation of the load torque. In order to solve such a problem, the present applicant has filed Japanese Patent Application No.
-229143 and Japanese Patent Application No. 60-229144 have proposed a high-performance motor speed controller that is extremely resistant to load torque fluctuations. That is, Japanese Patent Application No. Sho 60-229143 and Japanese Patent Application No. Sho 60
In No. 229144, a rotation sensor that generates an AC signal with a cycle corresponding to the rotation speed of the motor, a speed detection unit that detects a plurality of times per rotation of the motor by the AC signal of the rotation sensor, and a detection signal of the speed detection unit. A speed control system is composed of a compensating means for calculating and storing a control signal based on the above, and a power amplifying means (driving means) for supplying electric power according to the control signal of the compensating means to the motor. further,
Rotation error detection means for obtaining a rotation error in response to the detection signal of the speed detection means, and N × L (plural) memory value groups M

Combined value calculating means for substantially calculating a combined value calculated by using memory means for storing [0] to M [NxL-1] and Nx memory value groups separated by L intervals of the memory means. (Memory output value creating means), and update by substantially updating the memory values of the memory means in order by the update value corresponding to the value obtained by arithmetically combining the combined value of the combined value calculating means and the rotation error of the rotation error detecting means. High-performance motor speed control by using a compensating means having a storage means and a control signal generating means for arithmetically combining the combined value of the combined value calculating means and the rotation error of the rotation error detecting means to generate a control signal The device is realized. Problems to be Solved by the Invention When the speed control device for a motor shown in Japanese Patent Application No. 60-229143 or Japanese Patent Application No. 60-229144 is used as a control device for a cylinder motor, some improvement is required. I found out that there is. For example, in the case of a cylinder motor of a video tape recorder, it has been found that fluctuations in tension from the supply reel (or take-up reel) greatly affect the fluctuations in the rotational speed. Further, the frequency of the tension fluctuation from the reel changes with the winding diameter. Therefore, Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-229144
The configuration of No. could not reduce the fluctuation of the rotational speed due to the influence of these tension fluctuations. Further, in the configurations of Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-229144, it is indispensable to use a large number of digital memories, and normally, a memory of about 16 bits × 1000 wrods = 16 kbits is required. . Although IC devices for memories have been rapidly reduced in price due to recent improvements in semiconductor manufacturing technology, it is not preferable to use a memory of 16 kbits because the cost is significantly increased. In consideration of such a point, the present invention provides a cylinder motor control device in which the influence of tension fluctuation from the reel is sufficiently reduced and the number of required memories is reduced. Means for Solving the Problems According to the present invention, a rotation sensor that generates an AC signal with a cycle corresponding to the rotation speed of a cylinder motor, and an AC signal from the rotation sensor are used to perform a plurality of detections per rotation of the cylinder motor. The speed detecting means, a compensating means for generating a control signal based on the detection signal of the speed detecting means, and a driving means for driving the cylinder motor in accordance with the control signal of the compensating means, the compensating means, A rotation error detecting means for obtaining a rotation error in response to a detection signal of the detecting means, a memory means for storing four or more memory values, and a memory output using at least one memory value stored in the memory means. A memory output value creating means for creating a value, and a composite error creating means for creating a composite error that combines a plurality of rotation errors of the rotation error detecting means. And updating storage means for substantially updating stored sequentially memory value of said memory means by the update value corresponding to combined error in the calculation synthesized value of the memory output value and the combined error preparing means of said memory output value generating means,
Control signal generating means for arithmetically combining the memory output value of the memory output value generating means and the rotation error of the rotation error detecting means to generate the control signal, and the update storing means and the memory output according to the reel rotation cycle. A reel cycle responsive means for increasing or decreasing the number of memory values handled by the value creating means, the control signal creating means creates a new control signal each time the speed detecting means obtains a new detection signal, and the speed detecting means The above-mentioned problem is solved by arranging the update storing means to update substantially one memory value each time Q new detection signals (where Q is an integer of 2 or more) are obtained. It is a thing. Operation In the present invention, with the above configuration, a high-performance cylinder motor control device is realized with a small number of memories. That is, Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-
The improvement part of the control characteristics of the motor speed control device as shown in No. 229144 is devised so as to always correspond to the frequency of the tension fluctuation from the detection reel, and the required memory number is reduced. Embodiment FIG. 2 shows a basic block diagram of a tape running system of a video tape recorder. The magnetic tape 10 sent from the supply reel 11b is wound around the cylinder motor 1 by 180 degrees or more by the impedance rollers 22 and 23. Video information is recorded / reproduced on / from a magnetic tape by a rotary magnetic head mounted on the cylinder motor 1. The magnetic tape 10 is pressed against the capstan motor 21 by the pinch roller 24,
The tape runs at a predetermined speed proportional to the rotation speed of the capstan motor 1 and is wound on the take-up reel 11a. The rotation speed of the cylinder motor 1 fluctuates due to fluctuations in the tension of the magnetic tape 10 caused by the take-up reel 11a and the supply reel 11b, and fluctuations (wow and flutter) occur in the magnetic tape running speed. Since the frequency of tension fluctuation is proportional to the rotation speed of the reel, it changes according to the winding amount of the magnetic tape 10 on each reel, and occurs in a fairly wide frequency range from the beginning to the end of the tape. To do. In particular, the rotation speed fluctuation of the cylinder motor 1 is likely to occur largely due to the influence of the supply reel 11b. FIG. 3 is a block diagram showing an embodiment of the present invention. In FIG. 3, the rotation sensor 2 is Zq times per rotation according to the rotation of the cylinder motor 1 (Zq is an integer of 2 or more, and in a cylinder motor of a video tape recorder, normally Zq = 6).
To generate the AC signal a. The AC signal a of the rotation sensor 2 is input to the speed detector 3, and a digital signal b corresponding to the cycle of the AC signal a is obtained. A specific configuration example of the speed detector 3 is shown in FIG. The AC signal a is waveform-shaped by the waveform shaping circuit 31 to obtain the shaped signal g. The shaping signal g is directly input to the AND circuit 33 and the first differentiating circuit 36, and is also input to the second differentiating circuit 38 via the inverter circuit 37. First differentiation circuit
36 generates a minute differential pulse i at the rising edge of the shaping signal g, and this pulse causes the counter circuit
Reset the internal state of 34. The second differentiating circuit 38 generates a minute differential pulse k at the falling edge of the shaping signal g, loads (inputs / holds) the digital signal j of the counter circuit 34 into the latch circuit 39, and at the same time, inputs the data input flip-flop. Set the output of group 40. The clock pulse p of the puncture circuit 32 and the overflow output signal w of the counter circuit 34 are also input to the input side of the AND circuit 33. The oscillation circuit 32 is composed of a crystal oscillator, a frequency divider, etc., and generates a clock pulse p (about 500 KHz) having a frequency considerably higher than the frequency of the shaping signal g. The counter circuit 34 is a 12-bit up-counter that counts up the contents of the output pulse h of the AND circuit 33 each time it arrives. The overflow output signal w is "H" when the count content of the counter circuit 34 is less than or equal to a predetermined value, and w changes to "L" when the count content of the counter circuit 34 is greater than or equal to the predetermined value (here, ""H" represents a high potential state, "L" represents a constant potential state). The data input flip-flop 40 has the "H" input to the data input terminal at the falling edge of the shaping signal g.
Is taken in, and its output Q is set to "H" (q = "H"). Further, when the reset signal r from the compensator 4 becomes "H", the internal state of the flip-flop 40 is reset (q =
"L"). Next, the operation of the speed detector 3 shown in FIG. 4 will be described. Now, it is assumed that the flip-flop 40 is reset by the reset signal r. When the output signal g of the waveform shaping circuit 31 changes from "L" to "H", first, the first differentiating circuit 36
Generates a differential pulse i and resets the counter circuit 34. Then, the output signal h of the AND circuit 33 is added to the oscillation circuit 32.
, The counter circuit 34 counts the output signal h and changes its internal state. Next, when the output signal g of the waveform shaping circuit 31 changes from "H" to "L", the output signal h of the AND circuit 33 becomes "L", and the counter circuit 34 holds its internal state. Also,
The second differentiating circuit 38 outputs the differential pulse k, loads the state signal j of the counter circuit 34 into the latch circuit 39, and changes the output signal q of the flip-flop 40 from "L" to "H".
Therefore, the digital signal b of the latch circuit 39 is a value proportional to the (half) cycle length of the AC signal a of the rotation sensor 2,
It is inversely proportional to the rotation speed of the cylinder motor 1. The compensator 4 to be described later looks at the output signal q of the flip-flop 40,
When q becomes "H", the digital signal b of the latch circuit 39 is input, and then the reset signal r is kept at "H" for a predetermined short time.
Then, the flip-flop 40 is reset to the desired state. When the rotation speed of the cylinder motor 1 is too slow, the internal state of the counter circuit 34 becomes a predetermined value or more because the cycle of the output signal g of the waveform shaping circuit 31 is long, and the overflow output signal w changes from "H" to " Change to L ", and circuit
The output signal h of 33 becomes "L", and the counter circuit 34 may hold a predetermined large value. The reel rotation sensor 12 shown in FIG. 3 generates an AC signal e in response to the rotation of the detection reel (winding reel or supply reel) 11. The reel rotation detector 13 obtains the digital signal 1 proportional to the cycle of the AC signal e. The specific configuration example is similar to that of the speed detector 3 shown in FIG. 4 (the flip-flop 40 is omitted). The compensator 4 shown in FIG. 3 is composed of a computing unit 5, a memory 6 and a D / A converter 7, and a digital signal b of the speed detector 3 is obtained.
And the digital signal 1 of the reel rotation detector 13 are input, and the control signal c is output after being processed by a built-in program described later. The control signal c of the compensator 4 is the power amplifier 8
The driving signal d input to (driving means) and power-amplified
(Current proportional to the control signal c) is supplied to the cylinder motor 1. Therefore, the cylinder motor 1, the rotation sensor 2, the speed detector 3, the compensator 4, and the power amplifier 8 (driving means) constitute a speed control system, and the rotation speed of the cylinder motor 1 is controlled to a predetermined value. The memory 6 of the compensator 4 is divided into a ROM area (ROM: read only memory) in which a predetermined program and constants are stored and a RAM area (RAM: random access memory) in which a required value is stored at any time. The computing unit 5 performs a predetermined operation or computation according to a program in the ROM area. FIG. 1 shows a concrete flowchart of the program. Next, the operation will be described in detail. (1) <Rotation Error Detection Means> First, the arithmetic unit 5 inputs the output signal q of the flip-flop 40 of the speed detector 3 and waits for the signal q to become “H”. That is, it is monitored that the speed detector 3 detects the (half) cycle of the AC signal a and outputs a new digital signal b. When q becomes "H", the digital signal b of the speed detector 3 is read, the speed detection value S (digital value) corresponding to the digital signal b is read, and the reset signal r is set to "H" for a predetermined time. The flip-flop 40 of the speed detector 3 is reset. The speed detection value S is subtracted from the predetermined reference value Sref, and the value is multiplied by R (where R is a predetermined positive constant) to calculate the rotation error E of the cylinder motor 1 at the present time [E = R -(Sref-S)]. (2) <Control signal creating means> The memory output value V0 by the memory output value creating means, which will be described later, and the current rotation error E are set to a predetermined ratio D: 1 (where D is 0).
It is a constant such that <D ≦ 1, preferably D = 1), and the control signal value Y is calculated (Y = E + D · V0). The control signal value Y is output to the D / A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y. (3) <Saving the rotation error time series> A memory value F [I [I] corresponding to a first count variable I1 described later.
The current rotation error E is stored and saved in [1] (F [I
1] = E). (4) <First Counting Means> Q (where Q is an integer of 2 or more) is mod (modulus),
Each time a new speed detection value S is obtained, the first count variable I1 is incremented. That is, I1 = I1 + 1 (I1 +
1 is changed to I1), then I1 is set to 0 if I1 = Q
Reset to. If such an operation is performed, I1 is 0
To an integer between Q-1. The initial value of I1 is 0. If I1 is 0, then (5), (6), (7), (8),
The operation (9) is executed, and if I1 is not 0, the operation returns to the operation (1). (5) <Second Counting Means> Nx.L (generally, Nx is an integer, L is an integer of 4 or more. However, since Nx is preferably an integer of 2 or more, such a case will be described below. .) As a mod (modulus), the second count variable I2 is incremented each time the first count variable I1 becomes 0 (every Q new speed detection values S are obtained). That is, after setting I2 = I2 + 1, I2 is reset to 0 if I2 = NxL. If such an operation is performed, I2 will be an integer between 0 and NxL-1. The initial value of I2 is NxL-1, and the initial value of L is a predetermined large integer. Further, the value of L is changed at any time by the reel cycle responsive means described later. (6) <Memory output value creating means> The integer J is made equal to I2 (J = I2), and Nx memory value groups M [J-nL (mod NxL)] are separated by L intervals in the RAM area.
Using (n = 1, ..., Nx), the memory output value V0 is created by the following equation. Here, the value of the ratio Wn is 0 <Wn <2 / Nx (n = 1, ..., Nx) (2), and Is standardized. Specifically, if Wn = 1 / Nx (n = 1, ..., Nx) (4) in the case of Nx ≧ 2, the equation (1) becomes the memory value group M [J−nL (mod Nx
L)] (n = 1, ..., Nx) is simply added and synthesized, and then Nx
It will be divided by (integer), which makes the calculation very simple. (7) <Synthesis error creation means> F [m] (m
= 0, 1, ..., Q−1) stores consecutive Q rotation errors. Of these, Fd (where Fd is an integer of 2 or more and Q or less) latest rotation error F [Q-m] (m = 1,
2, ..., Fd) with predetermined ratio Bm (m = 1,2, ...
・, Fd) is multiplied and the value is added and combined to generate a combined error Eg. That is, Here, the coefficient Bm has a relationship of Bm = BFd−m + 1 (m = 1,2, ..., Fd) (6). further, Have been standardized. (8) <Update / storing means> Memory output value V0 and synthesis error by the memory output value creating means
Eg is calculated and combined at a ratio of 1: 1 to calculate the updated value, and the second
Memory value M in the RAM area corresponding to the count variable I2 of
[I2] is updated (M [I2] = Eg + V0) and stored and saved until the next update. (9) <Reel period response means> The digital signal 1 of the reel rotation detector 13 is input and the reel rotation detection value Ld (digital value) corresponding to the signal 1 is obtained. Here, Ld is proportional to the rotation cycle of the reel. Next, the value of L (basic memory length) is the reel rotation detection value.
Change to Ld. After that, the operation returns to (1). With this configuration, the detection reel 11 (take-up reel
The rotation speed fluctuation of the cylinder motor 1 hardly occurs in response to the tension fluctuation generated in 11a or the supply reel 11b). This is because the reel cycle response means changes the basic memory length L to a value proportional to the rotation cycle of the detected reel at any time, and the number of memories NxL handled by the update storage means and the memory output value creation means changes, thereby improving the control characteristics. This is because it is possible to always match the frequency at which the noise appears in accordance with the frequency according to the rotation cycle of the detection reel (for the effect of improving the control characteristics, refer to the patent of the previous application). That is, regardless of the winding diameter of the detection reel 11, it is possible to always improve the control characteristic (disturbance suppression characteristic) of the cylinder motor at the frequency of the tension fluctuation of the detection reel 11. Therefore, even if the detection reel 11 undergoes a large tension fluctuation, the rotation speed of the cylinder motor 1 does not fluctuate. The influence of the tension fluctuation of the supply reel 11b is affected by the cylinder motor 1.
Therefore, it can be said that it is preferable to select the supply reel 11b as the detection reel 11 because it has occurred significantly. Further, as shown in the present embodiment, the control signal generating means generates a new control signal each time the speed detector obtains a new detection signal, and updates each time the speed detector obtains Q new detection signals. If the storage means is adapted to update one memory value, the number of memories required for the memory means is substantially reduced by a factor of Q. Even if the number of memories is reduced as described above, the effect of being extremely strong against the fluctuation of the tension of the detection reel (the effect of not causing the fluctuation of the rotation speed) is retained. This can be explained as follows. It was found that the frequency component (frequency of tension fluctuation) that needs to be improved by the operation of the memory means, the memory output value creating means, and the update saving means is considerably lower than the detection frequency of the speed detector. Therefore, even if the frequency of the detection signal of the speed detector used in the update storage means is reduced to 1 / Q, it is possible to prevent the above-mentioned improvement effect from being adversely affected. Further, as shown in the present embodiment, if the continuous Fd rotation errors are combined to obtain the combined error Eg and the combined value of the combined error Eg and the memory output value V0 is used to update the memory value M [I2]. Therefore, it was found that the operation can be prevented from becoming unstable due to unnecessary noise components included in the rotation error. This makes it possible to obtain the effect of preventing the influence of a considerably high-frequency fluctuation included in the rotation error from entering the memory value of the update saving means and the memory output value of the memory output value creating means by the combining error creating means. Because. Also,
Since the frequency component improved by the operation of the memory means, the memory output value creating means and the update dependent means is considerably lower than the detection frequency of the speed detector, even if the synthetic error creating means is inserted before the update saving means. There is almost no adverse effect on the above-mentioned improvement effect. FIG. 5 shows a flowchart of the program of the compensator 4 in consideration of the stability of the entire control system. Here, the method of calculating the update value in the update storing means, the number of preparations of the memory output value in the memory output value creating means, and the method of using the memory output value in the memory output value creating means in the control signal creating means are improved. is doing. In addition, 1 of the speed detector 3
The amount of calculation required in the detection cycle is also reduced. Next, the operation will be described in detail (the entire configuration is the same as that in FIG. 3, and the description is omitted). (11) <Rotation Error Detection Means> First, the arithmetic unit 5 inputs the output signal q of the flip-flop 40 of the speed detector 3 and waits for the signal q to become “H”. That is, it is monitored that the speed detector 3 detects the (half) cycle of the AC signal a and outputs a new digital signal b. When q becomes "H", the digital signal b of the speed detector 3 is read, the speed detection value S (digital value) corresponding to the digital signal b is read, and the reset signal r is set to "H" for a predetermined time to set the speed. The flip-flop 40 of the detector 3 is reset. The speed detection value S is subtracted from the predetermined reference value Sref, and the value is multiplied by R (where R is a predetermined positive constant) to obtain the rotation error E of the cylinder motor 1 at the present time.
Is calculated [E = R. (Sref-S)]. (12) <Control signal creating means> The memory output value V0 by the memory output value creating means, which will be described later, and the current rotation error E are arithmetically combined at a predetermined ratio D: 1,
The control signal value Y is calculated (Y = E + D · V0). The control signal value Y is output to the D / A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y. (13) <Saving the rotation error time series> A memory value F [I] corresponding to a first count variable I1 described later.
The current rotation error E is stored and saved in [1] (F [I
1] = E). (14) <First Counting Means> With Q as a mod, the first count variable I1 is incremented each time a new speed detection value S is obtained. I1 is
When it becomes equal to Qa (here, Qa is an integer smaller than Q), the memory output value V0 is changed to V [Px] described later, and when I1 is not equal to Qa, such a changing operation is not performed. As a result, V0 = V [Px−1] (described later) in the range of I1 <Qa, and V0 = V [Px] in the range of I1 ≧ Qa. Further, if I1 is 0, the operations of (15) and (16) are executed, and I1
If is 1, the operation of (17) is executed, and if I1 is 2, (18)
If the I1 is not 0, 1 or 2, the operation of (19) is executed. (15) <Second Counting Means> The first count variable I1 is 0 when Nx · L is mod.
Every 2 times (every Q new speed detection values S are obtained)
The count variable I2 of is incremented. (16) <Memory output value creating means> After the contents of the register variable V [m + 1] are sequentially transferred to V [m] (m = 0, 1, ..., Px−1), NxL is set to mod. The count variable I2 of 2 is Px (where Px is 1 or more and 3
The integer J below, preferably Px = 1)
Is calculated [J = I2 + Px (mod NxL)]. Memory value group M [J-nL (mod NxL)] (n = 1, ..., N) in the RAM area
x) is used to put the latest memory output value calculated in the following equation into V [Px]. Here, the value of Wn satisfies the expressions (2), (3) and (4). That is, V [Px] to V

A group of Px + 1 memory output values consecutive to [0] is obtained. At this time, V [P
Let x be the integer J in equation (8) when calculating

When the integer J in the equation (8) when calculating [0] is J2, there is a relation of 1 = J2 + Px. Next, the memory output value V0 used first in the control signal generating means is set to V [Px−
1] (V0 = V [Px-1]). Then, the operation returns to (11). (17) <Synthesis error creating means> F [m] (m
= 0, 1, ..., Q−1) stores consecutive Q rotation errors. Fd latest rotation error F [Q
-M] (m = 1, 1, ..., Fd) respectively has a predetermined ratio Bm
The values multiplied by (m = 1, 2, ..., Fd) are added and combined to generate a combined error Eg [Equations (5), (6), (7)]. Then, the operation returns to (11). (18) <Update / storing means> After transferring the contents of the register variable X [m + 1] to X [m] in order (m = 0,1,2, ..., 2Kd-1), X [2Kd]
(Where Kd is an integer, preferably Kd = 3), the old memory output value V created by the memory output value creating means

Insert the combined value obtained by arithmetically combining [0] and the combined error Eg at a ratio of 1: 1 (X [2Kd] = Eg + V

[0]). That is, from X [2Kd] to X

2Kd + 1 addition values (addition value of memory output value and synthesis error) consecutive to [0] are obtained. NxL to m
The integer K obtained by subtracting Kd from the second count variable I2 is calculated as od [K = I2-Kd (mod NxL)]. Next, X [m]
And a predetermined positive ratio Cm (m = 0,1, ..., 2Kd) are added and synthesized to obtain a new update value, and the memory value M [K] in the RAM area is updated at the time of the next update. Store up to save. That is, And Here, the ratio Cm has the following relationship. Cm = C2Kd-m (m = 0,1, ..., Kd) (10) Then, the operation returns to (11). (19) <Reel Period Response Means> The digital signal 1 of the reel rotation detector 13 is input and the reel rotation detection value Ld (digital value) corresponding to the signal 1 is obtained. Here, Ld is proportional to the rotation cycle of the reel. Next, the value of Ld is set to the above-mentioned L (basic memory length). Then, the operation returns to (11). As in the present embodiment, a calculation for taking a weighted average is inserted in the update storing means, or the first memory output value V0 (V [Px]) of the memory output value creating means used in the control signal creating means.
And the second memory output value V of the memory output value creating means used in the update storing means

A certain deviation (V
[Px] is V

If it is more advanced than [0],
It was confirmed that the operation of the entire control system was stable. In particular,
The values of Px and Qa related to the usage timing thereof are deeply related to the value of the number of operation terms Fd of the composite error creating means, and (QPx−Qa) ≧
I also found that it would be better to use (Q + Fd) / 2. this is,
The same memory output value (for example, V

When the use timing of the control signal creating means is converted into the number of detection times of the speed detector as compared with the use timing of the updating and storing means (value of [0]), (Q + F)
d) / Means to speed up twice or more. Further, as shown in this embodiment, when the operation of the memory output value creating means, the operation of the composite error creating means, and the operation of the update storing means are shifted in timing with respect to the detection signal of the speed detector, one detection of the speed detector is made. The amount of calculation required in a cycle is reduced. In particular, when a large number of transfers and multiplications are included in the operation of the memory output value creating means and the operation of the update storing means, there is an effect that the amount of calculation required in one detection cycle of the speed detector is reduced. It is large, and the restrictions on the operating speed of hardware are relaxed. Further, since the operation of the memory output value creating means is performed when I1 = 0, the memory output value V0 used in the control signal creating means is changed without delay. FIG. 6 shows a flowchart of another program of the compensator 4 in consideration of the stability of the entire control system. Here, the method of calculating the memory output value in the memory output value creating means and the number of preparations, and the way of using the memory output value of the memory output value creating means in the control signal creating means are improved. Also, the amount of calculation required within one detection cycle of the speed detector 3 is reduced. Next, the operation will be described in detail (the entire configuration is the same as that in FIG. 3, and the description is omitted). (21) <Rotation Error Detection Means> First, the arithmetic unit 5 receives the output signal q of the flip-flop 40 of the speed detector 3, and the signal q becomes “H”. That is, it is monitored that the speed detector 3 detects the (half) cycle of the AC signal a and outputs a new digital signal b. When q becomes "H", the digital signal b of the speed detector 3 is read, the speed detection value S (digital value) corresponding to the digital signal b is read, and the reset signal r is set to "H" for a predetermined time to set the speed. The flip-flop 40 of the detector 3 is reset. The speed detection value S is subtracted from the predetermined reference value Sref, and the value is multiplied by R (where R is a predetermined positive constant) to obtain the rotation error E of the cylinder motor 1 at the present time.
Is calculated [E = R. (Sref-S)]. (22) <Control signal creating means> The memory output value V0 by the memory output value creating means, which will be described later, and the current rotation error E are arithmetically combined at a predetermined ratio D: 1,
The control signal value Y is calculated (Y = E + D · V0). The control signal value Y is output to the D / A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y. (23) <Saving the rotation error time series> The memory value F [I] corresponding to a first count variable I1 described later.
The current rotation error E is stored and saved in [1] (F [I
1] = E). (24) <First Counting Means> With Q as a mod, the first count variable I1 is incremented each time a new speed detection value S is obtained. I1 is
When it becomes equal to Qa (here, Qa is an integer smaller than Q), the memory output value V0 is changed to V [Px] described later, and when I1 is not equal to Qa, such a changing operation is not performed. As a result, V0 = V [Px-1] (described later) in the range of I1 <Qa, and V0 = V [Px] in the range of I1 = Qa. Further, if I1 is 0, the operations of (25) and (26) are executed, and I1
If is 1, the operation of (27) is executed, and if I1 is 2, (28)
The operation of (29) is executed, and if I1 is not 0, 1 or 2, the operation of (29) is executed. (25) <Second Counting Means> The first count variable I1 is 0 when Nx · L is mod.
Every 2 times (every Q new speed detection values S are obtained)
The count variable I2 of is incremented. (26) <Memory output value creation means> After transferring the contents of the register variable X [m + 1] to X [m] in order (m = 0,1,2, ..., 2Kd-1), mod NxL Then, an integer J is calculated by adding Px + Kd (Px is an integer of 1 or more and 3 or less and Kd is an integer of 1 or more) to the second count variable I2 [J = I2 + Px + Qx (mod NxL)]. Nx memory value group M [J−nL (mod NxL)] (n = 1,
2, ..., Nx) and put the calculated value calculated by the following equation into X [2Kd]. Here, the value of Wn satisfies the expressions (2), (3), and (4). That is, from X [2Kd] to X

2Kd + 1 calculated values (calculated values obtained from Nx memory values separated by L intervals) consecutive to [0] are obtained. Next, after sequentially transferring the contents of the register variable V [m + 1] to V [m] (m = 0,1, ..., Px−1), X [m] (m = 0,1 ,.・
,, 2Kd) multiplied by a predetermined positive ratio Cm (m = 0,1, ..., 2Kd) to obtain the latest memory output value that is added and synthesized, and
Put in [Px]. Here, the ratio Cm has a relationship of equations (10) and (11). That is, V [Px] to V

Px + 1 memory output values consecutive to [0] are obtained. At this time, the integer J in the equation (12) when substantially calculating V [Px] is J1, and V is substantially

Let J1 be the integer J in equation (12) when calculating [0], and substantially

Let J2 be the integer J in the equation (12) when calculating [0].
Then, there is a relation of J1 = J2 + Px. That is, V [P
x] and V

There is a gap corresponding to the integer Px between [0].
Next, the memory output value V0 is set to V [Px−1] (V0 = V
[Px-1] (V0 = V [Px-1]). After that,
Return to the operation of (21). (27) <Synthesis error creation means> F [m] (m
= 0, 1, ..., Q−1) stores consecutive Q rotation errors. Fd latest rotation error F [Q
-M] (m = 1,2, ..., Fd) with a predetermined ratio Bm
The values multiplied by (m = 1, 2, ..., Fd) are added and combined to generate a combined error Eg [Equations (5), (6), (7)]. Then, the operation returns to (21). (28) <Update storage means> Old memory output value V created by the memory output value creation means

[0] and the composition error Eg are arithmetically combined at a ratio of 1: 1 to calculate an update value, and the memory value M [I2] in the RAM area corresponding to the second count variable I2 is updated (M [ I2] = Eg +
V

[0]), store and save until the next update. After that,
Return to the operation of (21). (29) <Reel Period Response Means> The digital signal 1 of the reel rotation detector 13 is input and the reel rotation detector Ld (digital value) corresponding to the signal 1 is obtained. Here, Ld is proportional to the rotation cycle of the reel. Next, the value of Ld is set to the above-mentioned L (basic memory length). Then, the operation returns to (21). As in the present embodiment, the first memory of the memory output value creating means used in the control signal creating means by inserting the operation for taking the weighted average and the operation for preparing a plurality of memory output values into the memory output value creating means. The output value V0 (V [Px]) and the second memory output value V of the memory output value creating means used in the update storing means

A certain deviation (V [Px] is V

If it is more advanced than [0], the operation of the entire control system becomes stable. Also in this case, (QPx−Qa) ≧
(Q + Fd) / 2 is better. The calculation by the ratio Wn and Cm is not limited to the above-mentioned form, and it is needless to say that various equivalent formula modifications are possible as long as they substantially realize the contents of the above-mentioned program. Yes. Also, when a new rotation error is obtained, the control signal creating means first outputs a new control signal, and then the memory output value creating means calculates the memory output value to be used at the next sampling time. In this case, the calculation time of the memory output value creating means can be lengthened and the time delay until the output of the control signal can be shortened, so that the stability of the control system can be easily ensured. In each of the above-described embodiments, the speed detector detects only the rotation speed of the cylinder motor, but in addition to this, the rotation phase of the cylinder motor is detected by a well-known phase detector, and both are combined to rotate. It goes without saying that it may be an error and is included in the present invention. In addition, the output of the compensator is a digital signal or PWM signal (pulse width modulation signal).
Alternatively, the output signal of the power amplifier (driving means) may be a PWM signal. A brushless DC cylinder motor may be used as the cylinder motor. In addition, PL the compensator
A complete programmable hardware such as A (programmable logic array) may be used to perform the same operation as the program described above. Alternatively, an analog arithmetic element may be used. Besides, various modifications can be made without changing the gist of the present invention. EFFECTS OF THE INVENTION In the cylinder motor control device of the present invention, fluctuations in rotation speed due to fluctuations in reel tension are significantly reduced, and the number of required memories is also significantly reduced. Therefore,
If a control device for a cylinder motor for a video tape recorder is constructed based on the present invention, a high performance video tape recorder can be economically obtained.

[Brief description of drawings]

FIG. 1 is a flow chart showing an example of a built-in program of the compensator shown in FIG. 3, FIG. 2 is a configuration diagram of a magnetic tape running system of a video tape recorder, and FIG. 3 is a whole control apparatus of a cylinder motor of the present invention. Configuration diagram, FIG. 4 is a specific configuration diagram of the speed detector of FIG. 3, FIG. 5 is a flow chart diagram showing another example of a built-in program of the compensator of the present invention, and FIG. 6 is compensation of the present invention. It is a flowchart figure showing the other example of the built-in program of a container. 1 ... Cylinder motor, 2 ... Rotation sensor, 3 ... Speed detector, 4 ... Compensator, 5 ... Computing unit, 6 ... Memory,
7 ... D / A converter, 8 ... power amplifier, 10 ... magnetic tape, 11 ... detection reel, 11a ... take-up reel, 11b ... supply reel, 12 ... reel rotation sensor, 13 ... Reel rotation detector.

Claims (10)

[Claims] 1. A rotation sensor for generating an AC signal having a cycle corresponding to the rotation speed of a cylinder motor, speed detection means for detecting a plurality of times per rotation of the cylinder motor by the AC signal of the rotation sensor, and the speed. Compensation means for producing a control signal based on the detection signal of the detection means, and drive means for driving the cylinder motor according to the control signal of the compensation means are provided, and the compensation means responds to the detection signal of the speed detection means. Rotation error detecting means for obtaining the rotation error, memory means for storing four or more memory values, and memory output value creation for producing a memory output value using at least one memory value stored in the memory means Means, a composite error creating means for creating a composite error by combining a plurality of rotation errors of the rotation error detecting means, and the memory output value creating means. Of the memory output value and the memory output value creation means, and the update value corresponding to the value obtained by arithmetically combining the memory output value and the composition error of the composition error creation means. A control signal generating means for arithmetically synthesizing the memory output value and the rotation error of the rotation error detecting means to generate the control signal, and a memory value handled by the update storing means or the memory output value generating means in accordance with the reel rotation cycle. And a reel cycle responsive means for increasing or decreasing the number of reels, each time the speed detecting means obtains a new detection signal, the control signal creating means creates a new control signal, and the speed detecting means produces Q new detection signals ( Here, the update storage means substantially updates one memory value each time Q is an integer of 2 or more). 2. The memory means stores NxL (where Nx is an integer of 1 or more and L is an integer of 4 or more) memory value groups M [0] to M [NxL-1], and update saving means is provided. Are sequentially M [0],
Claim [1], wherein M [1], ..., M [NxL-1] are updated in this order, and the value of L is changed by reel cycle responsive means. Cylinder motor controller. 3. A memory value group M [J-nL (mo
d NxL)] (n = 1, ..., Nx) (where J is an integer) is calculated, and a memory output value substantially corresponding to a value is calculated. The control device for a cylinder motor according to claim (2). 4. The memory output value creating means is Nx of the memory means.
Memory values M [J-nL (mod NxL)] (n = 1, ...,
Nx) (where J is an integer) to obtain a calculated value, and further, a value obtained by multiplying a plurality of consecutive calculated values for the integer J by a predetermined ratio is added and combined to output a memory. The control device for a cylinder motor according to claim (2), characterized in that the value is a value. 5. The update storage means obtains an added value obtained by adding the memory output value of the memory output value creating means and the rotation error of the rotation error detection means, and multiplies each of the plurality of consecutive added values by a predetermined ratio. The cylinder motor control device according to claim (2), wherein a value obtained by adding and synthesizing the values is stored and stored as a new update value in the memory value of the memory means. 6. The composite error creating means has a predetermined ratio Bm (m = 1, 2, ..., Fd) to a continuous Fd number of rotation errors (where Fd is an integer of 2 or more and Q or less). The control device for a cylinder motor according to claim (2), characterized in that a composite error is generated by adding and combining. 7. A cylinder motor control device according to claim 6, wherein Bm = BFd-m + 1 (m = 1, 2, ..., Fd). 8. The cylinder motor control device according to claim 1, wherein the reel cycle responsive means detects a rotation cycle of the supply reel. 9. At least two operations of the operation of the memory output value creating means, the operation of the composite error creating means and the operation of the update storing means are substantially different with respect to the timing of the detection signal of the speed detecting means. The cylinder motor control device according to claim (1). 10. The operation of the memory output value creating means is performed first, then the operation of the composite error creating means is performed, and thereafter,
The cylinder motor control device according to claim (9), characterized in that the update storage means is operated.