JPH0773431B2 - Compensator - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to compensators used in feedback loops.

2. Description of the Related Art As an example of feedback control, for example, a motor speed control device that detects the rotation speed of a motor by a speed detector and controls the electric power supplied to the motor by the detection signal is a capstan motor of a video tape recorder. It is widely used as a cylinder motor and a cylinder motor (for example, see Japanese Patent Application No. 56-142724 proposed by the present applicant). However, the compensator used in such a speed control device only performs the proportional / integral / derivative compensation conventionally used, and sufficiently suppresses the fluctuation of the rotation speed due to the fluctuation of the load torque. I couldn't.

In order to solve such a problem, the present applicant has filed Japanese Patent Application No.
In No. 229143 and Japanese Patent Application No. 60-229144, we proposed a high-performance motor speed controller that is extremely resistant to load torque fluctuations by using a compensator with a new structure.
That is, in Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-229144, a rotation sensor that generates an AC signal with a cycle corresponding to the rotation speed of the motor, and the motor
Speed detecting means for detecting a plurality of times per rotation, compensating means for calculating and storing a control signal based on the detection signal of the speed detecting means, and power corresponding to the control signal of the compensating means to the motor. A speed control system is configured by the power amplification means (driving means) to be supplied. Further, a rotation error detecting means for obtaining a rotation error in response to the detection signal of the speed detecting means, and NxL (plural) memory value groups M [0] to M [NxL
-1] and a memory value storing means (memory output value generating means) for substantially calculating a composite value calculated by using Nx memory value groups separated by L intervals of the memory means. An update storing means for updating and storing the memory value of the memory means substantially in order by the update value corresponding to the value obtained by arithmetically combining the combined value of the combined value calculating means and the rotation error of the rotation error detecting means; A high-performance motor speed control device is realized by using a compensating means (compensator) having a control signal generating means for arithmetically combining the combined value of the means and the rotation error of the rotation error detecting means to generate a control signal. is doing.

Problems to be Solved by the Invention However, Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-229144
In the compensator configuration used in the issue, it is essential to use a large number of digital memories, usually 16 bits × 10
A memory of about 00 words = 16 kbits is required. Although IC devices for memories have been rapidly reduced in price due to recent improvements in semiconductor manufacturing technology, it is not preferable to use a memory of 16 kbits because the cost is significantly increased.

In consideration of such a point, the present invention examined a compensator using many memories as shown in the above example, and drastically reduced the required number of memories without deteriorating the control performance. Is.

Means for Solving the Problems In the compensator of the present invention, error detection means for obtaining a digital error at each predetermined timing or substantially every predetermined timing,
Memory means for storing and storing Nx · L pieces (where Nx is an integer of 1 or more and L is an integer of 4 or more) and a plurality of digital errors of the error detecting means are arithmetically combined. The composite error creating means for creating a composite error and the composite error creating means of the Nx · L memory values are sequentially arranged at each update timing Q times the predetermined timing (where Q is an integer of 2 or more). Update saving means for updating and saving the combined error and the memory output value of the memory output value creating means by the update value obtained by operation combining, and at least 1 if Nx is 1.
Memory values are used, and when Nx is 2 or more, at least one set of Nx memory value groups whose update interval is L times or more of the update timing is used to output the memory in synchronization with the update timing. The memory output value creating means for creating a value, and the control signal creating means for creating a control signal by arithmetically synthesizing the digital error of the error detecting means and the memory output value of the memory output value creating means at every predetermined timing are provided. This solves the above problems.

In the present invention, by adopting the above configuration, for example, in the case of being applied to a speed control device of a motor, Japanese Patent Application No. 60-2291
As shown in Japanese Patent Application No. 43 and Japanese Patent Application No. 60-229144, it was possible to significantly reduce the influence of load torque fluctuation at a specific frequency. That is, an economically high-performance compensator is realized by using a small number (1 / Q) of the number of memories. of course,
The compensator according to the present invention can be applied to many control devices other than the motor speed control device, and the characteristic improving effect at a specific frequency can be obtained even in them. In addition, since the composite error that combines the plurality of digital errors of the error detecting means is created by the composite error creating means, and the composite error and the memory output value are arithmetically combined and the memory value is updated and stored, it is included in the digital error. It is possible to prevent the output (control signal) of the compensator from being disturbed by an unnecessary noise component that is generated or the operation of the entire control system from becoming unstable.

Embodiment Hereinafter, a compensator according to an embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing an example of a motor speed control device using the compensator of the present invention. In FIG. 2, the DC motor 1 directly drives the rotation sensor 2 and the load 10 to rotate. The rotation sensor 2 is Zq times per rotation as the motor 1 rotates (Zq is an integer of 2 or more. In a capstan motor of a video tape recorder, normally, Zq = 35.
The AC signal a of 7) is generated. The AC signal a of the rotation sensor 2 is input to the speed detector 3 to obtain a digital signal b corresponding to the cycle of the AC signal a.

FIG. 3 shows a specific configuration example of the speed detector 3. The AC signal a is waveform-shaped by the waveform shaping circuit 31 to obtain the shaped signal g. The shaping signal g is input to the AND circuit 33 and the flip-flop 35. On the input side of the AND circuit 33, the clock pulse p of the oscillation circuit 32 and the counter are further provided.
34 overflow output signals w are also input. The oscillating circuit 32 is composed of a crystal oscillator and a frequency divider, etc.
(About 500kHz) is generated. The counter 34 is a 12-bit up counter that counts up the contents of the output pulse h of the AND circuit 33 each time it arrives. The overflow output signal w is "H" when the counter content of the counter 34 is less than or equal to a predetermined value, and w changes to "L" when the count content of the counter 34 is greater than or equal to the predetermined value (here, "H"). Represents a high potential state, "L" represents a low potential state). The data input flip-flop 35 takes in "H" input to the data input terminal with the falling edge of the shaping signal g as a trigger signal, and outputs its output Q to "H".
(Q = “H”). Further, when the reset signal r from the compensator 4 becomes “H”, the counter 34 and the flip-flop 35.
The internal state of is reset (b = "LLLLLLLLLLLL",
w = “H”, q = “L”).

Next, the operation of the speed detector 3 shown in FIG. 3 will be described.
Now, it is assumed that the counter 34 and the flip-flop 35 are reset by the reset signal r. When the output signal g of the waveform shaping circuit 31 changes from “L” to “H”, the clock pulse p of the oscillation circuit 32 is output as the output signal h of the AND circuit 33.
Is output. The counter 34 counts the output signal h,
The internal state is changed. When the output signal g of the waveform shaping circuit 31 changes from "H" to "L", the output signal h of the AND circuit 33 becomes "L", and the counter 34 holds its internal state. Further, the flip-flop 35 takes in the data “H” at the falling edge of the signal g and outputs its output signal q.
Is changed from “L” to “H”. The digital signal b of the counter 34 is a value proportional to the (half) cycle length of the AC signal a of the rotation sensor 2 and inversely proportional to the rotation speed of the motor 1. The compensator 4, which will be described later, looks at the output signal q of the flip-flop 35, inputs the digital signal b of the counter 34 when q becomes “H”, and then outputs the reset signal r to “H” for a predetermined short time. Then, the counter 34 and the flip-flop 35 are reset to the initial state to prepare for the next speed detection operation. When the rotation speed of the motor 1 is too slow, the internal state of the counter 34 exceeds a predetermined value because the cycle of the output signal g of the waveform shaping circuit 31 is long, and the overflow output signal w changes from "H" to "L". In some cases, the output signal h of the AND circuit 33 becomes "L" and the counter 34 holds a predetermined large value.

The compensator 4 shown in FIG. 2 is composed of a computing unit 5, a memory 6 and a D / A converter 7. The digital signal b of the speed detector 3 is calculated and processed by a built-in program described later, and a control signal c is output. To do. The control signal c of the compensator 4 is the power amplifier 8
The driving signal d input to (driving means) and power-amplified
(Current proportional to the control signal c) is supplied to the motor 1. Therefore, the motor 1, the rotation sensor 2, the speed detector 3, the compensator 4, and the power amplifier 8 (driving means) constitute a speed control system, and the rotation speed of the motor 1 is controlled to a predetermined value.

The memory 6 of the compensator 4 is divided into a ROM area (ROM: read only memory) in which a predetermined program and constants are stored and a RAM area (RAM: random access memory) in which a required value is stored at any time. The computing unit 5 performs a predetermined operation or computation according to a program in the ROM area. FIG. 1 shows a concrete example of the program. Next, the operation will be described in detail.

(1) <Error detecting means 1A> First, the arithmetic unit 5 inputs the output signal q of the flip-flop 35 of the speed detector 3 and waits for the signal q to become "H". That is, it is monitored that the speed detector 3 detects the (half) cycle of the AC signal a and outputs a new digital signal b. When q becomes "H", the digital signal b of the speed detector 3 is read and converted into the speed detector S (digital value) corresponding to the digital signal b, and the reset signal r is set to "H" for a predetermined time to speed. The counter 34 and the flip-flop 35 of the detector 3 are reset. The speed detector S is subtracted from the predetermined reference value Sref, and the value is multiplied by R (where R is a predetermined positive constant) to calculate the rotation error E (digital error) of the motor 1 at the present time [ E = R. (Sref-S)]. That is, a new digital error E is obtained at every predetermined timing (every time the speed detector 3 outputs a new digital signal b) or at almost every predetermined timing.

(2) <Control signal creating means 1B> A memory output value V0, which will be described later, and a current digital error E are set to a predetermined ratio D: 1 (where D is a constant 0.5≤D≤1, preferably D = 1). Then, the control signal value Y is calculated (Y = E + D · V0). Control signal value Y is converted to D / A converter 7
To DC voltage corresponding to Y value (control signal)
Convert to.

(3) <Saving of digital error time series 1C> Memory value F [I corresponding to a first count variable I1 described later
The new digital error E at the present time is stored and saved in 1] (F [I1] = E).

(4) <First Counting Means 1D> Q (where Q is an integer of 2 or more) is mod (modulus),
Each time a new digital error E is obtained, the first count variable I1
Count up. That is, I1 = I1 + 1 (I1
If I1 = Q, then I1 is reset to 0. If such an operation is performed, I1 becomes an integer between 0 and Q-1. The initial value of I1 is 0
And If I1 is 0, the operation after (5) is executed, and if I1 is not 0, the operation returns to (1).

(5) <Synthesis error creating means 1E> F [m] is generated by the above digital error time series saving operation.
Q consecutive digital errors are stored in (m = 0, 1, ..., Q-1). Of these, Fd (where Fd is an integer of 2 or more and Q or less) latest digital error F [Q-
m] (m = 1,2, ..., Fd) to a predetermined ratio Bm
A value obtained by multiplying (m = 1, 2, ..., Fd) is added and combined to generate a combined error Eg. That is, Here, the coefficient Bm has a relationship of Bm = B Fd −m + 1 (m = 1,2, ..., Fd) (2). further, Have been standardized.

(6) <Second counting means 1F> Nx · L (generally, Nx is an integer of 1 or more, L is an integer of 4 or more. However, Nx is an integer of 2 or more and L is an integer multiple of (Zq / Q). Since such a case is preferable, a case where such a case will be described below) will be described as mod (modulus), and each time the first count variable I1 becomes 0 (a new digital error E is Q
The second count variable I2 is incremented each time a new number is obtained. That is, after setting I2 = I2 + 1, I2 is reset to 0 if I2 = NxL. If such an operation is performed, I2 will be an integer between 0 and NxL-1. The initial value of I2 is NxL-1.

(7) <Memory output value creating means 1G> The integer J is made equal to I2 (J = I2), and Nx memory value groups M [J-nL (mod NxL)] are separated by L intervals in the RAM area.
Using (n = 1, ..., Nx), a memory output value X0 is created by the following equation.

Here, the value of the ratio Wn is 0 <Wn <2 / Nx (n = 1, ..., Nx) (5), and Is standardized. Specifically, if Wn = 1 / Nx (n = 1, ..., Nx) (7) in the case of Nx ≧ 2, the equation (4) becomes the memory value group M [J−nL (mod Nx
L)] (n = 1, ..., Nx) is simply added and synthesized, and then Nx
It will be divided by (integer), which makes the calculation very simple.

(8) <Update storage unit 1H> The memory output value V0 and the composition error Eg are arithmetically combined at a ratio of 1: 1 to calculate the updated value, and the memory value in the RAM area corresponding to the second count variable I2. Update M [I2] (M [I2] = Eg
+ V0), Store and save until the next update. After that (1)
Return to operation.

The speed control device for a motor using the compensator of the present invention shown in this embodiment is extremely strong against a specific frequency component of the load torque fluctuation caused by the load 10 in FIG. (Japanese Patent Application No. Sho 60-229143, 60-229144). Furthermore, as shown in the present embodiment, the control signal creating means 1B creates a new control signal each time the error detecting means 1A obtains a new digital error, and the error detecting means
Every time 1A gets Q new digital error E, update storage means
By making 1H update one memory value,
The number of memories (required memory) updated and saved by the update saving means 1H can be reduced to 1 / Q. As described above, even if the number of memories is significantly reduced, it is possible to secure the effect of being extremely strong with respect to the specific frequency component of the load torque fluctuation (the effect of not causing the rotation speed fluctuation). It can be seen that when the value of L is increased, the frequency component improved by the above-mentioned compensator becomes considerably lower than the detection frequency of the speed detector, and the composite error Eg is calculated from the plurality of digital errors E.
And the memory value is updated and saved by using this combined error Eg, so that the update frequency of the update saving means 1H is 1 / Q.
This is because the stability of the control system and the above-described improvement effect can be prevented from being adversely affected even if the amount is extremely reduced.

Further, as shown in the present embodiment, the continuous Fd digital errors are combined to obtain the combined error Eg, and the memory value M [I2] is updated by the combined value of the combined error Eg and the memory output value V _0. Then, it was also found that it is possible to prevent the operation of the feedback control system from becoming unstable due to an unnecessary noise component included in the digital error E. This is because the combined error creating unit 1E prevents the influence of a considerably high frequency fluctuation included in the digital error E from entering the memory value of the update saving unit 1H and the memory output value of the memory output value creating unit 1G. Because I was able to get it.

Further, in the case of the motor speed control device using the compensator of the present invention, if the value of L is L = (Zq / Q) · k (where k is an integer of 1 or more). The effect of significantly suppressing the rotational speed fluctuation due to the load torque fluctuation in a cycle of k times (an integer times) of one rotation cycle of the motor 1 is obtained. Such an effect is very preferable in the case of a capstan motor of a video tape recorder. This will be described. Since the load of the capstan motor is magnetic tape or pinch roller, the load fluctuation generated by the load 10 is the motor 1
In addition to the component that is synchronized with the rotation of the motor 1 (periodic load fluctuation having one rotation of the motor 1 as a basic cycle), a load fluctuation component having a frequency lower than the rotation frequency of the motor 1 often occurs. Such load fluctuations cause fluctuations in the rotational speed of the capstan motor, causing wow and flutter of the tape speed. By the way, it has been found that such load fluctuations often have periodic fluctuations having a cycle that is an integral multiple of the cycle of one rotation of the motor 1. Therefore, due to the above-mentioned effect, a considerably low frequency fluctuation of the rotation speed of the motor 1 due to the load torque fluctuation can be effectively reduced.

FIG. 4 shows a program example of the compensator 4 of the present invention in consideration of the stability of the entire control system. Here, the calculation and method of the update value in the update storing means, the number of preparations of the memory output value in the memory output value creating means, and the method of using the memory output value of the memory output value creating means in the control signal creating means are improved. is doing. Next, the operation will be described in detail (the entire structure of the motor speed control device is the same as that in FIG. 2, and the description thereof will be omitted).

(11) <Error detecting means 4A> First, the arithmetic unit 5 inputs the output signal q of the flip-flop 35 of the speed detector 3 and waits for the signal q to become "H". That is, it is monitored that the speed detector 3 detects the (half) cycle of the AC signal a and outputs a new digital signal b. When q becomes "H", the digital signal b of the speed detector 3 is read, the speed detection value S (digital value) corresponding to the digital signal b is read, and the reset signal r is set to "H" for a predetermined time to set the speed. The counter 34 and the flip-flop 35 of the detector 3 are reset. The speed detection value S is subtracted from the predetermined reference value Sref, and the value is multiplied by R (where R is a predetermined positive constant) to calculate the rotation error E (digital error) of the motor 1 at the present time [ E = R. (Sref-S)]. That is, a new digital error E is obtained at every predetermined timing or almost every predetermined timing.

(12) <Control signal generating means 4B> A memory output value V0, which will be described later, and a current digital error E are arithmetically combined at a predetermined ratio D: 1 to calculate a control signal value Y (Y = E + D · V0). The control signal value Y is output to the D / A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y.

(13) <Saving of digital error time series 4C> Memory value F [I corresponding to a first count variable I1 described later
The new digital error E at the present time is stored and saved in 1] (F [I1] = E).

(14) <First Counting Means 4D> The first count variable I1 is incremented each time a new digital error E is obtained with Q as mad (modulus). I1
Becomes equal to Qa (here, Qa is an integer smaller than Q), the memory output value V0 is changed to V [Px] described later, and when I1 is not equal to Qa, such a changing operation is not performed. As a result, in the range of I1 <Qa, V0 = V [Px-1] (described later)
And V0 = V [Px] in the range of I1 ≧ Qa.
Further, if I1 is 0, the operation after (15) is executed, and if I1 is not 0, the operation returns to (11).

(15) <Synthesis error creating means 4E> F [m] by the above-mentioned digital error time series saving operation.
Q consecutive digital errors are stored in (m = 0, 1, ..., Q-1). The latest Fd digital errors F [Q-m] (m = 1,2, ..., Fd) are multiplied by a predetermined ratio Bm (m = 1,2, ..., Fd). The added values are added and combined to create a combined error Eg [(1), (2),
Expression (3)].

(16) <Second Counting Means 4F> The first count variable I1 is 0 when Nx · L is mod.
The second count variable I2 is incremented every time (each time a new digital error E is obtained).

(17) <Memory output value creating means 4G> After transferring the contents of the register variable V [m + 1] to V [m] in order (m = 0, 1, ..., Px−1), NxL is set as mod The second count variable 12 is Px (where Px is 1 or more and 3
The integer J below, preferably Px = 1)
Is calculated [J = I2 + Px (mod NxL)]. Memory value group M [J-nL (mod NxL)] (n = 1, ..., N) in the RAM area
Put the latest memory output value calculated by the following equation using x) into V [Px].

Here, the value of Wn satisfies the equations (5), (6) and (7). That is, a group of Px + 1 memory output values consecutive from V [Px] to V [0] is obtained. At this time, V [P
Let x be the integer J in equation (8) when calculating
When the integer J in the equation (8) when calculating [0] is J2, there is a relationship of J1 = J2 + Px. Next, the memory output value V0 used first in the control signal generating means is set to V [Px−
1] (V0 = V [Px-1]).

(18) <Update storing means 4H> After transferring the contents of the register variable X [m + 1] to X [m] in order (m = 0,1,2, ..., 2Kd-1), X [2Kd]
(Where Kd is an integer, preferably Kd = 3), the old memory output value V [0] created by the memory output value creating means and the composition error Eg are arithmetically combined at a ratio of 1: 1 Enter the value (X [2Kd] = Eg + V [0]). That is, 2Kd + 1 additional values consecutive from X [2Kd] to X [0] (addition value of memory output value and synthesis error) are obtained. NxL to m
As od, an integer K is calculated by subtracting Kd from the second count variable I2 [K = I2-Kd (mod NxL)]. Next, X [m]
And a predetermined positive ratio Cm (m = 0,1, ..., 2Kd) are added to obtain a new update value, which is used as the memory value M [K] in the RAM area at the next update. Store up to save. That is, And Here, the ratio Cm has the following relationship.

Cm = C2Kd-m (m = 0,1, ..., Kd) (10) Then, the operation returns to (11).

As in the present embodiment, the calculation for taking the weighted average is inserted into the update storage means 4H, or the first memory output value V0 (V0 of the memory output value generation means 4G used in the control signal generation means 4B is used.
[Px]) and the second memory output value V [0] of the memory output value creating means 4G used in the update storing means 4H is larger than V [0] by a predetermined deviation (V [Px]). It was confirmed that the operation of the entire control system would be stable if () was provided. In particular, the values of Px and Qa related to the use timing thereof are deeply related to the number of operation terms Fd of the composite error creating unit 4E, and (QPx
It was also found that it is better to make −Qa) ≧ (Q + Fd) / 2. This is because the use timing of the control signal producing means 4B is detected by the error detecting means 4A as compared with the use timing of the update storing means 4H of the same memory output value (for example, V [0]) of the memory output value producing means 4G. When converted to the number of times, it means (Q + Fd) / 2 or more times faster.

FIG. 5 shows another program example of the compensator 4 of the present invention in consideration of the stability of the entire control system. Here, the method of calculating the memory output value in the memory output value creating means and the number of preparations, and the way of using the memory output value of the memory output value creating means in the control signal creating means are improved.
Next, the operation will be described in detail (the entire structure of the motor speed control device is the same as that in FIG. 2, and the description thereof will be omitted).

(21) <Error detecting means 5A> First, the arithmetic unit 5 inputs the output signal q of the flip-flop 35 of the speed detector 3 and waits for the signal q to become "H". That is, it is monitored that the speed detector 3 detects the (half) cycle of the AC signal a and outputs a new digital signal b. When q becomes "H", the digital signal b of the speed detector 3 is read, the speed detection value S (digital value) corresponding to the digital signal b is read, and the reset signal r is set to "H" for a predetermined time to set the speed. The counter 34 and the flip-flop 35 of the detector 3 are reset. The speed detection value S is subtracted from the predetermined reference value Sref, and the value is multiplied by R (where R is a predetermined positive constant) to calculate the rotation error E (digital error) of the motor 1 at the present time [ E = R. (Sref-S)]. That is, a new digital error E is obtained at every predetermined timing or almost every predetermined timing.

(22) <Control signal generating means 5B> The memory output value V0, which will be described later, and the current digital error E are arithmetically combined at a predetermined ratio D: 1 to calculate a control signal value Y (Y = E + DV0). The control signal value Y is output to the D / A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y.

(23) <Saving of digital error time series 5C> Memory value F [I corresponding to a first count variable I1 described later
The new digital error E at the present time is stored and saved in 1] (F [I1] = E).

(24) <First Counting Means 5D> The first count variable I1 is incremented each time a new digital error E is obtained with Q as a mod. I1
Becomes equal to Qa (here, Qa is an integer smaller than Q), the memory output value V0 is changed to V [Px] described later, and when I1 is not equal to Qa, such a changing operation is not performed. As a result, in the range of I1 <Qa, V0 = V [Px-1] (described later)
And V0 = V [Px] in the range of I1 ≧ Qa.
Further, if I1 is 0, the operation after (25) is executed, and if I1 is not 0, the operation returns to (21).

(25) <Synthesis error creating means 5E> F [m] is generated by the digital error time series saving operation described above.
Q consecutive digital errors are stored in (m = 0, 1, ..., Q-1). The latest Fd digital errors F [Q-m] (m = 1,2, ..., Fd) are multiplied by a predetermined ratio Bm (m = 1,2, ..., Fd). The added values are added and combined to create a combined error Eg [(1), (2),
Expression (3)].

(26) <Second Counting Means 5F> The first count variable I1 is 0 when Nx · L is mod (modulus).
The second count variable I2 is incremented every time (each time a new digital error E is obtained).

(27) <Memory output value creating means 5G> After transferring the contents of the register variable X [m + 1] to X [m] in order (m = 0,1,2, ..., 2Kd-1), NxL is set. As the mod, an integer J is calculated by adding Px + Kd (Px is an integer of 1 or more and 3 or less and Kd is an integer of 1 or more) to the second count variable I2 (J = I2 + Px + Qx (mod NxL)]. Memory value group M [J−nL (mod NxL)] (n = 0,
,, Nx) and the calculated value calculated by the following equation is X
Put in [2Kd].

Here, the value of Wn satisfies the equations (5), (6) and (7). That is, 2Kd + 1 calculated values (calculated values obtained from Nx memory values separated by L intervals) consecutive from X [2Kd] to X [0] are obtained. Next, after sequentially transferring the contents of the register variable V [m + 1] to V [m] (m = 0,1, ..., Px−1), X [m] (m = 0,1 ,.・
,, 2Kd) multiplied by a predetermined positive ratio Cm (m = 0,1, ..., 2Kd) to obtain the latest memory output value that is added and synthesized, and
Put it in [Px].

Here, the ratio Cm has a relationship of equations (10) and (11). That is, Px + 1 memory output values consecutive from V [Px] to V [0] are obtained. At this time, the integer J in the equation (12) when substantially calculating V [Px] is set to J1, and substantially V
Assuming that the integer J in the equation (12) when calculating [0] is J2, there is a relation of J1 = J2 + Px. That is, V [Px] and V
There is a gap corresponding to the integer Px between [0]. Next, the memory output value V0 is set to V [Px−1] (V0 = V [Px−
1]).

(28) <Update storing means 5H> The old memory output value V [0] created by the memory output value creating means and the composition error Eg are arithmetically combined at a ratio of 1: 1 to calculate the updated value, and the second value is calculated. Update the memory value M [I2] in the RAM area corresponding to the count variable I2 of (M [I2] = Eg +
V [0]), stored and saved until the next update. After that,
Return to the operation of (21).

As in the present embodiment, the arithmetic operation for taking a weighted average and the arithmetic operation for preparing a plurality of memory output values are inserted in the memory output value creating means 5G, and the memory output value creating means 5G used in the control signal creating means 5B One memory output value V ₀ (V [Px])
And a predetermined deviation (V [Px] is ahead of V [0]) between the second memory output value V [0] of the memory output value creating means 5G used in the update storage means 5H. If so, the operation of the entire control system becomes stable. Again, (QP
It is better to make x−Qa) ≧ (Q + Fd) / 2.

The calculation by the ratio Wn and Cm is not limited to the above-mentioned form, and it is needless to say that various equivalent formula modifications are possible as long as they substantially realize the contents of the above-mentioned program. Yes. Further, when a new digital error is obtained, the control signal creating means first outputs a new control signal, and then the memory output value creating means determines the memory output value to be used at the next sampling time (timing). If the calculation is performed, the calculation time of the memory output value creating means can be lengthened and the time delay until the output of the control signal can be shortened, so that the stability of the control system can be easily ensured.

In each of the above-described embodiments, the compensator is configured by a software program, but the present invention is not limited to such a case, and is configured by complete hardware such as PLA (Programmable Logic Array), and You may make it perform the same operation as the operation by. Besides, various modifications can be made without changing the gist of the present invention.

EFFECTS OF THE INVENTION The compensator of the present invention significantly reduces the influence of load torque fluctuations at a plurality of specific frequencies, and uses a small number (1 / Q) of memory to provide an economically high-performance compensator. realizable. In addition, since the composite error that combines the plurality of digital errors of the error detecting means is created by the composite error creating means, and the composite error and the memory output value are arithmetically combined and the memory value is updated and stored, it is included in the digital error. It is possible to prevent the output (control signal) of the compensator from being disturbed by an unnecessary noise component that is generated or the operation of the entire control system from becoming unstable. Therefore, if the compensator of the present invention is used in a feedback loop to construct a control device, a control device having extremely high performance control characteristics can be obtained at low cost. For example, if it is used as a motor speed controller for a capstan motor of a video tape recorder, a high-performance motor speed controller can be economically constructed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow chart showing an example of a built-in program of the compensator of the present invention shown in FIG. 2, and FIG. 2 is an example of a motor speed control device using the compensator of the present invention. FIG. 3 is a block diagram showing the configuration, FIG. 3 is a block diagram showing a concrete configuration example of the speed detector of FIG. 2, and FIG. 4 is a flow chart diagram showing another example of a program built in the compensator of the present invention. FIG. 5 is a flow chart showing another example of the built-in program of the compensator of the present invention. 1 ... motor, 2 ... rotation sensor, 3 ... speed detector,
4 ... Compensator, 5 ... Calculator, 6 ... Memory, 7 ... D /
A converter, 8 ... Power amplifier, 10 ... Load, 1A, 4A, 5A ...
... Error detection means, 1B, 4B, 5B ... Control signal generation means, 1E, 4
E, 5E ... Composite error creation means, 1G, 4G, 5G ... Memory output value creation means, 1H, 4H, 5H ... Update storage means.

Claims (1)

[Claims] 1. An error detecting means for obtaining a digital error at every predetermined timing or substantially every predetermined timing, and Nx · L (where Nx is an integer of 1 or more and L is an integer of 4 or more) ordered. Memory means for storing and storing memory values, synthetic error creating means for producing a synthetic error by arithmetically synthesizing a plurality of digital errors of the error detecting means, and Q times the predetermined timing (where Q is an integer of 2 or more). ), The Nx · L memory values are sequentially updated and stored by the update value obtained by arithmetically combining the composite error of the composite error creating means and the memory output value of the memory output value creating means with each other. , Nx is 1, at least one memory value is used, and when Nx is 2 or more, at least one set of Nx memory value groups whose update interval is L times or more of the update timing is used. The above The memory output value creating means for creating the memory output value in synchronization with a new timing, and the control signal by arithmetically combining the digital error of the error detecting means and the memory output value of the memory output value creating means at every predetermined timing. And a control signal creating means for creating the compensator.